训练营PLSR题目
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_sdram.c
  4. * @author MCD Application Team
  5. * @brief SDRAM HAL module driver.
  6. * This file provides a generic firmware to drive SDRAM memories mounted
  7. * as external device.
  8. *
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2016 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. @verbatim
  21. ==============================================================================
  22. ##### How to use this driver #####
  23. ==============================================================================
  24. [..]
  25. This driver is a generic layered driver which contains a set of APIs used to
  26. control SDRAM memories. It uses the FMC layer functions to interface
  27. with SDRAM devices.
  28. The following sequence should be followed to configure the FMC to interface
  29. with SDRAM memories:
  30. (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
  31. SDRAM_HandleTypeDef hsdram
  32. (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
  33. values of the structure member.
  34. (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
  35. base register instance for NOR or SDRAM device
  36. (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
  37. FMC_SDRAM_TimingTypeDef Timing;
  38. and fill its fields with the allowed values of the structure member.
  39. (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
  40. performs the following sequence:
  41. (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
  42. (##) Control register configuration using the FMC SDRAM interface function
  43. FMC_SDRAM_Init()
  44. (##) Timing register configuration using the FMC SDRAM interface function
  45. FMC_SDRAM_Timing_Init()
  46. (##) Program the SDRAM external device by applying its initialization sequence
  47. according to the device plugged in your hardware. This step is mandatory
  48. for accessing the SDRAM device.
  49. (#) At this stage you can perform read/write accesses from/to the memory connected
  50. to the SDRAM Bank. You can perform either polling or DMA transfer using the
  51. following APIs:
  52. (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
  53. (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
  54. (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
  55. HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
  56. the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
  57. device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
  58. structure.
  59. (#) You can continuously monitor the SDRAM device HAL state by calling the function
  60. HAL_SDRAM_GetState()
  61. *** Callback registration ***
  62. =============================================
  63. [..]
  64. The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
  65. allows the user to configure dynamically the driver callbacks.
  66. Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
  67. it allows to register following callbacks:
  68. (+) MspInitCallback : SDRAM MspInit.
  69. (+) MspDeInitCallback : SDRAM MspDeInit.
  70. This function takes as parameters the HAL peripheral handle, the Callback ID
  71. and a pointer to the user callback function.
  72. Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
  73. weak (surcharged) function. It allows to reset following callbacks:
  74. (+) MspInitCallback : SDRAM MspInit.
  75. (+) MspDeInitCallback : SDRAM MspDeInit.
  76. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  77. By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
  78. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  79. Exception done for MspInit and MspDeInit callbacks that are respectively
  80. reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
  81. and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
  82. If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
  83. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  84. Callbacks can be registered/unregistered in READY state only.
  85. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  86. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  87. during the Init/DeInit.
  88. In that case first register the MspInit/MspDeInit user callbacks
  89. using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
  90. or HAL_SDRAM_Init function.
  91. When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
  92. not defined, the callback registering feature is not available
  93. and weak (surcharged) callbacks are used.
  94. @endverbatim
  95. ******************************************************************************
  96. */
  97. /* Includes ------------------------------------------------------------------*/
  98. #include "stm32f4xx_hal.h"
  99. #if defined(FMC_Bank5_6)
  100. /** @addtogroup STM32F4xx_HAL_Driver
  101. * @{
  102. */
  103. #ifdef HAL_SDRAM_MODULE_ENABLED
  104. /** @defgroup SDRAM SDRAM
  105. * @brief SDRAM driver modules
  106. * @{
  107. */
  108. /* Private typedef -----------------------------------------------------------*/
  109. /* Private define ------------------------------------------------------------*/
  110. /* Private macro -------------------------------------------------------------*/
  111. /* Private variables ---------------------------------------------------------*/
  112. /* Private function prototypes -----------------------------------------------*/
  113. static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
  114. static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
  115. static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
  116. /* Exported functions --------------------------------------------------------*/
  117. /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
  118. * @{
  119. */
  120. /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  121. * @brief Initialization and Configuration functions
  122. *
  123. @verbatim
  124. ==============================================================================
  125. ##### SDRAM Initialization and de_initialization functions #####
  126. ==============================================================================
  127. [..]
  128. This section provides functions allowing to initialize/de-initialize
  129. the SDRAM memory
  130. @endverbatim
  131. * @{
  132. */
  133. /**
  134. * @brief Performs the SDRAM device initialization sequence.
  135. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  136. * the configuration information for SDRAM module.
  137. * @param Timing Pointer to SDRAM control timing structure
  138. * @retval HAL status
  139. */
  140. HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
  141. {
  142. /* Check the SDRAM handle parameter */
  143. if (hsdram == NULL)
  144. {
  145. return HAL_ERROR;
  146. }
  147. if (hsdram->State == HAL_SDRAM_STATE_RESET)
  148. {
  149. /* Allocate lock resource and initialize it */
  150. hsdram->Lock = HAL_UNLOCKED;
  151. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  152. if (hsdram->MspInitCallback == NULL)
  153. {
  154. hsdram->MspInitCallback = HAL_SDRAM_MspInit;
  155. }
  156. hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
  157. hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
  158. hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
  159. /* Init the low level hardware */
  160. hsdram->MspInitCallback(hsdram);
  161. #else
  162. /* Initialize the low level hardware (MSP) */
  163. HAL_SDRAM_MspInit(hsdram);
  164. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  165. }
  166. /* Initialize the SDRAM controller state */
  167. hsdram->State = HAL_SDRAM_STATE_BUSY;
  168. /* Initialize SDRAM control Interface */
  169. (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
  170. /* Initialize SDRAM timing Interface */
  171. (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
  172. /* Update the SDRAM controller state */
  173. hsdram->State = HAL_SDRAM_STATE_READY;
  174. return HAL_OK;
  175. }
  176. /**
  177. * @brief Perform the SDRAM device initialization sequence.
  178. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  179. * the configuration information for SDRAM module.
  180. * @retval HAL status
  181. */
  182. HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
  183. {
  184. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  185. if (hsdram->MspDeInitCallback == NULL)
  186. {
  187. hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
  188. }
  189. /* DeInit the low level hardware */
  190. hsdram->MspDeInitCallback(hsdram);
  191. #else
  192. /* Initialize the low level hardware (MSP) */
  193. HAL_SDRAM_MspDeInit(hsdram);
  194. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  195. /* Configure the SDRAM registers with their reset values */
  196. (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
  197. /* Reset the SDRAM controller state */
  198. hsdram->State = HAL_SDRAM_STATE_RESET;
  199. /* Release Lock */
  200. __HAL_UNLOCK(hsdram);
  201. return HAL_OK;
  202. }
  203. /**
  204. * @brief SDRAM MSP Init.
  205. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  206. * the configuration information for SDRAM module.
  207. * @retval None
  208. */
  209. __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
  210. {
  211. /* Prevent unused argument(s) compilation warning */
  212. UNUSED(hsdram);
  213. /* NOTE: This function Should not be modified, when the callback is needed,
  214. the HAL_SDRAM_MspInit could be implemented in the user file
  215. */
  216. }
  217. /**
  218. * @brief SDRAM MSP DeInit.
  219. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  220. * the configuration information for SDRAM module.
  221. * @retval None
  222. */
  223. __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
  224. {
  225. /* Prevent unused argument(s) compilation warning */
  226. UNUSED(hsdram);
  227. /* NOTE: This function Should not be modified, when the callback is needed,
  228. the HAL_SDRAM_MspDeInit could be implemented in the user file
  229. */
  230. }
  231. /**
  232. * @brief This function handles SDRAM refresh error interrupt request.
  233. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  234. * the configuration information for SDRAM module.
  235. * @retval HAL status
  236. */
  237. void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
  238. {
  239. /* Check SDRAM interrupt Rising edge flag */
  240. if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
  241. {
  242. /* SDRAM refresh error interrupt callback */
  243. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  244. hsdram->RefreshErrorCallback(hsdram);
  245. #else
  246. HAL_SDRAM_RefreshErrorCallback(hsdram);
  247. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  248. /* Clear SDRAM refresh error interrupt pending bit */
  249. __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
  250. }
  251. }
  252. /**
  253. * @brief SDRAM Refresh error callback.
  254. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  255. * the configuration information for SDRAM module.
  256. * @retval None
  257. */
  258. __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
  259. {
  260. /* Prevent unused argument(s) compilation warning */
  261. UNUSED(hsdram);
  262. /* NOTE: This function Should not be modified, when the callback is needed,
  263. the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
  264. */
  265. }
  266. /**
  267. * @brief DMA transfer complete callback.
  268. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  269. * the configuration information for the specified DMA module.
  270. * @retval None
  271. */
  272. __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
  273. {
  274. /* Prevent unused argument(s) compilation warning */
  275. UNUSED(hdma);
  276. /* NOTE: This function Should not be modified, when the callback is needed,
  277. the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
  278. */
  279. }
  280. /**
  281. * @brief DMA transfer complete error callback.
  282. * @param hdma DMA handle
  283. * @retval None
  284. */
  285. __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
  286. {
  287. /* Prevent unused argument(s) compilation warning */
  288. UNUSED(hdma);
  289. /* NOTE: This function Should not be modified, when the callback is needed,
  290. the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
  291. */
  292. }
  293. /**
  294. * @}
  295. */
  296. /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
  297. * @brief Input Output and memory control functions
  298. *
  299. @verbatim
  300. ==============================================================================
  301. ##### SDRAM Input and Output functions #####
  302. ==============================================================================
  303. [..]
  304. This section provides functions allowing to use and control the SDRAM memory
  305. @endverbatim
  306. * @{
  307. */
  308. /**
  309. * @brief Reads 8-bit data buffer from the SDRAM memory.
  310. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  311. * the configuration information for SDRAM module.
  312. * @param pAddress Pointer to read start address
  313. * @param pDstBuffer Pointer to destination buffer
  314. * @param BufferSize Size of the buffer to read from memory
  315. * @retval HAL status
  316. */
  317. HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
  318. uint32_t BufferSize)
  319. {
  320. uint32_t size;
  321. __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
  322. uint8_t *pdestbuff = pDstBuffer;
  323. HAL_SDRAM_StateTypeDef state = hsdram->State;
  324. /* Check the SDRAM controller state */
  325. if (state == HAL_SDRAM_STATE_BUSY)
  326. {
  327. return HAL_BUSY;
  328. }
  329. else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  330. {
  331. /* Process Locked */
  332. __HAL_LOCK(hsdram);
  333. /* Update the SDRAM controller state */
  334. hsdram->State = HAL_SDRAM_STATE_BUSY;
  335. /* Read data from source */
  336. for (size = BufferSize; size != 0U; size--)
  337. {
  338. *pdestbuff = *(__IO uint8_t *)pSdramAddress;
  339. pdestbuff++;
  340. pSdramAddress++;
  341. }
  342. /* Update the SDRAM controller state */
  343. hsdram->State = state;
  344. /* Process Unlocked */
  345. __HAL_UNLOCK(hsdram);
  346. }
  347. else
  348. {
  349. return HAL_ERROR;
  350. }
  351. return HAL_OK;
  352. }
  353. /**
  354. * @brief Writes 8-bit data buffer to SDRAM memory.
  355. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  356. * the configuration information for SDRAM module.
  357. * @param pAddress Pointer to write start address
  358. * @param pSrcBuffer Pointer to source buffer to write
  359. * @param BufferSize Size of the buffer to write to memory
  360. * @retval HAL status
  361. */
  362. HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
  363. uint32_t BufferSize)
  364. {
  365. uint32_t size;
  366. __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
  367. uint8_t *psrcbuff = pSrcBuffer;
  368. /* Check the SDRAM controller state */
  369. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  370. {
  371. return HAL_BUSY;
  372. }
  373. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  374. {
  375. /* Process Locked */
  376. __HAL_LOCK(hsdram);
  377. /* Update the SDRAM controller state */
  378. hsdram->State = HAL_SDRAM_STATE_BUSY;
  379. /* Write data to memory */
  380. for (size = BufferSize; size != 0U; size--)
  381. {
  382. *(__IO uint8_t *)pSdramAddress = *psrcbuff;
  383. psrcbuff++;
  384. pSdramAddress++;
  385. }
  386. /* Update the SDRAM controller state */
  387. hsdram->State = HAL_SDRAM_STATE_READY;
  388. /* Process Unlocked */
  389. __HAL_UNLOCK(hsdram);
  390. }
  391. else
  392. {
  393. return HAL_ERROR;
  394. }
  395. return HAL_OK;
  396. }
  397. /**
  398. * @brief Reads 16-bit data buffer from the SDRAM memory.
  399. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  400. * the configuration information for SDRAM module.
  401. * @param pAddress Pointer to read start address
  402. * @param pDstBuffer Pointer to destination buffer
  403. * @param BufferSize Size of the buffer to read from memory
  404. * @retval HAL status
  405. */
  406. HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
  407. uint32_t BufferSize)
  408. {
  409. uint32_t size;
  410. __IO uint32_t *pSdramAddress = pAddress;
  411. uint16_t *pdestbuff = pDstBuffer;
  412. HAL_SDRAM_StateTypeDef state = hsdram->State;
  413. /* Check the SDRAM controller state */
  414. if (state == HAL_SDRAM_STATE_BUSY)
  415. {
  416. return HAL_BUSY;
  417. }
  418. else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  419. {
  420. /* Process Locked */
  421. __HAL_LOCK(hsdram);
  422. /* Update the SDRAM controller state */
  423. hsdram->State = HAL_SDRAM_STATE_BUSY;
  424. /* Read data from memory */
  425. for (size = BufferSize; size >= 2U ; size -= 2U)
  426. {
  427. *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
  428. pdestbuff++;
  429. *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
  430. pdestbuff++;
  431. pSdramAddress++;
  432. }
  433. /* Read last 16-bits if size is not 32-bits multiple */
  434. if ((BufferSize % 2U) != 0U)
  435. {
  436. *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
  437. }
  438. /* Update the SDRAM controller state */
  439. hsdram->State = state;
  440. /* Process Unlocked */
  441. __HAL_UNLOCK(hsdram);
  442. }
  443. else
  444. {
  445. return HAL_ERROR;
  446. }
  447. return HAL_OK;
  448. }
  449. /**
  450. * @brief Writes 16-bit data buffer to SDRAM memory.
  451. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  452. * the configuration information for SDRAM module.
  453. * @param pAddress Pointer to write start address
  454. * @param pSrcBuffer Pointer to source buffer to write
  455. * @param BufferSize Size of the buffer to write to memory
  456. * @retval HAL status
  457. */
  458. HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
  459. uint32_t BufferSize)
  460. {
  461. uint32_t size;
  462. __IO uint32_t *psdramaddress = pAddress;
  463. uint16_t *psrcbuff = pSrcBuffer;
  464. /* Check the SDRAM controller state */
  465. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  466. {
  467. return HAL_BUSY;
  468. }
  469. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  470. {
  471. /* Process Locked */
  472. __HAL_LOCK(hsdram);
  473. /* Update the SDRAM controller state */
  474. hsdram->State = HAL_SDRAM_STATE_BUSY;
  475. /* Write data to memory */
  476. for (size = BufferSize; size >= 2U ; size -= 2U)
  477. {
  478. *psdramaddress = (uint32_t)(*psrcbuff);
  479. psrcbuff++;
  480. *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
  481. psrcbuff++;
  482. psdramaddress++;
  483. }
  484. /* Write last 16-bits if size is not 32-bits multiple */
  485. if ((BufferSize % 2U) != 0U)
  486. {
  487. *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
  488. }
  489. /* Update the SDRAM controller state */
  490. hsdram->State = HAL_SDRAM_STATE_READY;
  491. /* Process Unlocked */
  492. __HAL_UNLOCK(hsdram);
  493. }
  494. else
  495. {
  496. return HAL_ERROR;
  497. }
  498. return HAL_OK;
  499. }
  500. /**
  501. * @brief Reads 32-bit data buffer from the SDRAM memory.
  502. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  503. * the configuration information for SDRAM module.
  504. * @param pAddress Pointer to read start address
  505. * @param pDstBuffer Pointer to destination buffer
  506. * @param BufferSize Size of the buffer to read from memory
  507. * @retval HAL status
  508. */
  509. HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
  510. uint32_t BufferSize)
  511. {
  512. uint32_t size;
  513. __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
  514. uint32_t *pdestbuff = pDstBuffer;
  515. HAL_SDRAM_StateTypeDef state = hsdram->State;
  516. /* Check the SDRAM controller state */
  517. if (state == HAL_SDRAM_STATE_BUSY)
  518. {
  519. return HAL_BUSY;
  520. }
  521. else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  522. {
  523. /* Process Locked */
  524. __HAL_LOCK(hsdram);
  525. /* Update the SDRAM controller state */
  526. hsdram->State = HAL_SDRAM_STATE_BUSY;
  527. /* Read data from source */
  528. for (size = BufferSize; size != 0U; size--)
  529. {
  530. *pdestbuff = *(__IO uint32_t *)pSdramAddress;
  531. pdestbuff++;
  532. pSdramAddress++;
  533. }
  534. /* Update the SDRAM controller state */
  535. hsdram->State = state;
  536. /* Process Unlocked */
  537. __HAL_UNLOCK(hsdram);
  538. }
  539. else
  540. {
  541. return HAL_ERROR;
  542. }
  543. return HAL_OK;
  544. }
  545. /**
  546. * @brief Writes 32-bit data buffer to SDRAM memory.
  547. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  548. * the configuration information for SDRAM module.
  549. * @param pAddress Pointer to write start address
  550. * @param pSrcBuffer Pointer to source buffer to write
  551. * @param BufferSize Size of the buffer to write to memory
  552. * @retval HAL status
  553. */
  554. HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
  555. uint32_t BufferSize)
  556. {
  557. uint32_t size;
  558. __IO uint32_t *pSdramAddress = pAddress;
  559. uint32_t *psrcbuff = pSrcBuffer;
  560. /* Check the SDRAM controller state */
  561. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  562. {
  563. return HAL_BUSY;
  564. }
  565. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  566. {
  567. /* Process Locked */
  568. __HAL_LOCK(hsdram);
  569. /* Update the SDRAM controller state */
  570. hsdram->State = HAL_SDRAM_STATE_BUSY;
  571. /* Write data to memory */
  572. for (size = BufferSize; size != 0U; size--)
  573. {
  574. *pSdramAddress = *psrcbuff;
  575. psrcbuff++;
  576. pSdramAddress++;
  577. }
  578. /* Update the SDRAM controller state */
  579. hsdram->State = HAL_SDRAM_STATE_READY;
  580. /* Process Unlocked */
  581. __HAL_UNLOCK(hsdram);
  582. }
  583. else
  584. {
  585. return HAL_ERROR;
  586. }
  587. return HAL_OK;
  588. }
  589. /**
  590. * @brief Reads a Words data from the SDRAM memory using DMA transfer.
  591. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  592. * the configuration information for SDRAM module.
  593. * @param pAddress Pointer to read start address
  594. * @param pDstBuffer Pointer to destination buffer
  595. * @param BufferSize Size of the buffer to read from memory
  596. * @retval HAL status
  597. */
  598. HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
  599. uint32_t BufferSize)
  600. {
  601. HAL_StatusTypeDef status;
  602. HAL_SDRAM_StateTypeDef state = hsdram->State;
  603. /* Check the SDRAM controller state */
  604. if (state == HAL_SDRAM_STATE_BUSY)
  605. {
  606. status = HAL_BUSY;
  607. }
  608. else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  609. {
  610. /* Process Locked */
  611. __HAL_LOCK(hsdram);
  612. /* Update the SDRAM controller state */
  613. hsdram->State = HAL_SDRAM_STATE_BUSY;
  614. /* Configure DMA user callbacks */
  615. if (state == HAL_SDRAM_STATE_READY)
  616. {
  617. hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
  618. }
  619. else
  620. {
  621. hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
  622. }
  623. hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
  624. /* Enable the DMA Stream */
  625. status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
  626. /* Process Unlocked */
  627. __HAL_UNLOCK(hsdram);
  628. }
  629. else
  630. {
  631. status = HAL_ERROR;
  632. }
  633. return status;
  634. }
  635. /**
  636. * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
  637. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  638. * the configuration information for SDRAM module.
  639. * @param pAddress Pointer to write start address
  640. * @param pSrcBuffer Pointer to source buffer to write
  641. * @param BufferSize Size of the buffer to write to memory
  642. * @retval HAL status
  643. */
  644. HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
  645. uint32_t BufferSize)
  646. {
  647. HAL_StatusTypeDef status;
  648. /* Check the SDRAM controller state */
  649. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  650. {
  651. status = HAL_BUSY;
  652. }
  653. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  654. {
  655. /* Process Locked */
  656. __HAL_LOCK(hsdram);
  657. /* Update the SDRAM controller state */
  658. hsdram->State = HAL_SDRAM_STATE_BUSY;
  659. /* Configure DMA user callbacks */
  660. hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
  661. hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
  662. /* Enable the DMA Stream */
  663. status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
  664. /* Process Unlocked */
  665. __HAL_UNLOCK(hsdram);
  666. }
  667. else
  668. {
  669. status = HAL_ERROR;
  670. }
  671. return status;
  672. }
  673. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  674. /**
  675. * @brief Register a User SDRAM Callback
  676. * To be used instead of the weak (surcharged) predefined callback
  677. * @param hsdram : SDRAM handle
  678. * @param CallbackId : ID of the callback to be registered
  679. * This parameter can be one of the following values:
  680. * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
  681. * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
  682. * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
  683. * @param pCallback : pointer to the Callback function
  684. * @retval status
  685. */
  686. HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
  687. pSDRAM_CallbackTypeDef pCallback)
  688. {
  689. HAL_StatusTypeDef status = HAL_OK;
  690. HAL_SDRAM_StateTypeDef state;
  691. if (pCallback == NULL)
  692. {
  693. return HAL_ERROR;
  694. }
  695. /* Process locked */
  696. __HAL_LOCK(hsdram);
  697. state = hsdram->State;
  698. if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  699. {
  700. switch (CallbackId)
  701. {
  702. case HAL_SDRAM_MSP_INIT_CB_ID :
  703. hsdram->MspInitCallback = pCallback;
  704. break;
  705. case HAL_SDRAM_MSP_DEINIT_CB_ID :
  706. hsdram->MspDeInitCallback = pCallback;
  707. break;
  708. case HAL_SDRAM_REFRESH_ERR_CB_ID :
  709. hsdram->RefreshErrorCallback = pCallback;
  710. break;
  711. default :
  712. /* update return status */
  713. status = HAL_ERROR;
  714. break;
  715. }
  716. }
  717. else if (hsdram->State == HAL_SDRAM_STATE_RESET)
  718. {
  719. switch (CallbackId)
  720. {
  721. case HAL_SDRAM_MSP_INIT_CB_ID :
  722. hsdram->MspInitCallback = pCallback;
  723. break;
  724. case HAL_SDRAM_MSP_DEINIT_CB_ID :
  725. hsdram->MspDeInitCallback = pCallback;
  726. break;
  727. default :
  728. /* update return status */
  729. status = HAL_ERROR;
  730. break;
  731. }
  732. }
  733. else
  734. {
  735. /* update return status */
  736. status = HAL_ERROR;
  737. }
  738. /* Release Lock */
  739. __HAL_UNLOCK(hsdram);
  740. return status;
  741. }
  742. /**
  743. * @brief Unregister a User SDRAM Callback
  744. * SDRAM Callback is redirected to the weak (surcharged) predefined callback
  745. * @param hsdram : SDRAM handle
  746. * @param CallbackId : ID of the callback to be unregistered
  747. * This parameter can be one of the following values:
  748. * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
  749. * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
  750. * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
  751. * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
  752. * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
  753. * @retval status
  754. */
  755. HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
  756. {
  757. HAL_StatusTypeDef status = HAL_OK;
  758. HAL_SDRAM_StateTypeDef state;
  759. /* Process locked */
  760. __HAL_LOCK(hsdram);
  761. state = hsdram->State;
  762. if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  763. {
  764. switch (CallbackId)
  765. {
  766. case HAL_SDRAM_MSP_INIT_CB_ID :
  767. hsdram->MspInitCallback = HAL_SDRAM_MspInit;
  768. break;
  769. case HAL_SDRAM_MSP_DEINIT_CB_ID :
  770. hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
  771. break;
  772. case HAL_SDRAM_REFRESH_ERR_CB_ID :
  773. hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
  774. break;
  775. case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
  776. hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
  777. break;
  778. case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
  779. hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
  780. break;
  781. default :
  782. /* update return status */
  783. status = HAL_ERROR;
  784. break;
  785. }
  786. }
  787. else if (hsdram->State == HAL_SDRAM_STATE_RESET)
  788. {
  789. switch (CallbackId)
  790. {
  791. case HAL_SDRAM_MSP_INIT_CB_ID :
  792. hsdram->MspInitCallback = HAL_SDRAM_MspInit;
  793. break;
  794. case HAL_SDRAM_MSP_DEINIT_CB_ID :
  795. hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
  796. break;
  797. default :
  798. /* update return status */
  799. status = HAL_ERROR;
  800. break;
  801. }
  802. }
  803. else
  804. {
  805. /* update return status */
  806. status = HAL_ERROR;
  807. }
  808. /* Release Lock */
  809. __HAL_UNLOCK(hsdram);
  810. return status;
  811. }
  812. /**
  813. * @brief Register a User SDRAM Callback for DMA transfers
  814. * To be used instead of the weak (surcharged) predefined callback
  815. * @param hsdram : SDRAM handle
  816. * @param CallbackId : ID of the callback to be registered
  817. * This parameter can be one of the following values:
  818. * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
  819. * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
  820. * @param pCallback : pointer to the Callback function
  821. * @retval status
  822. */
  823. HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
  824. pSDRAM_DmaCallbackTypeDef pCallback)
  825. {
  826. HAL_StatusTypeDef status = HAL_OK;
  827. HAL_SDRAM_StateTypeDef state;
  828. if (pCallback == NULL)
  829. {
  830. return HAL_ERROR;
  831. }
  832. /* Process locked */
  833. __HAL_LOCK(hsdram);
  834. state = hsdram->State;
  835. if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
  836. {
  837. switch (CallbackId)
  838. {
  839. case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
  840. hsdram->DmaXferCpltCallback = pCallback;
  841. break;
  842. case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
  843. hsdram->DmaXferErrorCallback = pCallback;
  844. break;
  845. default :
  846. /* update return status */
  847. status = HAL_ERROR;
  848. break;
  849. }
  850. }
  851. else
  852. {
  853. /* update return status */
  854. status = HAL_ERROR;
  855. }
  856. /* Release Lock */
  857. __HAL_UNLOCK(hsdram);
  858. return status;
  859. }
  860. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  861. /**
  862. * @}
  863. */
  864. /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
  865. * @brief management functions
  866. *
  867. @verbatim
  868. ==============================================================================
  869. ##### SDRAM Control functions #####
  870. ==============================================================================
  871. [..]
  872. This subsection provides a set of functions allowing to control dynamically
  873. the SDRAM interface.
  874. @endverbatim
  875. * @{
  876. */
  877. /**
  878. * @brief Enables dynamically SDRAM write protection.
  879. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  880. * the configuration information for SDRAM module.
  881. * @retval HAL status
  882. */
  883. HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
  884. {
  885. /* Check the SDRAM controller state */
  886. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  887. {
  888. return HAL_BUSY;
  889. }
  890. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  891. {
  892. /* Update the SDRAM state */
  893. hsdram->State = HAL_SDRAM_STATE_BUSY;
  894. /* Enable write protection */
  895. (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
  896. /* Update the SDRAM state */
  897. hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
  898. }
  899. else
  900. {
  901. return HAL_ERROR;
  902. }
  903. return HAL_OK;
  904. }
  905. /**
  906. * @brief Disables dynamically SDRAM write protection.
  907. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  908. * the configuration information for SDRAM module.
  909. * @retval HAL status
  910. */
  911. HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
  912. {
  913. HAL_SDRAM_StateTypeDef state = hsdram->State;
  914. /* Check the SDRAM controller state */
  915. if (state == HAL_SDRAM_STATE_BUSY)
  916. {
  917. return HAL_BUSY;
  918. }
  919. else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
  920. {
  921. /* Update the SDRAM state */
  922. hsdram->State = HAL_SDRAM_STATE_BUSY;
  923. /* Disable write protection */
  924. (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
  925. /* Update the SDRAM state */
  926. hsdram->State = HAL_SDRAM_STATE_READY;
  927. }
  928. else
  929. {
  930. return HAL_ERROR;
  931. }
  932. return HAL_OK;
  933. }
  934. /**
  935. * @brief Sends Command to the SDRAM bank.
  936. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  937. * the configuration information for SDRAM module.
  938. * @param Command SDRAM command structure
  939. * @param Timeout Timeout duration
  940. * @retval HAL status
  941. */
  942. HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
  943. uint32_t Timeout)
  944. {
  945. HAL_SDRAM_StateTypeDef state = hsdram->State;
  946. /* Check the SDRAM controller state */
  947. if (state == HAL_SDRAM_STATE_BUSY)
  948. {
  949. return HAL_BUSY;
  950. }
  951. else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
  952. {
  953. /* Update the SDRAM state */
  954. hsdram->State = HAL_SDRAM_STATE_BUSY;
  955. /* Send SDRAM command */
  956. (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
  957. /* Update the SDRAM controller state state */
  958. if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
  959. {
  960. hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
  961. }
  962. else
  963. {
  964. hsdram->State = HAL_SDRAM_STATE_READY;
  965. }
  966. }
  967. else
  968. {
  969. return HAL_ERROR;
  970. }
  971. return HAL_OK;
  972. }
  973. /**
  974. * @brief Programs the SDRAM Memory Refresh rate.
  975. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  976. * the configuration information for SDRAM module.
  977. * @param RefreshRate The SDRAM refresh rate value
  978. * @retval HAL status
  979. */
  980. HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
  981. {
  982. /* Check the SDRAM controller state */
  983. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  984. {
  985. return HAL_BUSY;
  986. }
  987. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  988. {
  989. /* Update the SDRAM state */
  990. hsdram->State = HAL_SDRAM_STATE_BUSY;
  991. /* Program the refresh rate */
  992. (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
  993. /* Update the SDRAM state */
  994. hsdram->State = HAL_SDRAM_STATE_READY;
  995. }
  996. else
  997. {
  998. return HAL_ERROR;
  999. }
  1000. return HAL_OK;
  1001. }
  1002. /**
  1003. * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
  1004. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  1005. * the configuration information for SDRAM module.
  1006. * @param AutoRefreshNumber The SDRAM auto Refresh number
  1007. * @retval HAL status
  1008. */
  1009. HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
  1010. {
  1011. /* Check the SDRAM controller state */
  1012. if (hsdram->State == HAL_SDRAM_STATE_BUSY)
  1013. {
  1014. return HAL_BUSY;
  1015. }
  1016. else if (hsdram->State == HAL_SDRAM_STATE_READY)
  1017. {
  1018. /* Update the SDRAM state */
  1019. hsdram->State = HAL_SDRAM_STATE_BUSY;
  1020. /* Set the Auto-Refresh number */
  1021. (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
  1022. /* Update the SDRAM state */
  1023. hsdram->State = HAL_SDRAM_STATE_READY;
  1024. }
  1025. else
  1026. {
  1027. return HAL_ERROR;
  1028. }
  1029. return HAL_OK;
  1030. }
  1031. /**
  1032. * @brief Returns the SDRAM memory current mode.
  1033. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  1034. * the configuration information for SDRAM module.
  1035. * @retval The SDRAM memory mode.
  1036. */
  1037. uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
  1038. {
  1039. /* Return the SDRAM memory current mode */
  1040. return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
  1041. }
  1042. /**
  1043. * @}
  1044. */
  1045. /** @defgroup SDRAM_Exported_Functions_Group4 State functions
  1046. * @brief Peripheral State functions
  1047. *
  1048. @verbatim
  1049. ==============================================================================
  1050. ##### SDRAM State functions #####
  1051. ==============================================================================
  1052. [..]
  1053. This subsection permits to get in run-time the status of the SDRAM controller
  1054. and the data flow.
  1055. @endverbatim
  1056. * @{
  1057. */
  1058. /**
  1059. * @brief Returns the SDRAM state.
  1060. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
  1061. * the configuration information for SDRAM module.
  1062. * @retval HAL state
  1063. */
  1064. HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
  1065. {
  1066. return hsdram->State;
  1067. }
  1068. /**
  1069. * @}
  1070. */
  1071. /**
  1072. * @}
  1073. */
  1074. /**
  1075. * @brief DMA SDRAM process complete callback.
  1076. * @param hdma : DMA handle
  1077. * @retval None
  1078. */
  1079. static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
  1080. {
  1081. SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
  1082. /* Disable the DMA channel */
  1083. __HAL_DMA_DISABLE(hdma);
  1084. /* Update the SDRAM controller state */
  1085. hsdram->State = HAL_SDRAM_STATE_READY;
  1086. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  1087. hsdram->DmaXferCpltCallback(hdma);
  1088. #else
  1089. HAL_SDRAM_DMA_XferCpltCallback(hdma);
  1090. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  1091. }
  1092. /**
  1093. * @brief DMA SRAM process complete callback.
  1094. * @param hdma : DMA handle
  1095. * @retval None
  1096. */
  1097. static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
  1098. {
  1099. SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
  1100. /* Disable the DMA channel */
  1101. __HAL_DMA_DISABLE(hdma);
  1102. /* Update the SDRAM controller state */
  1103. hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
  1104. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  1105. hsdram->DmaXferCpltCallback(hdma);
  1106. #else
  1107. HAL_SDRAM_DMA_XferCpltCallback(hdma);
  1108. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  1109. }
  1110. /**
  1111. * @brief DMA SDRAM error callback.
  1112. * @param hdma : DMA handle
  1113. * @retval None
  1114. */
  1115. static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
  1116. {
  1117. SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
  1118. /* Disable the DMA channel */
  1119. __HAL_DMA_DISABLE(hdma);
  1120. /* Update the SDRAM controller state */
  1121. hsdram->State = HAL_SDRAM_STATE_ERROR;
  1122. #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
  1123. hsdram->DmaXferErrorCallback(hdma);
  1124. #else
  1125. HAL_SDRAM_DMA_XferErrorCallback(hdma);
  1126. #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
  1127. }
  1128. /**
  1129. * @}
  1130. */
  1131. #endif /* HAL_SDRAM_MODULE_ENABLED */
  1132. /**
  1133. * @}
  1134. */
  1135. #endif /* FMC_Bank5_6 */