[Add]进行hal库移植测试，ucos移植电灯测试

.mxproject

@@ -0,0 +1,25 @@
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Inc/stm32f4xx_it.h
+HeaderFiles#1=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Inc/stm32f4xx_hal_conf.h
+HeaderFiles#2=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Src/stm32f4xx_it.c
+SourceFiles#1=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Src/stm32f4xx_hal_msp.c
+SourceFiles#2=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=D:/xinjiedianqi/学习文档/TrainCamp_zengbingjie_Modbus/Modbus/Core/Src
+SourceFiles=;
+
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+
+[PreviousUsedIarFiles]
+SourceFiles=..\Core\Src\main.c;..\Core\Src\stm32f4xx_it.c;..\Core\Src\stm32f4xx_hal_msp.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Core\Src/system_stm32f4xx.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;..\Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;..\Core\Src/system_stm32f4xx.c;..\Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;;
+HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+

Core/Inc/main.h

@@ -0,0 +1,83 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <app_cfg.h>
+#include <os_cfg.h>
+#include <ucos_ii.h>
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* USER CODE BEGIN ET */
+extern UART_HandleTypeDef huart1;
+/* USER CODE END ET */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+#define LED_GPIO_PORT       GPIOF
+#define LED_GPIO_PIN        GPIO_PIN_6
+#define LED_ON()            HAL_GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PIN, GPIO_PIN_RESET)
+#define LED_OFF()           HAL_GPIO_WritePin(LED_GPIO_PORT, LED_GPIO_PIN, GPIO_PIN_SET)
+#define LED_TOGGLE()        HAL_GPIO_TogglePin(LED_GPIO_PORT, LED_GPIO_PIN)
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Inc/stm32f4xx_hal_conf.h

@@ -0,0 +1,492 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_CAN_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    12000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE		      3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U   /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS           0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Inc/stm32f4xx_it.h

@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Modbus/modbus.c

@@ -0,0 +1,315 @@
+/*
+*********************************************************************************************************
+*                                   MODBUS RTU SLAVE PROTOCOL
+*
+* Filename : modbus.c
+*********************************************************************************************************
+*/
+
+#include "modbus.h"
+
+/* Modbus CRC16 高位表 */
+static const uint8_t  Modbus_CRCHiTable[] = {
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,
+    0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
+    0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,
+    0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,
+    0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,
+    0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40,
+    0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,
+    0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,
+    0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40,
+    0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
+    0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,
+    0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
+    0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,
+    0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1,
+    0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
+    0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0,
+    0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+};
+
+/* Modbus CRC16 低位表 */
+static const uint8_t  Modbus_CRCLoTable[] = {
+    0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06,
+    0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD,
+    0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09,
+    0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A,
+    0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 0x14, 0xD4,
+    0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
+    0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3,
+    0xF2, 0x32, 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4,
+    0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A,
+    0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29,
+    0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED,
+    0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
+    0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60,
+    0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67,
+    0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F,
+    0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68,
+    0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 0xBE, 0x7E,
+    0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
+    0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71,
+    0x70, 0xB0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92,
+    0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C,
+    0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B,
+    0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B,
+    0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
+    0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42,
+    0x43, 0x83, 0x41, 0x81, 0x80, 0x40
+};
+
+
+/*
+*********************************************************************************************************
+*                                       CRC16 计算
+*********************************************************************************************************
+*/
+uint16_t  Modbus_CRC16 (uint8_t *buf, uint16_t len)
+{
+    uint8_t   crc_hi = 0xFFu;
+    uint8_t   crc_lo = 0xFFu;
+    uint16_t  i;
+    uint8_t   idx;
+
+    for (i = 0u; i < len; i++) {
+        idx      = crc_hi ^ buf[i];
+        crc_hi   = crc_lo ^ Modbus_CRCHiTable[idx];
+        crc_lo   = Modbus_CRCLoTable[idx];
+    }
+
+    return ((uint16_t)crc_hi << 8u) | (uint16_t)crc_lo;
+}
+
+
+/*
+*********************************************************************************************************
+*                                      从站初始化
+*********************************************************************************************************
+*/
+void  Modbus_SlaveInit (Modbus_Slave_t *slave, uint8_t addr)
+{
+    uint16_t  i;
+
+    slave->slave_addr = addr;
+
+    /* 清空保持寄存器 */
+    for (i = 0u; i < MODBUS_REG_COUNT; i++) {
+        slave->holding_regs[i] = 0u;
+    }
+
+    /* 设置默认测试值 */
+    slave->holding_regs[0] = 0x1234u;   /* 寄存器 0: 0x1234 */
+    slave->holding_regs[1] = 0x5678u;   /* 寄存器 1: 0x5678 */
+}
+
+
+/*
+*********************************************************************************************************
+*                                   Modbus 帧处理 (从站)
+*
+* 返回:  0 = 成功
+*       -1 = 帧错误(不回复)
+*        1 = 异常响应
+*********************************************************************************************************
+*/
+int8_t  Modbus_ProcessFrame (Modbus_Slave_t *slave,
+                             uint8_t *rx_buf,  uint16_t  rx_len,
+                             uint8_t *tx_buf,  uint16_t *tx_len)
+{
+    uint8_t    slave_addr;
+    uint8_t    func_code;
+    uint16_t   crc_rx;
+    uint16_t   crc_calc;
+    uint16_t   reg_addr;
+    uint16_t   reg_count;
+    uint16_t   byte_cnt;
+    uint16_t   i;
+    uint16_t   val;
+
+    *tx_len = 0u;
+
+    /* 帧至少需要 4 字节: 地址 + 功能码 + CRC(2) */
+    if (rx_len < 4u) {
+        return -1;
+    }
+
+    /* CRC 校验 */
+    crc_calc = Modbus_CRC16(rx_buf, rx_len - 2u);
+    crc_rx   = ((uint16_t)rx_buf[rx_len - 2u] << 8u) |
+                (uint16_t)rx_buf[rx_len - 1u];
+    if (crc_calc != crc_rx) {
+        return -1;
+    }
+
+    slave_addr = rx_buf[0];
+    func_code  = rx_buf[1];
+
+    /* 地址不匹配，不响应 */
+    if (slave_addr != slave->slave_addr && slave_addr != 0u) {
+        return -1;
+    }
+
+    switch (func_code) {
+
+    /*
+    *****************************************************************************
+    *  功能码 0x03: 读保持寄存器
+    *  请求:  ADDR FC START_H START_L COUNT_H COUNT_L CRC_L CRC_H
+    *  响应:  ADDR FC BYTE_CNT DATA_H DATA_L ... CRC_L CRC_H
+    *****************************************************************************
+    */
+    case MODBUS_FC_READ_HOLDING_REGS:
+        if (rx_len != 8u) {
+            goto exception_illegal_data_val;
+        }
+
+        reg_addr  = ((uint16_t)rx_buf[2] << 8u) | (uint16_t)rx_buf[3];
+        reg_count = ((uint16_t)rx_buf[4] << 8u) | (uint16_t)rx_buf[5];
+
+        if (reg_count == 0u || reg_count > 125u) {
+            goto exception_illegal_data_val;
+        }
+        if ((reg_addr + reg_count) > MODBUS_REG_COUNT) {
+            goto exception_illegal_data_addr;
+        }
+
+        /* 构建响应 */
+        byte_cnt = reg_count * 2u;
+        tx_buf[0] = slave->slave_addr;
+        tx_buf[1] = func_code;
+        tx_buf[2] = (uint8_t)byte_cnt;
+
+        for (i = 0u; i < reg_count; i++) {
+            val = slave->holding_regs[reg_addr + i];
+            tx_buf[3u + i * 2u]     = (uint8_t)(val >> 8u);
+            tx_buf[3u + i * 2u + 1u] = (uint8_t)(val & 0xFFu);
+        }
+
+        *tx_len = 3u + byte_cnt;
+        break;
+
+    /*
+    *****************************************************************************
+    *  功能码 0x06: 写单个寄存器
+    *  请求:  ADDR FC REG_H REG_L DATA_H DATA_L CRC_L CRC_H
+    *  响应:  回显请求
+    *****************************************************************************
+    */
+    case MODBUS_FC_WRITE_SINGLE_REG:
+        if (rx_len != 8u) {
+            goto exception_illegal_data_val;
+        }
+
+        reg_addr = ((uint16_t)rx_buf[2] << 8u) | (uint16_t)rx_buf[3];
+        val      = ((uint16_t)rx_buf[4] << 8u) | (uint16_t)rx_buf[5];
+
+        if (reg_addr >= MODBUS_REG_COUNT) {
+            goto exception_illegal_data_addr;
+        }
+
+        slave->holding_regs[reg_addr] = val;
+
+        /* 回显请求帧 */
+        for (i = 0u; i < rx_len; i++) {
+            tx_buf[i] = rx_buf[i];
+        }
+        *tx_len = rx_len;
+        break;
+
+    /*
+    *****************************************************************************
+    *  功能码 0x10: 写多个寄存器
+    *  请求:  ADDR FC START_H START_L COUNT_H COUNT_L BYTE_CNT DATA... CRC
+    *  响应:  ADDR FC START_H START_L COUNT_H COUNT_L CRC
+    *****************************************************************************
+    */
+    case MODBUS_FC_WRITE_MULTIPLE_REGS:
+        if (rx_len < 9u) {
+            goto exception_illegal_data_val;
+        }
+
+        reg_addr  = ((uint16_t)rx_buf[2] << 8u) | (uint16_t)rx_buf[3];
+        reg_count = ((uint16_t)rx_buf[4] << 8u) | (uint16_t)rx_buf[5];
+        byte_cnt  =  (uint16_t)rx_buf[6];
+
+        if (reg_count == 0u || reg_count > 123u) {
+            goto exception_illegal_data_val;
+        }
+        if (byte_cnt != (reg_count * 2u)) {
+            goto exception_illegal_data_val;
+        }
+        if ((reg_addr + reg_count) > MODBUS_REG_COUNT) {
+            goto exception_illegal_data_addr;
+        }
+
+        for (i = 0u; i < reg_count; i++) {
+            val = ((uint16_t)rx_buf[7u + i * 2u] << 8u) |
+                   (uint16_t)rx_buf[7u + i * 2u + 1u];
+            slave->holding_regs[reg_addr + i] = val;
+        }
+
+        /* 构建响应: ADDR FC START_H START_L COUNT_H COUNT_L */
+        tx_buf[0] = slave->slave_addr;
+        tx_buf[1] = func_code;
+        tx_buf[2] = rx_buf[2];
+        tx_buf[3] = rx_buf[3];
+        tx_buf[4] = rx_buf[4];
+        tx_buf[5] = rx_buf[5];
+        *tx_len = 6u;
+        break;
+
+    default:
+        /* 不支持的功能码 */
+        goto exception_illegal_func;
+    }
+
+    /* 追加 CRC */
+    {
+        uint16_t  crc;
+        crc = Modbus_CRC16(tx_buf, *tx_len);
+        tx_buf[*tx_len]     = (uint8_t)(crc >> 8u);
+        tx_buf[*tx_len + 1u] = (uint8_t)(crc & 0xFFu);
+        *tx_len += 2u;
+    }
+
+    return 0;
+
+
+    /* ------ 异常响应 ------ */
+exception_illegal_func:
+    tx_buf[0] = slave->slave_addr;
+    tx_buf[1] = func_code | 0x80u;
+    tx_buf[2] = MODBUS_EXCEPTION_ILLEGAL_FUNC;
+    goto exception_crc;
+
+exception_illegal_data_addr:
+    tx_buf[0] = slave->slave_addr;
+    tx_buf[1] = func_code | 0x80u;
+    tx_buf[2] = MODBUS_EXCEPTION_ILLEGAL_DATA_ADDR;
+    goto exception_crc;
+
+exception_illegal_data_val:
+    tx_buf[0] = slave->slave_addr;
+    tx_buf[1] = func_code | 0x80u;
+    tx_buf[2] = MODBUS_EXCEPTION_ILLEGAL_DATA_VALUE;
+
+exception_crc:
+    {
+        uint16_t  crc;
+        crc = Modbus_CRC16(tx_buf, 3u);
+        tx_buf[3] = (uint8_t)(crc >> 8u);
+        tx_buf[4] = (uint8_t)(crc & 0xFFu);
+        *tx_len = 5u;
+    }
+    return 1;
+}

Core/Modbus/modbus.h

@@ -0,0 +1,56 @@
+/*
+*********************************************************************************************************
+*                                   MODBUS RTU SLAVE PROTOCOL
+*
+* Filename : modbus.h
+*********************************************************************************************************
+*/
+
+#ifndef __MODBUS_H
+#define __MODBUS_H
+
+#include "main.h"
+
+/* Modbus RTU 帧长度限制 */
+#define MODBUS_RX_BUF_SIZE      256u
+#define MODBUS_TX_BUF_SIZE      256u
+#define MODBUS_REG_COUNT        10u          /* 保持寄存器数量 */
+
+/* Modbus 功能码 */
+#define MODBUS_FC_READ_HOLDING_REGS      0x03u
+#define MODBUS_FC_WRITE_SINGLE_REG       0x06u
+#define MODBUS_FC_WRITE_MULTIPLE_REGS    0x10u
+
+/* Modbus 异常码 */
+#define MODBUS_EXCEPTION_ILLEGAL_FUNC        0x01u
+#define MODBUS_EXCEPTION_ILLEGAL_DATA_ADDR   0x02u
+#define MODBUS_EXCEPTION_ILLEGAL_DATA_VALUE  0x03u
+
+/* Modbus 默认从站地址 */
+#define MODBUS_SLAVE_ADDR_DEFAULT        0x01u
+
+/* 3.5字符超时 (tick数, @1ms) */
+#define MODBUS_T35_TIMEOUT              5u
+
+/*
+*********************************************************************************************************
+*                                       MODBUS 从站结构体
+*********************************************************************************************************
+*/
+typedef struct {
+    uint8_t   slave_addr;
+    uint16_t  holding_regs[MODBUS_REG_COUNT];   /* 保持寄存器 */
+} Modbus_Slave_t;
+
+/*
+*********************************************************************************************************
+*                                   MODBUS 从站公开函数
+*********************************************************************************************************
+*/
+void     Modbus_SlaveInit       (Modbus_Slave_t *slave, uint8_t addr);
+uint16_t Modbus_CRC16           (uint8_t *buf, uint16_t len);
+int8_t   Modbus_ProcessFrame    (Modbus_Slave_t *slave,
+                                 uint8_t *rx_buf, uint16_t rx_len,
+                                 uint8_t *tx_buf, uint16_t *tx_len);
+
+#endif /* __MODBUS_H */

Core/OS/Cfg/app_cfg.h

@@ -0,0 +1,81 @@
+/*
+*********************************************************************************************************
+*                                      APPLICATION CONFIGURATION
+*
+* Filename : app_cfg.h
+*********************************************************************************************************
+*/
+
+#ifndef  _APP_CFG_H_
+#define  _APP_CFG_H_
+
+
+/*
+*********************************************************************************************************
+*                               uC/OS-II CPU CONFIGURATION
+*********************************************************************************************************
+*/
+                                                                /* Kernel aware interrupt priority boundary            */
+#define  CPU_CFG_KA_IPL_BOUNDARY              4u
+                                                                /* STM32F4 uses 4-bits NVIC priority (bits 7:4)       */
+#define  CPU_CFG_NVIC_PRIO_BITS               4u
+
+
+/*
+*********************************************************************************************************
+*                                     INCLUDE FILES
+*********************************************************************************************************
+*/
+
+#include  <stdio.h>
+
+
+/*
+*********************************************************************************************************
+*                                  TRACE / DEBUG CONFIGURATION
+*********************************************************************************************************
+*/
+
+#ifndef  TRACE_LEVEL_OFF
+#define  TRACE_LEVEL_OFF                      0u
+#endif
+
+#ifndef  TRACE_LEVEL_INFO
+#define  TRACE_LEVEL_INFO                     1u
+#endif
+
+#ifndef  TRACE_LEVEL_DBG
+#define  TRACE_LEVEL_DBG                      2u
+#endif
+
+#define  APP_TRACE_LEVEL                     TRACE_LEVEL_OFF
+#define  APP_TRACE                           printf
+
+#define  APP_TRACE_INFO(x)    ((APP_TRACE_LEVEL >= TRACE_LEVEL_INFO)  ? (void)(APP_TRACE x) : (void)0)
+#define  APP_TRACE_DBG(x)     ((APP_TRACE_LEVEL >= TRACE_LEVEL_DBG)   ? (void)(APP_TRACE x) : (void)0)
+
+
+/*
+*********************************************************************************************************
+*                                        TASK PRIORITIES
+*********************************************************************************************************
+*/
+
+#define  APP_TASK_START_PRIO                   5u
+#define  APP_TASK_LED_PRIO                     6u
+#define  APP_TASK_MODBUS_PRIO                  4u
+
+#define  OS_TASK_TMR_PRIO                     (OS_LOWEST_PRIO - 2u)
+
+
+/*
+*********************************************************************************************************
+*                                       TASK STACK SIZES
+*********************************************************************************************************
+*/
+
+#define  APP_TASK_START_STK_SIZE             128u
+#define  APP_TASK_LED_STK_SIZE               128u
+
+
+#endif

Core/OS/Cfg/app_hooks.c

@@ -0,0 +1,253 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                              uC/OS-II
+*                                          Application Hooks
+*
+* Filename : app_hooks.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            INCLUDE FILES
+*********************************************************************************************************
+*/
+
+#include  <os.h>
+
+
+/*
+*********************************************************************************************************
+*                                      EXTERN  GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                          LOCAL DATA TYPES
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            LOCAL TABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                       LOCAL GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                      LOCAL FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+**                                         GLOBAL FUNCTIONS
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+**                                        uC/OS-II APP HOOKS
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#if (OS_APP_HOOKS_EN > 0)
+
+/*
+*********************************************************************************************************
+*                                  TASK CREATION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is created.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being created.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskCreateHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+
+
+/*
+*********************************************************************************************************
+*                                  TASK DELETION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is deleted.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being deleted.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskDelHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+
+
+/*
+*********************************************************************************************************
+*                                    IDLE TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskIdleHook(), which is called by the idle task.  This hook
+*               has been added to allow you to do such things as STOP the CPU to conserve power.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are enabled during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 251
+void  App_TaskIdleHook (void)
+{
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                  STATISTIC TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskStatHook(), which is called every second by uC/OS-II's
+*               statistics task.  This allows your application to add functionality to the statistics task.
+*
+* Argument(s) : none.
+*********************************************************************************************************
+*/
+
+void  App_TaskStatHook (void)
+{
+}
+
+
+/*
+*********************************************************************************************************
+*                                   TASK RETURN HOOK (APPLICATION)
+*
+* Description: This function is called if a task accidentally returns.  In other words, a task should
+*              either be an infinite loop or delete itself when done.
+*
+* Arguments  : ptcb      is a pointer to the task control block of the task that is returning.
+*
+* Note(s)    : none
+*********************************************************************************************************
+*/
+
+
+#if OS_VERSION >= 289
+void  App_TaskReturnHook (OS_TCB  *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                   TASK SWITCH HOOK (APPLICATION)
+*
+* Description : This function is called when a task switch is performed.  This allows you to perform other
+*               operations during a context switch.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*
+*               (2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
+*                   will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                  task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SW_HOOK_EN > 0
+void  App_TaskSwHook (void)
+{
+
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                   OS_TCBInit() HOOK (APPLICATION)
+*
+* Description : This function is called by OSTCBInitHook(), which is called by OS_TCBInit() after setting
+*               up most of the TCB.
+*
+* Argument(s) : ptcb    is a pointer to the TCB of the task being created.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 204
+void  App_TCBInitHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       TICK HOOK (APPLICATION)
+*
+* Description : This function is called every tick.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_TICK_HOOK_EN > 0
+void  App_TimeTickHook (void)
+{
+
+}
+#endif
+#endif

Core/OS/Cfg/os_cfg.h

@@ -0,0 +1,154 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                 uC/OS-II Configuration File for V2.9x
+*
+* Filename : os_cfg.h
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef OS_CFG_H
+#define OS_CFG_H
+
+
+                                       /* ---------------------- MISCELLANEOUS ----------------------- */
+#define OS_APP_HOOKS_EN           1u   /* Application-defined hooks are called from the uC/OS-II hooks */
+#define OS_ARG_CHK_EN             1u   /* Enable (1) or Disable (0) argument checking                  */
+#define OS_CPU_HOOKS_EN           1u   /* uC/OS-II hooks are found in the processor port files         */
+
+#define OS_DEBUG_EN               1u   /* Enable(1) debug variables                                    */
+
+#define OS_EVENT_MULTI_EN         1u   /* Include code for OSEventPendMulti()                          */
+#define OS_EVENT_NAME_EN          1u   /* Enable names for Sem, Mutex, Mbox and Q                      */
+
+#define OS_LOWEST_PRIO           63u   /* Defines the lowest priority that can be assigned ...         */
+                                       /* ... MUST NEVER be higher than 254!                           */
+
+#define OS_MAX_EVENTS            10u   /* Max. number of event control blocks in your application      */
+#define OS_MAX_FLAGS              5u   /* Max. number of Event Flag Groups    in your application      */
+#define OS_MAX_MEM_PART           5u   /* Max. number of memory partitions                             */
+#define OS_MAX_QS                 4u   /* Max. number of queue control blocks in your application      */
+#define OS_MAX_TASKS             20u   /* Max. number of tasks in your application, MUST be >= 2       */
+
+#define OS_SCHED_LOCK_EN          1u   /* Include code for OSSchedLock() and OSSchedUnlock()           */
+
+#define OS_TICK_STEP_EN           1u   /* Enable tick stepping feature for uC/OS-View                  */
+#define OS_TICKS_PER_SEC       1000u   /* Set the number of ticks in one second (matching HAL 1ms)      */
+
+#define OS_TLS_TBL_SIZE           0u   /* Size of Thread-Local Storage Table                           */
+
+
+                                       /* --------------------- TASK STACK SIZE ---------------------- */
+#define OS_TASK_TMR_STK_SIZE    128u   /* Timer      task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_STAT_STK_SIZE   128u   /* Statistics task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_IDLE_STK_SIZE   128u   /* Idle       task stack size (# of OS_STK wide entries)        */
+
+
+                                       /* --------------------- TASK MANAGEMENT ---------------------- */
+#define OS_TASK_CHANGE_PRIO_EN    1u   /*     Include code for OSTaskChangePrio()                      */
+#define OS_TASK_CREATE_EN         1u   /*     Include code for OSTaskCreate()                          */
+#define OS_TASK_CREATE_EXT_EN     1u   /*     Include code for OSTaskCreateExt()                       */
+#define OS_TASK_DEL_EN            1u   /*     Include code for OSTaskDel()                             */
+#define OS_TASK_NAME_EN           1u   /*     Enable task names                                        */
+#define OS_TASK_PROFILE_EN        1u   /*     Include variables in OS_TCB for profiling                */
+#define OS_TASK_QUERY_EN          1u   /*     Include code for OSTaskQuery()                           */
+#define OS_TASK_REG_TBL_SIZE      1u   /*     Size of task variables array (#of INT32U entries)        */
+#define OS_TASK_STAT_EN           1u   /*     Enable (1) or Disable(0) the statistics task             */
+#define OS_TASK_STAT_STK_CHK_EN   1u   /*     Check task stacks from statistic task                    */
+#define OS_TASK_SUSPEND_EN        1u   /*     Include code for OSTaskSuspend() and OSTaskResume()      */
+#define OS_TASK_SW_HOOK_EN        1u   /*     Include code for OSTaskSwHook()                          */
+
+
+                                       /* ----------------------- EVENT FLAGS ------------------------ */
+#define OS_FLAG_EN                1u   /* Enable (1) or Disable (0) code generation for EVENT FLAGS    */
+#define OS_FLAG_ACCEPT_EN         1u   /*     Include code for OSFlagAccept()                          */
+#define OS_FLAG_DEL_EN            1u   /*     Include code for OSFlagDel()                             */
+#define OS_FLAG_NAME_EN           1u   /*     Enable names for event flag group                        */
+#define OS_FLAG_QUERY_EN          1u   /*     Include code for OSFlagQuery()                           */
+#define OS_FLAG_WAIT_CLR_EN       1u   /* Include code for Wait on Clear EVENT FLAGS                   */
+#define OS_FLAGS_NBITS           16u   /* Size in #bits of OS_FLAGS data type (8, 16 or 32)            */
+
+
+                                       /* -------------------- MESSAGE MAILBOXES --------------------- */
+#define OS_MBOX_EN                1u   /* Enable (1) or Disable (0) code generation for MAILBOXES      */
+#define OS_MBOX_ACCEPT_EN         1u   /*     Include code for OSMboxAccept()                          */
+#define OS_MBOX_DEL_EN            1u   /*     Include code for OSMboxDel()                             */
+#define OS_MBOX_PEND_ABORT_EN     1u   /*     Include code for OSMboxPendAbort()                       */
+#define OS_MBOX_POST_EN           1u   /*     Include code for OSMboxPost()                            */
+#define OS_MBOX_POST_OPT_EN       1u   /*     Include code for OSMboxPostOpt()                         */
+#define OS_MBOX_QUERY_EN          1u   /*     Include code for OSMboxQuery()                           */
+
+
+                                       /* --------------------- MEMORY MANAGEMENT -------------------- */
+#define OS_MEM_EN                 1u   /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
+#define OS_MEM_NAME_EN            1u   /*     Enable memory partition names                            */
+#define OS_MEM_QUERY_EN           1u   /*     Include code for OSMemQuery()                            */
+
+
+                                       /* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
+#define OS_MUTEX_EN               1u   /* Enable (1) or Disable (0) code generation for MUTEX          */
+#define OS_MUTEX_ACCEPT_EN        1u   /*     Include code for OSMutexAccept()                         */
+#define OS_MUTEX_DEL_EN           1u   /*     Include code for OSMutexDel()                            */
+#define OS_MUTEX_QUERY_EN         1u   /*     Include code for OSMutexQuery()                          */
+
+
+                                       /* ---------------------- MESSAGE QUEUES ---------------------- */
+#define OS_Q_EN                   1u   /* Enable (1) or Disable (0) code generation for QUEUES         */
+#define OS_Q_ACCEPT_EN            1u   /*     Include code for OSQAccept()                             */
+#define OS_Q_DEL_EN               1u   /*     Include code for OSQDel()                                */
+#define OS_Q_FLUSH_EN             1u   /*     Include code for OSQFlush()                              */
+#define OS_Q_PEND_ABORT_EN        1u   /*     Include code for OSQPendAbort()                          */
+#define OS_Q_POST_EN              1u   /*     Include code for OSQPost()                               */
+#define OS_Q_POST_FRONT_EN        1u   /*     Include code for OSQPostFront()                          */
+#define OS_Q_POST_OPT_EN          1u   /*     Include code for OSQPostOpt()                            */
+#define OS_Q_QUERY_EN             1u   /*     Include code for OSQQuery()                              */
+
+
+                                       /* ------------------------ SEMAPHORES ------------------------ */
+#define OS_SEM_EN                 1u   /* Enable (1) or Disable (0) code generation for SEMAPHORES     */
+#define OS_SEM_ACCEPT_EN          1u   /*    Include code for OSSemAccept()                            */
+#define OS_SEM_DEL_EN             1u   /*    Include code for OSSemDel()                               */
+#define OS_SEM_PEND_ABORT_EN      1u   /*    Include code for OSSemPendAbort()                         */
+#define OS_SEM_QUERY_EN           1u   /*    Include code for OSSemQuery()                             */
+#define OS_SEM_SET_EN             1u   /*    Include code for OSSemSet()                               */
+
+
+                                       /* --------------------- TIME MANAGEMENT ---------------------- */
+#define OS_TIME_DLY_HMSM_EN       1u   /*     Include code for OSTimeDlyHMSM()                         */
+#define OS_TIME_DLY_RESUME_EN     1u   /*     Include code for OSTimeDlyResume()                       */
+#define OS_TIME_GET_SET_EN        1u   /*     Include code for OSTimeGet() and OSTimeSet()             */
+#define OS_TIME_TICK_HOOK_EN      1u   /*     Include code for OSTimeTickHook()                        */
+
+
+                                       /* --------------------- TIMER MANAGEMENT --------------------- */
+#define OS_TMR_EN                 1u   /* Enable (1) or Disable (0) code generation for TIMERS         */
+#define OS_TMR_CFG_MAX           16u   /*     Maximum number of timers                                 */
+#define OS_TMR_CFG_NAME_EN        1u   /*     Determine timer names                                    */
+#define OS_TMR_CFG_WHEEL_SIZE     7u   /*     Size of timer wheel (#Spokes)                            */
+#define OS_TMR_CFG_TICKS_PER_SEC 10u   /*     Rate at which timer management task runs (Hz)            */
+
+
+                                       /* ---------------------- TRACE RECORDER ---------------------- */
+#define OS_TRACE_EN               0u   /* Enable (1) or Disable (0) uC/OS-II Trace instrumentation     */
+#define OS_TRACE_API_ENTER_EN     0u   /* Enable (1) or Disable (0) uC/OS-II Trace API enter instrum.  */
+#define OS_TRACE_API_EXIT_EN      0u   /* Enable (1) or Disable (0) uC/OS-II Trace API exit  instrum.  */
+
+#endif

Core/OS/Ports/os_cpu.h

@@ -0,0 +1,236 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                             ARMv7-M Port
+*
+* Filename  : os_cpu.h
+* Version   : V2.93.00
+*********************************************************************************************************
+* For       : ARMv7-M Cortex-M
+* Mode      : Thumb-2 ISA
+* Toolchain : IAR EWARM
+*********************************************************************************************************
+* Note(s)   : (1) This port supports the ARM Cortex-M3, Cortex-M4 and Cortex-M7 architectures.
+*             (2) It has been tested with the following Hardware Floating Point Unit.
+*                 (a) Single-precision: FPv4-SP-D16-M and FPv5-SP-D16-M
+*                 (b) Double-precision: FPv5-D16-M
+*********************************************************************************************************
+*/
+
+#ifndef  OS_CPU_H
+#define  OS_CPU_H
+
+#ifdef   OS_CPU_GLOBALS
+#define  OS_CPU_EXT
+#else
+#define  OS_CPU_EXT  extern
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                     EXTERNAL C LANGUAGE LINKAGE
+*
+* Note(s) : (1) C++ compilers MUST 'extern'ally declare ALL C function prototypes & variable/object
+*               declarations for correct C language linkage.
+*********************************************************************************************************
+*/
+
+#ifdef __cplusplus
+extern  "C" {                                    /* See Note #1.                                       */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                               DEFINES
+*
+* Note(s) : (1) If using uC/CPU then 'cpu_cfg.h' has already this define in its template. The user will
+*               only need to include 'cpu_cfg.h' in 'app_cfg.h'; otherwise, define CPU_CFG_KA_IPL_BOUNDARY
+*               and CPU_CFG_NVIC_PRIO_BITS in 'app_cfg.h'
+*
+*           (2) Since the port is using BASEPRI to separate kernel vs non-kernel aware ISR, please make sure
+*               your external interrupt priorities are set accordingly. For example, if CPU_CFG_KA_IPL_BOUNDARY
+*               is set to 4 then external interrupt priorities 4-15 will be kernel aware while priorities
+*               0-3 will be use as non-kernel aware.
+*
+*           (3) Determines the interrupt programmable priority levels. This is normally specified in the
+*               Microcontroller reference manual. 4-bits gives us 16 programmable priority levels.
+*
+*                     NVIC_IPRx
+*                 7                0
+*                +------------------+
+*                |       PRIO       |
+*                +------------------+
+*
+*                Bits[7:4] Priority mask bits
+*                Bits[3:0] Reserved
+*
+*                In this example our CPU_CFG_NVIC_PRIO_BITS define should be set to 4 due to the processor
+*                implementing only bits[7:4].
+*********************************************************************************************************
+*/
+
+#ifndef  OS_CPU_EXCEPT_STK_SIZE
+#define  OS_CPU_EXCEPT_STK_SIZE      256u        /* Default exception stack size is 256 OS_STK entries */
+#endif
+
+#ifdef __ARMVFP__
+#define  OS_CPU_ARM_FP_EN              1u
+#else
+#define  OS_CPU_ARM_FP_EN              0u
+#endif
+
+#ifndef CPU_CFG_KA_IPL_BOUNDARY
+#error  "CPU_CFG_KA_IPL_BOUNDARY        not #define'd in 'app_cfg.h'    "   /* See Note # 1 & 2        */
+#else
+#if (CPU_CFG_KA_IPL_BOUNDARY == 0u)
+#error  "CPU_CFG_KA_IPL_BOUNDARY        should be > 0 "
+#endif
+#endif
+
+#ifndef CPU_CFG_NVIC_PRIO_BITS
+#error  "CPU_CFG_NVIC_PRIO_BITS         not #define'd in 'app_cfg.h'    "   /* See Note # 3            */
+#else
+#if (CPU_CFG_KA_IPL_BOUNDARY >= (1u << CPU_CFG_NVIC_PRIO_BITS))
+#error  "CPU_CFG_KA_IPL_BOUNDARY        should not be set to higher than max programable priority level "
+#endif
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                              DATA TYPES
+*                                         (Compiler Specific)
+*********************************************************************************************************
+*/
+
+typedef unsigned char  BOOLEAN;
+typedef unsigned char  INT8U;                    /* Unsigned  8 bit quantity                           */
+typedef signed   char  INT8S;                    /* Signed    8 bit quantity                           */
+typedef unsigned short INT16U;                   /* Unsigned 16 bit quantity                           */
+typedef signed   short INT16S;                   /* Signed   16 bit quantity                           */
+typedef unsigned int   INT32U;                   /* Unsigned 32 bit quantity                           */
+typedef signed   int   INT32S;                   /* Signed   32 bit quantity                           */
+typedef float          FP32;                     /* Single precision floating point                    */
+typedef double         FP64;                     /* Double precision floating point                    */
+
+typedef unsigned int   OS_STK;                   /* Each stack entry is 32-bit wide                    */
+typedef unsigned int   OS_CPU_SR;                /* Define size of CPU status register (PSR = 32 bits) */
+
+
+/*
+*********************************************************************************************************
+*                                              Cortex-M
+*                                      Critical Section Management
+*
+* Method #1:  Disable/Enable interrupts using simple instructions.  After critical section, interrupts
+*             will be enabled even if they were disabled before entering the critical section.
+*             NOT IMPLEMENTED
+*
+* Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In other words, if
+*             interrupts were disabled before entering the critical section, they will be disabled when
+*             leaving the critical section.
+*             NOT IMPLEMENTED
+*
+* Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
+*             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
+*             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to
+*             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
+*             into the CPU's status register.
+*********************************************************************************************************
+*/
+
+#define  OS_CRITICAL_METHOD   3u
+
+#if OS_CRITICAL_METHOD == 3u
+                                                 /* Save current BASEPRI priority lvl for exception... */
+                                                 /* .. and set BASEPRI to CPU_CFG_KA_IPL_BOUNDARY      */
+#define  OS_ENTER_CRITICAL()  do { cpu_sr = OS_CPU_SR_Save(CPU_CFG_KA_IPL_BOUNDARY << (8u - CPU_CFG_NVIC_PRIO_BITS));} while (0)
+                                                 /* Restore CPU BASEPRI priority level.                */
+#define  OS_EXIT_CRITICAL()   do { OS_CPU_SR_Restore(cpu_sr);} while (0)
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                        Cortex-M Miscellaneous
+*********************************************************************************************************
+*/
+
+#define  OS_STK_GROWTH        1u                 /* Stack grows from HIGH to LOW memory on ARM         */
+
+#define  OS_TASK_SW()         OSCtxSw()
+
+
+/*
+*********************************************************************************************************
+*                                          GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+OS_CPU_EXT  OS_STK   OS_CPU_ExceptStk[OS_CPU_EXCEPT_STK_SIZE];
+OS_CPU_EXT  OS_STK  *OS_CPU_ExceptStkBase;
+
+
+/*
+*********************************************************************************************************
+*                                         FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+#if OS_CRITICAL_METHOD == 3u                     /* See OS_CPU_A.ASM                                   */
+OS_CPU_SR  OS_CPU_SR_Save         (OS_CPU_SR  new_basepri);
+void       OS_CPU_SR_Restore      (OS_CPU_SR  cpu_sr);
+#endif
+
+void       OSCtxSw                (void);
+void       OSIntCtxSw             (void);
+void       OSStartHighRdy         (void);
+
+                                                 /* See OS_CPU_C.C                                     */
+void       OS_CPU_SysTickInit     (INT32U     cnts);
+void       OS_CPU_SysTickInitFreq (INT32U     cpu_freq);
+
+void       OS_CPU_SysTickHandler  (void);
+void       OS_CPU_PendSVHandler   (void);
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+void       OS_CPU_FP_Reg_Push     (OS_STK    *stkPtr);
+void       OS_CPU_FP_Reg_Pop      (OS_STK    *stkPtr);
+#endif
+
+/*
+*********************************************************************************************************
+*                                   EXTERNAL C LANGUAGE LINKAGE END
+*********************************************************************************************************
+*/
+
+#ifdef __cplusplus
+}                                                /* End of 'extern'al C lang linkage.                  */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif

Core/OS/Ports/os_cpu_a.asm

@@ -0,0 +1,361 @@
+;********************************************************************************************************
+;                                              uC/OS-II
+;                                        The Real-Time Kernel
+;
+;                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+;
+;                                 SPDX-License-Identifier: APACHE-2.0
+;
+;               This software is subject to an open source license and is distributed by
+;                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+;                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+;
+;********************************************************************************************************
+
+;********************************************************************************************************
+;
+;                                             ARMv7-M Port
+;
+; Filename  : os_cpu_a.asm
+; Version   : V2.93.00
+;********************************************************************************************************
+; For       : ARMv7-M Cortex-M
+; Mode      : Thumb-2 ISA
+; Toolchain : IAR EWARM
+;********************************************************************************************************
+; Note(s)   : (1) This port supports the ARM Cortex-M3, Cortex-M4 and Cortex-M7 architectures.
+;             (2) It has been tested with the following Hardware Floating Point Unit.
+;                 (a) Single-precision: FPv4-SP-D16-M and FPv5-SP-D16-M
+;                 (b) Double-precision: FPv5-D16-M
+;********************************************************************************************************
+
+;********************************************************************************************************
+;                                          PUBLIC FUNCTIONS
+;********************************************************************************************************
+
+    EXTERN  OSRunning                                           ; External references
+    EXTERN  OSPrioCur
+    EXTERN  OSPrioHighRdy
+    EXTERN  OSTCBCur
+    EXTERN  OSTCBHighRdy
+    EXTERN  OSIntExit
+    EXTERN  OSTaskSwHook
+    EXTERN  OS_CPU_ExceptStkBase
+    EXTERN  OS_KA_BASEPRI_Boundary
+
+
+    PUBLIC  OSStartHighRdy                                      ; Functions declared in this file
+    PUBLIC  OS_CPU_SR_Save
+    PUBLIC  OS_CPU_SR_Restore
+    PUBLIC  OSCtxSw
+    PUBLIC  OSIntCtxSw
+    PUBLIC  OS_CPU_PendSVHandler
+
+#ifdef __ARMVFP__
+    PUBLIC  OS_CPU_FP_Reg_Push
+    PUBLIC  OS_CPU_FP_Reg_Pop
+#endif
+
+
+;********************************************************************************************************
+;                                               EQUATES
+;********************************************************************************************************
+
+NVIC_INT_CTRL   EQU     0xE000ED04                              ; Interrupt control state register.
+NVIC_SYSPRI14   EQU     0xE000ED22                              ; System priority register (priority 14).
+NVIC_PENDSV_PRI EQU           0xFF                              ; PendSV priority value (lowest).
+NVIC_PENDSVSET  EQU     0x10000000                              ; Value to trigger PendSV exception.
+
+
+;********************************************************************************************************
+;                                     CODE GENERATION DIRECTIVES
+;********************************************************************************************************
+
+    RSEG CODE:CODE:NOROOT(2)
+    THUMB
+
+
+;********************************************************************************************************
+;                                   FLOATING POINT REGISTERS PUSH
+;                             void  OS_CPU_FP_Reg_Push (OS_STK  *stkPtr)
+;
+; Note(s) : 1) This function saves S16-S31 registers of the Floating Point Unit.
+;
+;           2) Pseudo-code is:
+;              a) Push remaining FPU regs S16-S31 on process stack;
+;              b) Update OSTCBCur->OSTCBStkPtr;
+;********************************************************************************************************
+
+#ifdef __ARMVFP__
+OS_CPU_FP_Reg_Push
+    MRS     R1, PSP                                             ; PSP is process stack pointer
+    CBZ     R1, OS_CPU_FP_nosave                                ; Skip FP register save the first time
+
+    VSTMDB  R0!, {S16-S31}
+    LDR     R1, =OSTCBCur
+    LDR     R2, [R1]
+    STR     R0, [R2]
+OS_CPU_FP_nosave
+    BX      LR
+#endif
+
+
+;********************************************************************************************************
+;                                   FLOATING POINT REGISTERS POP
+;                             void  OS_CPU_FP_Reg_Pop (OS_STK  *stkPtr)
+;
+; Note(s) : 1) This function restores S16-S31 of the Floating Point Unit.
+;
+;           2) Pseudo-code is:
+;              a) Restore regs S16-S31 of new process stack;
+;              b) Update OSTCBHighRdy->OSTCBStkPtr pointer of new proces stack;
+;********************************************************************************************************
+
+#ifdef __ARMVFP__
+OS_CPU_FP_Reg_Pop
+    VLDMIA  R0!, {S16-S31}
+    LDR     R1, =OSTCBHighRdy
+    LDR     R2, [R1]
+    STR     R0, [R2]
+    BX      LR
+#endif
+
+
+;********************************************************************************************************
+;                                   CRITICAL SECTION METHOD 3 FUNCTIONS
+;
+; Description : Disable/Enable Kernel aware interrupts by preserving the state of BASEPRI.  Generally speaking,
+;               the state of the BASEPRI interrupt exception processing is stored in the local variable
+;               'cpu_sr' & Kernel Aware interrupts are then disabled ('cpu_sr' is allocated in all functions
+;               that need to disable Kernel aware interrupts). The previous BASEPRI interrupt state is restored
+;               by copying 'cpu_sr' into the BASEPRI register.
+;
+; Prototypes  : OS_CPU_SR  OS_CPU_SR_Save   (OS_CPU_SR  new_basepri);
+;               void       OS_CPU_SR_Restore(OS_CPU_SR  cpu_sr);
+;
+;
+; Note(s)     : 1) These functions are used in general like this:
+;
+;                  void Task (void *p_arg)
+;                  {
+;                  #if OS_CRITICAL_METHOD == 3          /* Allocate storage for CPU status register  */
+;                      OS_CPU_SR  cpu_sr;
+;                  #endif
+;
+;                          :
+;                          :
+;                      OS_ENTER_CRITICAL();             /* cpu_sr = OS_CPU_SR_Save(new_basepri);     */
+;                          :
+;                          :
+;                      OS_EXIT_CRITICAL();              /* OS_CPU_RestoreSR(cpu_sr);                 */
+;                          :
+;                          :
+;                  }
+;
+;               2) Increasing priority using a write to BASEPRI does not take effect immediately.
+;                  (a) IMPLICATION  This erratum means that the instruction after an MSR to boost BASEPRI
+;                      might incorrectly be preempted by an insufficient high priority exception.
+;
+;                  (b) WORKAROUND  The MSR to boost BASEPRI can be replaced by the following code sequence:
+;
+;                      CPSID i
+;                      MSR to BASEPRI
+;                      DSB
+;                      ISB
+;                      CPSIE i
+;********************************************************************************************************
+
+OS_CPU_SR_Save
+    CPSID   I                                   ; Cortex-M7 errata notice. See Note #2
+    PUSH   {R1}
+    MRS     R1, BASEPRI
+    MSR     BASEPRI, R0
+    DSB
+    ISB
+    MOV     R0, R1
+    POP    {R1}
+    CPSIE   I
+    BX      LR
+
+OS_CPU_SR_Restore
+    CPSID   I                                   ; Cortex-M7 errata notice. See Note #2
+    MSR     BASEPRI, R0
+    DSB
+    ISB
+    CPSIE   I
+    BX      LR
+
+
+;********************************************************************************************************
+;                                         START MULTITASKING
+;                                      void OSStartHighRdy(void)
+;
+; Note(s) : 1) This function triggers a PendSV exception (essentially, causes a context switch) to cause
+;              the first task to start.
+;
+;           2) During task execution, PSP is used as the stack pointer.
+;              When an exception occurs, the core will switch to MSP until the exception return.
+;
+;           3) OSStartHighRdy() MUST:
+;              a) Setup PendSV exception priority to lowest;
+;              b) Set initial PSP to 0, to tell context switcher this is first run;
+;              c) Set the main stack to OS_CPU_ExceptStkBase
+;              d) Set OSRunning to TRUE;
+;              e) Get current high priority, OSPrioCur = OSPrioHighRdy;
+;              f) Get current ready thread TCB, OSTCBCur = OSTCBHighRdy;
+;              g) Get new process SP from TCB, SP = OSTCBHighRdy->OSTCBStkPtr;
+;              h) Restore R0-R11 and R14 from new process stack;
+;              i) Enable interrupts (tasks will run with interrupts enabled).
+;********************************************************************************************************
+
+OSStartHighRdy
+    CPSID   I                                                   ; Prevent interruption during context switch
+    LDR     R0, =NVIC_SYSPRI14                                  ; Set the PendSV exception priority
+    LDR     R1, =NVIC_PENDSV_PRI
+    STRB    R1, [R0]
+
+    MOVS    R0, #0                                              ; Set the PSP to 0 for initial context switch call
+    MSR     PSP, R0
+
+    LDR     R0, =OS_CPU_ExceptStkBase                           ; Initialize the MSP to the OS_CPU_ExceptStkBase
+    LDR     R1, [R0]
+    MSR     MSP, R1
+
+    BL      OSTaskSwHook                                        ; Call OSTaskSwHook() for FPU Push & Pop
+
+    LDR     R0, =OSRunning                                      ; OSRunning = TRUE
+    MOVS    R1, #1
+    STRB    R1, [R0]
+
+    LDR     R0, =OSPrioCur                                      ; OSPrioCur = OSPrioHighRdy;
+    LDR     R1, =OSPrioHighRdy
+    LDRB    R2, [R1]
+    STRB    R2, [R0]
+
+    LDR     R0, =OSTCBCur                                       ; OSTCBCur  = OSTCBHighRdy;
+    LDR     R1, =OSTCBHighRdy
+    LDR     R2, [R1]
+    STR     R2, [R0]
+
+    LDR     R0, [R2]                                            ; R0 is new process SP; SP = OSTCBHighRdy->OSTCBStkPtr;
+    MSR     PSP, R0                                             ; Load PSP with new process SP
+
+    MRS     R0, CONTROL
+    ORR     R0, R0, #2
+    MSR     CONTROL, R0
+    ISB                                                         ; Sync instruction stream
+
+    LDMFD    SP!, {R4-R11, LR}                                  ; Restore r4-11, lr from new process stack
+    LDMFD    SP!, {R0-R3}                                       ; Restore r0, r3
+    LDMFD    SP!, {R12, LR}                                     ; Load R12 and LR
+    LDMFD    SP!, {R1, R2}                                      ; Load PC and discard xPSR
+    CPSIE    I
+    BX       R1
+
+
+;********************************************************************************************************
+;                       PERFORM A CONTEXT SWITCH (From task level) - OSCtxSw()
+;                   PERFORM A CONTEXT SWITCH (From interrupt level) - OSIntCtxSw()
+;
+; Note(s) : 1) OSCtxSw() is called when OS wants to perform a task context switch.  This function
+;              triggers the PendSV exception which is where the real work is done.
+;
+;           2) OSIntCtxSw() is called by OSIntExit() when it determines a context switch is needed as
+;              the result of an interrupt.  This function simply triggers a PendSV exception which will
+;              be handled when there are no more interrupts active and interrupts are enabled.
+;********************************************************************************************************
+
+OSCtxSw
+OSIntCtxSw
+    LDR     R0, =NVIC_INT_CTRL                                  ; Trigger the PendSV exception (causes context switch)
+    LDR     R1, =NVIC_PENDSVSET
+    STR     R1, [R0]
+    BX      LR
+
+
+;********************************************************************************************************
+;                                       HANDLE PendSV EXCEPTION
+;                                   void OS_CPU_PendSVHandler(void)
+;
+; Note(s) : 1) PendSV is used to cause a context switch.  This is a recommended method for performing
+;              context switches with Cortex-M.  This is because the Cortex-M auto-saves half of the
+;              processor context on any exception, and restores same on return from exception.  So only
+;              saving of R4-R11 & R14 is required and fixing up the stack pointers. Using the PendSV exception
+;              this way means that context saving and restoring is identical whether it is initiated from
+;              a thread or occurs due to an interrupt or exception.
+;
+;           2) Pseudo-code is:
+;              a) Get the process SP
+;              b) Save remaining regs r4-r11 & r14 on process stack;
+;              c) Save the process SP in its TCB, OSTCBCur->OSTCBStkPtr = SP;
+;              d) Call OSTaskSwHook();
+;              e) Get current high priority, OSPrioCur = OSPrioHighRdy;
+;              f) Get current ready thread TCB, OSTCBCur = OSTCBHighRdy;
+;              g) Get new process SP from TCB, SP = OSTCBHighRdy->OSTCBStkPtr;
+;              h) Restore R4-R11 and R14 from new process stack;
+;              i) Perform exception return which will restore remaining context.
+;
+;           3) On entry into PendSV handler:
+;              a) The following have been saved on the process stack (by processor):
+;                 xPSR, PC, LR, R12, R0-R3
+;              b) Processor mode is switched to Handler mode (from Thread mode)
+;              c) Stack is Main stack (switched from Process stack)
+;              d) OSTCBCur      points to the OS_TCB of the task to suspend
+;                 OSTCBHighRdy  points to the OS_TCB of the task to resume
+;
+;           4) Since PendSV is set to lowest priority in the system (by OSStartHighRdy() above), we
+;              know that it will only be run when no other exception or interrupt is active, and
+;              therefore safe to assume that context being switched out was using the process stack (PSP).
+;
+;           5) Increasing priority using a write to BASEPRI does not take effect immediately.
+;              (a) IMPLICATION  This erratum means that the instruction after an MSR to boost BASEPRI
+;                  might incorrectly be preempted by an insufficient high priority exception.
+;
+;              (b) WORKAROUND  The MSR to boost BASEPRI can be replaced by the following code sequence:
+;
+;                  CPSID i
+;                  MSR to BASEPRI
+;                  DSB
+;                  ISB
+;                  CPSIE i
+;********************************************************************************************************
+
+OS_CPU_PendSVHandler
+    CPSID   I                                                   ; Cortex-M7 errata notice. See Note #5
+    MOV32   R2, OS_KA_BASEPRI_Boundary                          ; Set BASEPRI priority level required for exception preemption
+    LDR     R1, [R2]
+    MSR     BASEPRI, R1
+    DSB
+    ISB
+    CPSIE   I
+
+    MRS     R0, PSP                                             ; PSP is process stack pointer
+    STMFD   R0!, {R4-R11, R14}                                  ; Save remaining regs r4-11, R14 on process stack
+
+    LDR     R5, =OSTCBCur                                       ; OSTCBCur->OSTCBStkPtr = SP;
+    LDR     R1, [R5]
+    STR     R0, [R1]                                            ; R0 is SP of process being switched out
+
+                                                                ; At this point, entire context of process has been saved
+    MOV     R4, LR                                              ; Save LR exc_return value
+    BL      OSTaskSwHook                                        ; Call OSTaskSwHook() for FPU Push & Pop
+
+    LDR     R0, =OSPrioCur                                      ; OSPrioCur = OSPrioHighRdy;
+    LDR     R1, =OSPrioHighRdy
+    LDRB    R2, [R1]
+    STRB    R2, [R0]
+
+    LDR     R1, =OSTCBHighRdy                                   ; OSTCBCur  = OSTCBHighRdy;
+    LDR     R2, [R1]
+    STR     R2, [R5]
+
+    ORR     LR,  R4, #0x04                                      ; Ensure exception return uses process stack
+    LDR     R0,  [R2]                                           ; R0 is new process SP; SP = OSTCBHighRdy->OSTCBStkPtr;
+    LDMFD   R0!, {R4-R11, R14}                                  ; Restore r4-11, R14 from new process stack
+    MSR     PSP, R0                                             ; Load PSP with new process SP
+
+    MOV32   R2, #0                                              ; Restore BASEPRI priority level to 0
+    MSR     BASEPRI, R2
+    BX      LR                                                  ; Exception return will restore remaining context
+
+    END

Core/OS/Ports/os_cpu_c.c

@@ -0,0 +1,727 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                             ARMv7-M Port
+*
+* File    : os_cpu_c.c
+* Version : V2.93.00
+*********************************************************************************************************
+* For     : ARMv7-M Cortex-M
+* Mode    : Thumb-2 ISA
+*********************************************************************************************************
+* Note(s) : (1) This port supports the ARM Cortex-M3, Cortex-M4 and Cortex-M7 architectures.
+*           (2) It has been tested with the following Hardware Floating Point Unit.
+*               (a) Single-precision: FPv4-SP-D16-M and FPv5-SP-D16-M
+*               (b) Double-precision: FPv5-D16-M
+*********************************************************************************************************
+*/
+
+#define   OS_CPU_GLOBALS
+
+
+/*
+*********************************************************************************************************
+*                                             INCLUDE FILES
+*********************************************************************************************************
+*/
+
+#include  <ucos_ii.h>
+
+
+/*
+*********************************************************************************************************
+*                                          LOCAL VARIABLES
+*********************************************************************************************************
+*/
+
+#if OS_TMR_EN > 0u
+static  INT16U  OSTmrCtr;
+#endif
+
+/*
+*********************************************************************************************************
+*                                       LOCAL GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+INT32U  OS_KA_BASEPRI_Boundary;                                 /* Base Priority boundary.                              */
+
+
+/*
+*********************************************************************************************************
+*                                          SYS TICK DEFINES
+*********************************************************************************************************
+*/
+
+#define  OS_CPU_CM_SYST_CSR         (*((volatile INT32U *)0xE000E010uL)) /* SysTick Ctrl & Status Reg.                  */
+#define  OS_CPU_CM_SYST_RVR         (*((volatile INT32U *)0xE000E014uL)) /* SysTick Reload  Value Reg.                  */
+#define  OS_CPU_CM_SYST_CVR         (*((volatile INT32U *)0xE000E018uL)) /* SysTick Current Value Reg.                  */
+#define  OS_CPU_CM_SYST_CALIB       (*((volatile INT32U *)0xE000E01CuL)) /* SysTick Cal     Value Reg.                  */
+#define  OS_CPU_CM_SCB_SHPRI1       (*((volatile INT32U *)0xE000ED18uL)) /* System Handlers  4 to  7 Prio.              */
+#define  OS_CPU_CM_SCB_SHPRI2       (*((volatile INT32U *)0xE000ED1CuL)) /* System Handlers  8 to 11 Prio.              */
+#define  OS_CPU_CM_SCB_SHPRI3       (*((volatile INT32U *)0xE000ED20uL)) /* System Handlers 12 to 15 Prio.              */
+
+
+#define  OS_CPU_CM_SYST_CSR_COUNTFLAG                     0x00010000uL   /* Count flag.                                 */
+#define  OS_CPU_CM_SYST_CSR_CLKSOURCE                     0x00000004uL   /* Clock Source.                               */
+#define  OS_CPU_CM_SYST_CSR_TICKINT                       0x00000002uL   /* Interrupt enable.                           */
+#define  OS_CPU_CM_SYST_CSR_ENABLE                        0x00000001uL   /* Counter mode.                               */
+
+
+/*
+*********************************************************************************************************
+*                                         FLOATING POINT DEFINES
+*
+* Note(s) : 1) Enabled FP lazy stacking and enable automatic state saving.
+*********************************************************************************************************
+*/
+
+#define  OS_CPU_CM_FP_FPCCR         (*((volatile INT32U *)0xE000EF34uL)) /* Floating-Point Context Control Reg.         */
+#define  OS_CPU_CM_FPCCR_LAZY_STK                         0xC0000000uL   /* See Note 1.                                 */
+
+
+/*
+*********************************************************************************************************
+*                                       OS INITIALIZATION HOOK
+*                                            (BEGINNING)
+*
+* Description: This function is called by OSInit() at the beginning of OSInit().
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts should be disabled during this call.
+*              2) When using hardware floating point please do the following during the reset handler:
+*                 a) Set full access for CP10 & CP11 bits in CPACR register.
+*                 b) Set bits ASPEN and LSPEN in FPCCR register.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSInitHookBegin (void)
+{
+    INT32U   size;
+    OS_STK  *pstk;
+#if (OS_CPU_ARM_FP_EN > 0u)
+    INT32U   reg_val;
+#endif
+                                                                /* Clear exception stack for stack checking.            */
+    pstk = &OS_CPU_ExceptStk[0];
+    size = OS_CPU_EXCEPT_STK_SIZE;
+    while (size > 0u) {
+        size--;
+       *pstk++ = (OS_STK)0;
+    }
+
+                                                                /* Align the ISR stack to 8-bytes                       */
+    OS_CPU_ExceptStkBase = (OS_STK *)&OS_CPU_ExceptStk[OS_CPU_EXCEPT_STK_SIZE];
+    OS_CPU_ExceptStkBase = (OS_STK *)((OS_STK)(OS_CPU_ExceptStkBase) & 0xFFFFFFF8);
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+    reg_val = OS_CPU_CM_FP_FPCCR;                               /* Check the floating point mode.                       */
+    if ((reg_val & OS_CPU_CM_FPCCR_LAZY_STK) != OS_CPU_CM_FPCCR_LAZY_STK) {
+        while (1u) {                                            /* See Note (2).                                        */
+            ;
+        }
+    }
+#endif
+
+#if OS_TMR_EN > 0u
+    OSTmrCtr = 0u;
+#endif
+
+                                                                /* Set BASEPRI boundary from the configuration.         */
+    OS_KA_BASEPRI_Boundary = (INT32U)(CPU_CFG_KA_IPL_BOUNDARY << (8u - CPU_CFG_NVIC_PRIO_BITS));
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       OS INITIALIZATION HOOK
+*                                               (END)
+*
+* Description: This function is called by OSInit() at the end of OSInit().
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts should be disabled during this call.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSInitHookEnd (void)
+{
+
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          TASK CREATION HOOK
+*
+* Description: This function is called when a task is created.
+*
+* Arguments  : ptcb   is a pointer to the task control block of the task being created.
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTaskCreateHook (OS_TCB *ptcb)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskCreateHook(ptcb);
+#else
+    (void)ptcb;                                                 /* Prevent compiler warning                             */
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                           TASK DELETION HOOK
+*
+* Description: This function is called when a task is deleted.
+*
+* Arguments  : ptcb   is a pointer to the task control block of the task being deleted.
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTaskDelHook (OS_TCB *ptcb)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskDelHook(ptcb);
+#else
+    (void)ptcb;                                                 /* Prevent compiler warning                             */
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                             IDLE TASK HOOK
+*
+* Description: This function is called by the idle task.  This hook has been added to allow you to do
+*              such things as STOP the CPU to conserve power.
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts are enabled during this call.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTaskIdleHook (void)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskIdleHook();
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                            TASK RETURN HOOK
+*
+* Description: This function is called if a task accidentally returns.  In other words, a task should
+*              either be an infinite loop or delete itself when done.
+*
+* Arguments  : ptcb      is a pointer to the task control block of the task that is returning.
+*
+* Note(s)    : none
+*********************************************************************************************************
+*/
+
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTaskReturnHook (OS_TCB  *ptcb)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskReturnHook(ptcb);
+#else
+    (void)ptcb;
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                           STATISTIC TASK HOOK
+*
+* Description: This function is called every second by uC/OS-II's statistics task.  This allows your
+*              application to add functionality to the statistics task.
+*
+* Arguments  : none
+*********************************************************************************************************
+*/
+
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTaskStatHook (void)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskStatHook();
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                        INITIALIZE A TASK'S STACK
+*
+* Description: This function is called by either OSTaskCreate() or OSTaskCreateExt() to initialize the
+*              stack frame of the task being created.  This function is highly processor specific.
+*
+* Arguments  : task          is a pointer to the task code
+*
+*              p_arg         is a pointer to a user supplied data area that will be passed to the task
+*                            when the task first executes.
+*
+*              ptos          is a pointer to the top of stack.  It is assumed that 'ptos' points to
+*                            a 'free' entry on the task stack.  If OS_STK_GROWTH is set to 1 then
+*                            'ptos' will contain the HIGHEST valid address of the stack.  Similarly, if
+*                            OS_STK_GROWTH is set to 0, the 'ptos' will contains the LOWEST valid address
+*                            of the stack.
+*
+*              opt           specifies options that can be used to alter the behavior of OSTaskStkInit().
+*                            (see uCOS_II.H for OS_TASK_OPT_xxx).
+*
+* Returns    : Always returns the location of the new top-of-stack once the processor registers have
+*              been placed on the stack in the proper order.
+*
+* Note(s)    : (1) Interrupts are enabled when task starts executing.
+*
+*              (2) All tasks run in Thread mode, using process stack.
+*
+*              (3) There are two different stack frames depending on whether the Floating-Point(FP)
+*                  co-processor is enabled or not.
+*
+*                  (a) The stack frame shown in the diagram is used when the Co-processor Access Control
+*                      Register(CPACR) is disabling the Floating Point Unit. In this case, the FP
+*                      registers(S0- S31) & FP Status Control(FPSCR) register are not saved in the stack frame.
+*
+*                  (b) The stack frame shown in the diagram is used when the Floating Point Unit is enabled,
+*                      that is, CP10 and CP11 field in CPACR are ones and FPCCR sets bits ASPEN and LSPEN to 1.
+*
+*                      (1) When enabling the FPU through CPACR, make sure to set bits ASPEN and LSPEN in the
+*                          Floating-Point Context Control Register (FPCCR).
+*
+*                                          +-------------+
+*                                          |             |
+*                                          +-------------+
+*                                          |             |
+*                                          +-------------+
+*                                          |    FPSCR    |
+*                                          +-------------+
+*                                          |     S15     |
+*                                          +-------------+
+*                                          |     S14     |
+*                                          +-------------+
+*                                          |     S13     |
+*                                          +-------------+
+*                                                .
+*                                                .
+*                                                .
+*                                          +-------------+
+*                                          |     S2      |
+*                                          +-------------+
+*                                          |     S1      |
+*                    +-------------+       +-------------+
+*                    |             |       |     S0      |
+*                    +-------------+       +-------------+
+*                    |    xPSR     |       |    xPSR     |
+*                    +-------------+       +-------------+
+*                    | Return Addr |       | Return Addr |
+*                    +-------------+       +-------------+
+*                    |  LR(R14)    |       |   LR(R14)   |
+*                    +-------------+       +-------------+
+*                    |    R12      |       |     R12     |
+*                    +-------------+       +-------------+
+*                    |    R3       |       |     R3      |
+*                    +-------------+       +-------------+
+*                    |    R2       |       |     R0      |
+*                    +-------------+       +-------------+
+*                    |    R1       |       |     R1      |
+*                    +-------------+       +-------------+
+*                    |    R0       |       |     R0      |
+*                    +-------------+       +-------------+
+*                    | EXEC_RETURN |       | EXEC_RETURN |
+*                    +-------------+       +-------------+
+*                    |    R11      |       |     R11     |
+*                    +-------------+       +-------------+
+*                    |    R10      |       |     R10     |
+*                    +-------------+       +-------------+
+*                    |    R9       |       |     R9      |
+*                    +-------------+       +-------------+
+*                    |    R8       |       |     R8      |
+*                    +-------------+       +-------------+
+*                    |    R7       |       |     R7      |
+*                    +-------------+       +-------------+
+*                    |    R6       |       |     R6      |
+*                    +-------------+       +-------------+
+*                    |    R5       |       |     R5      |
+*                    +-------------+       +-------------+
+*                    |    R4       |       |     R4      |
+*                    +-------------+       +-------------+
+*                          (a)             |     S31     |
+*                                          +-------------+
+*                                          |     S30     |
+*                                          +-------------+
+*                                          |     S29     |
+                                           +-------------+
+*                                                .
+*                                                .
+*                                                .
+*                                          +-------------+
+*                                          |     S17     |
+                                           +-------------+
+*                                          |     S16     |
+*                                          +-------------+
+*                                               (b)
+*
+*             (4) The SP must be 8-byte aligned in conforming to the Procedure Call Standard for the ARM architecture
+*
+*                    (a) Section 2.1 of the  ABI for the ARM Architecture Advisory Note. SP must be 8-byte aligned
+*                        on entry to AAPCS-Conforming functions states :
+*
+*                        The Procedure Call Standard for the ARM Architecture [AAPCS] requires primitive
+*                        data types to be naturally aligned according to their sizes (for size = 1, 2, 4, 8 bytes).
+*                        Doing otherwise creates more problems than it solves.
+*
+*                        In return for preserving the natural alignment of data, conforming code is permitted
+*                        to rely on that alignment. To support aligning data allocated on the stack, the stack
+*                        pointer (SP) is required to be 8-byte aligned on entry to a conforming function. In
+*                        practice this requirement is met if:
+*
+*                           (1) At each call site, the current size of the calling function's stack frame is a multiple of 8 bytes.
+*                               This places an obligation on compilers and assembly language programmers.
+*
+*                           (2) SP is a multiple of 8 when control first enters a program.
+*                               This places an obligation on authors of low level OS, RTOS, and runtime library
+*                               code to align SP at all points at which control first enters
+*                               a body of (AAPCS-conforming) code.
+*
+*                       In turn, this requires the value of SP to be aligned to 0 modulo 8:
+*
+*                           (3) By exception handlers, before calling AAPCS-conforming code.
+*
+*                           (4) By OS/RTOS/run-time system code, before giving control to an application.
+*
+*                 (b) Section 2.3.1 corrective steps from the the SP must be 8-byte aligned on entry
+*                     to AAPCS-conforming functions advisory note also states.
+*
+*                     " This requirement extends to operating systems and run-time code for all architecture versions
+*                       prior to ARMV7 and to the A, R and M architecture profiles thereafter. Special considerations
+*                       associated with ARMV7M are discussed in section 2.3.3"
+*
+*                     (1) Even if the SP 8-byte aligment is not a requirement for the ARMv7M profile, the stack is aligned
+*                         to 8-byte boundaries to support legacy execution enviroments.
+*
+*                 (c) Section 5.2.1.2 from the Procedure Call Standard for the ARM
+*                     architecture states :  "The stack must also conform to the following
+*                     constraint at a public interface:
+*
+*                     (1) SP mod 8 = 0. The stack must be double-word aligned"
+*
+*                 (d) From the ARM Technical Support Knowledge Base. 8 Byte stack aligment.
+*
+*                     "8 byte stack alignment is a requirement of the ARM Architecture Procedure
+*                      Call Standard [AAPCS]. This specifies that functions must maintain an 8 byte
+*                      aligned stack address (e.g. 0x00, 0x08, 0x10, 0x18, 0x20) on all external
+*                      interfaces. In practice this requirement is met if:
+*
+*                      (1) At each external interface, the current stack pointer
+*                          is a multiple of 8 bytes.
+*
+*                      (2) Your OS maintains 8 byte stack alignment on its external interfaces
+*                          e.g. on task switches"
+*
+*              (5) Exception Return Behavior(EXEC_RETURN)
+*                  0xFFFFFFFD      Return to Thread mode, exception return uses non-floating point state
+*                                  from the PSP and execution uses PSP after return.
+*
+*                  0xFFFFFFED      Return to Thread mode, exception return uses floating point state
+*                                  from the PSP and execution uses PSP after return.
+**********************************************************************************************************
+*/
+
+OS_STK  *OSTaskStkInit (void    (*task)(void *p_arg),
+                        void     *p_arg,
+                        OS_STK   *ptos,
+                        INT16U    opt)
+{
+    OS_STK  *p_stk;
+
+
+    (void)opt;                                                  /* 'opt' is not used, prevent warning                   */
+    p_stk      = ptos + 1u;                                     /* Load stack pointer                                   */
+                                                                /* Align the stack to 8-bytes.                          */
+    p_stk      = (OS_STK *)((OS_STK)(p_stk) & 0xFFFFFFF8u);
+                                                                /* Registers stacked as if auto-saved on exception      */
+#if (OS_CPU_ARM_FP_EN > 0u)                                     /* FPU auto-saved registers.                            */
+     --p_stk;
+    *(--p_stk) = (OS_STK)0x02000000u;                           /* FPSCR                                                */
+                                                                /* Initialize S0-S15 floating point registers           */
+    *(--p_stk) = (OS_STK)0x41700000u;                           /* S15                                                  */
+    *(--p_stk) = (OS_STK)0x41600000u;                           /* S14                                                  */
+    *(--p_stk) = (OS_STK)0x41500000u;                           /* S13                                                  */
+    *(--p_stk) = (OS_STK)0x41400000u;                           /* S12                                                  */
+    *(--p_stk) = (OS_STK)0x41300000u;                           /* S11                                                  */
+    *(--p_stk) = (OS_STK)0x41200000u;                           /* S10                                                  */
+    *(--p_stk) = (OS_STK)0x41100000u;                           /* S9                                                   */
+    *(--p_stk) = (OS_STK)0x41000000u;                           /* S8                                                   */
+    *(--p_stk) = (OS_STK)0x40E00000u;                           /* S7                                                   */
+    *(--p_stk) = (OS_STK)0x40C00000u;                           /* S6                                                   */
+    *(--p_stk) = (OS_STK)0x40A00000u;                           /* S5                                                   */
+    *(--p_stk) = (OS_STK)0x40800000u;                           /* S4                                                   */
+    *(--p_stk) = (OS_STK)0x40400000u;                           /* S3                                                   */
+    *(--p_stk) = (OS_STK)0x40000000u;                           /* S2                                                   */
+    *(--p_stk) = (OS_STK)0x3F800000u;                           /* S1                                                   */
+    *(--p_stk) = (OS_STK)0x00000000u;                           /* S0                                                   */
+#endif
+    *(--p_stk) = (OS_STK)0x01000000uL;                          /* xPSR                                                 */
+    *(--p_stk) = (OS_STK)task;                                  /* Entry Point                                          */
+    *(--p_stk) = (OS_STK)OS_TaskReturn;                         /* R14 (LR)                                             */
+    *(--p_stk) = (OS_STK)0x12121212uL;                          /* R12                                                  */
+    *(--p_stk) = (OS_STK)0x03030303uL;                          /* R3                                                   */
+    *(--p_stk) = (OS_STK)0x02020202uL;                          /* R2                                                   */
+    *(--p_stk) = (OS_STK)0x01010101uL;                          /* R1                                                   */
+    *(--p_stk) = (OS_STK)p_arg;                                 /* R0 : argument                                        */
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+    *(--p_stk) = (OS_STK)0xFFFFFFEDuL;                          /* R14: EXEC_RETURN; See Note 5                         */
+#else
+    *(--p_stk) = (OS_STK)0xFFFFFFFDuL;                          /* R14: EXEC_RETURN; See Note 5                         */
+#endif
+                                                                /* Remaining registers saved on process stack           */
+    *(--p_stk) = (OS_STK)0x11111111uL;                          /* R11                                                  */
+    *(--p_stk) = (OS_STK)0x10101010uL;                          /* R10                                                  */
+    *(--p_stk) = (OS_STK)0x09090909uL;                          /* R9                                                   */
+    *(--p_stk) = (OS_STK)0x08080808uL;                          /* R8                                                   */
+    *(--p_stk) = (OS_STK)0x07070707uL;                          /* R7                                                   */
+    *(--p_stk) = (OS_STK)0x06060606uL;                          /* R6                                                   */
+    *(--p_stk) = (OS_STK)0x05050505uL;                          /* R5                                                   */
+    *(--p_stk) = (OS_STK)0x04040404uL;                          /* R4                                                   */
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+                                                                /* Initialize S16-S31 floating point registers          */
+    *(--p_stk) = (OS_STK)0x41F80000u;                           /* S31                                                  */
+    *(--p_stk) = (OS_STK)0x41F00000u;                           /* S30                                                  */
+    *(--p_stk) = (OS_STK)0x41E80000u;                           /* S29                                                  */
+    *(--p_stk) = (OS_STK)0x41E00000u;                           /* S28                                                  */
+    *(--p_stk) = (OS_STK)0x41D80000u;                           /* S27                                                  */
+    *(--p_stk) = (OS_STK)0x41D00000u;                           /* S26                                                  */
+    *(--p_stk) = (OS_STK)0x41C80000u;                           /* S25                                                  */
+    *(--p_stk) = (OS_STK)0x41C00000u;                           /* S24                                                  */
+    *(--p_stk) = (OS_STK)0x41B80000u;                           /* S23                                                  */
+    *(--p_stk) = (OS_STK)0x41B00000u;                           /* S22                                                  */
+    *(--p_stk) = (OS_STK)0x41A80000u;                           /* S21                                                  */
+    *(--p_stk) = (OS_STK)0x41A00000u;                           /* S20                                                  */
+    *(--p_stk) = (OS_STK)0x41980000u;                           /* S19                                                  */
+    *(--p_stk) = (OS_STK)0x41900000u;                           /* S18                                                  */
+    *(--p_stk) = (OS_STK)0x41880000u;                           /* S17                                                  */
+    *(--p_stk) = (OS_STK)0x41800000u;                           /* S16                                                  */
+#endif
+
+    return (p_stk);
+}
+
+
+/*
+*********************************************************************************************************
+*                                           TASK SWITCH HOOK
+*
+* Description: This function is called when a task switch is performed.  This allows you to perform other
+*              operations during a context switch.
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts are disabled during this call.
+*              2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
+*                 will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                 task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+#if (OS_CPU_HOOKS_EN > 0u) && (OS_TASK_SW_HOOK_EN > 0u)
+void  OSTaskSwHook (void)
+{
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+    OS_CPU_FP_Reg_Push(OSTCBCur->OSTCBStkPtr);                  /* Push the FP registers of the current task.           */
+#endif
+
+#if OS_APP_HOOKS_EN > 0u
+    App_TaskSwHook();
+#endif
+
+    OS_TRACE_TASK_SWITCHED_IN(OSTCBHighRdy);
+
+#if (OS_CPU_ARM_FP_EN > 0u)
+    OS_CPU_FP_Reg_Pop(OSTCBHighRdy->OSTCBStkPtr);               /* Pop the FP registers of the highest ready task.      */
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                           OS_TCBInit() HOOK
+*
+* Description: This function is called by OS_TCBInit() after setting up most of the TCB.
+*
+* Arguments  : ptcb    is a pointer to the TCB of the task being created.
+*
+* Note(s)    : 1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+#if OS_CPU_HOOKS_EN > 0u
+void  OSTCBInitHook (OS_TCB *ptcb)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TCBInitHook(ptcb);
+#else
+    (void)ptcb;                                                 /* Prevent compiler warning                             */
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                               TICK HOOK
+*
+* Description: This function is called every tick.
+*
+* Arguments  : none
+*
+* Note(s)    : 1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+#if (OS_CPU_HOOKS_EN > 0u) && (OS_TIME_TICK_HOOK_EN > 0u)
+void  OSTimeTickHook (void)
+{
+#if OS_APP_HOOKS_EN > 0u
+    App_TimeTickHook();
+#endif
+
+#if OS_TMR_EN > 0u
+    OSTmrCtr++;
+    if (OSTmrCtr >= (OS_TICKS_PER_SEC / OS_TMR_CFG_TICKS_PER_SEC)) {
+        OSTmrCtr = 0u;
+        OSTmrSignal();
+    }
+#endif
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          SYS TICK HANDLER
+*
+* Description: Handle the system tick (SysTick) interrupt, which is used to generate the uC/OS-II tick
+*              interrupt.
+*
+* Arguments  : None.
+*
+* Note(s)    : 1) This function MUST be placed on entry 15 of the Cortex-M vector table.
+*********************************************************************************************************
+*/
+
+void  OS_CPU_SysTickHandler (void)
+{
+#if OS_CRITICAL_METHOD == 3u                                    /* Allocate storage for CPU status register             */
+    OS_CPU_SR  cpu_sr;
+#endif
+
+
+    OS_ENTER_CRITICAL();
+    OSIntEnter();                                               /* Tell uC/OS-II that we are starting an ISR            */
+    OS_EXIT_CRITICAL();
+
+    OSTimeTick();                                               /* Call uC/OS-II's OSTimeTick()                         */
+
+    OSIntExit();                                                /* Tell uC/OS-II that we are leaving the ISR            */
+}
+
+
+/*
+*********************************************************************************************************
+*                                         INITIALIZE SYS TICK
+*
+* Description: Initialize the SysTick using the CPU clock frequency.
+*
+* Arguments  : cpu_freq     CPU clock frequency.
+*
+* Note(s)    : 1) This function MUST be called after OSStart() & after processor initialization.
+*
+*              2) Either OS_CPU_SysTickInitFreq or OS_CPU_SysTickInit() can be called.
+*********************************************************************************************************
+*/
+
+void  OS_CPU_SysTickInitFreq (INT32U  cpu_freq)
+{
+    INT32U  cnts;
+
+
+    cnts = (cpu_freq / (INT32U)OS_TICKS_PER_SEC);               /* Determine nbr SysTick cnts between two OS tick intr. */
+
+    OS_CPU_SysTickInit(cnts);
+}
+
+
+/*
+*********************************************************************************************************
+*                                         INITIALIZE SYS TICK
+*
+* Description: Initialize the SysTick using the number of counts between two ticks.
+*
+* Arguments  : cnts     Number of SysTick counts between two OS tick interrupts.
+*
+* Note(s)    : 1) This function MUST be called after OSStart() & after processor initialization.
+*
+*              2) Either OS_CPU_SysTickInitFreq or OS_CPU_SysTickInit() can be called.
+*********************************************************************************************************
+*/
+
+void  OS_CPU_SysTickInit (INT32U  cnts)
+{
+    INT32U  prio;
+    INT32U  basepri;
+
+
+                                                                /* Set BASEPRI boundary from the configuration.         */
+    basepri               = (INT32U)(CPU_CFG_KA_IPL_BOUNDARY << (8u - CPU_CFG_NVIC_PRIO_BITS));
+    OS_CPU_CM_SYST_RVR    = cnts - 1u;                          /* Set Reload register.                                 */
+
+                                                                /* Set SysTick handler prio.                            */
+    prio                  =  OS_CPU_CM_SCB_SHPRI3;
+    prio                 &=  0x00FFFFFFu;
+    prio                 |= (basepri << 24u);
+    OS_CPU_CM_SCB_SHPRI3  = prio;
+
+                                                                /* Enable timer.                                        */
+    OS_CPU_CM_SYST_CSR   |= OS_CPU_CM_SYST_CSR_CLKSOURCE |
+                            OS_CPU_CM_SYST_CSR_ENABLE;
+                                                                /* Enable timer interrupt.                              */
+    OS_CPU_CM_SYST_CSR   |= OS_CPU_CM_SYST_CSR_TICKINT;
+}

Core/OS/Ports/os_dbg.c

@@ -0,0 +1,328 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                             ARMv7-M Port
+*                                          DEBUGGER CONSTANTS
+*
+* Filename  : os_dbg.c
+* Version   : V2.93.00
+*********************************************************************************************************
+* For       : ARMv7-M Cortex-M
+* Mode      : Thumb-2 ISA
+* Toolchain : IAR EWARM
+*********************************************************************************************************
+* Note(s)   : (1) This port supports the ARM Cortex-M3, Cortex-M4 and Cortex-M7 architectures.
+*             (2) It has been tested with the following Hardware Floating Point Unit.
+*                 (a) Single-precision: FPv4-SP-D16-M and FPv5-SP-D16-M
+*                 (b) Double-precision: FPv5-D16-M
+*********************************************************************************************************
+*/
+
+#include <ucos_ii.h>
+
+#define  OS_COMPILER_OPT  __root
+
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*********************************************************************************************************
+*/
+
+OS_COMPILER_OPT  INT16U  const  OSDebugEn           = OS_DEBUG_EN;               /* Debug constants are defined below   */
+
+#if OS_DEBUG_EN > 0u
+
+OS_COMPILER_OPT  INT32U  const  OSEndiannessTest    = 0x12345678L;               /* Variable to test CPU endianness     */
+
+OS_COMPILER_OPT  INT16U  const  OSEventEn           = OS_EVENT_EN;
+OS_COMPILER_OPT  INT16U  const  OSEventMax          = OS_MAX_EVENTS;             /* Number of event control blocks      */
+OS_COMPILER_OPT  INT16U  const  OSEventNameEn       = OS_EVENT_NAME_EN;
+#if (OS_EVENT_EN > 0u) && (OS_MAX_EVENTS > 0u)
+OS_COMPILER_OPT  INT16U  const  OSEventSize         = sizeof(OS_EVENT);          /* Size in Bytes of OS_EVENT           */
+OS_COMPILER_OPT  INT16U  const  OSEventTblSize      = sizeof(OSEventTbl);        /* Size of OSEventTbl[] in bytes       */
+#else
+OS_COMPILER_OPT  INT16U  const  OSEventSize         = 0u;
+OS_COMPILER_OPT  INT16U  const  OSEventTblSize      = 0u;
+#endif
+OS_COMPILER_OPT  INT16U  const  OSEventMultiEn      = OS_EVENT_MULTI_EN;
+
+
+OS_COMPILER_OPT  INT16U  const  OSFlagEn            = OS_FLAG_EN;
+#if (OS_FLAG_EN > 0u) && (OS_MAX_FLAGS > 0u)
+OS_COMPILER_OPT  INT16U  const  OSFlagGrpSize       = sizeof(OS_FLAG_GRP);       /* Size in Bytes of OS_FLAG_GRP        */
+OS_COMPILER_OPT  INT16U  const  OSFlagNodeSize      = sizeof(OS_FLAG_NODE);      /* Size in Bytes of OS_FLAG_NODE       */
+OS_COMPILER_OPT  INT16U  const  OSFlagWidth         = sizeof(OS_FLAGS);          /* Width (in bytes) of OS_FLAGS        */
+#else
+OS_COMPILER_OPT  INT16U  const  OSFlagGrpSize       = 0u;
+OS_COMPILER_OPT  INT16U  const  OSFlagNodeSize      = 0u;
+OS_COMPILER_OPT  INT16U  const  OSFlagWidth         = 0u;
+#endif
+OS_COMPILER_OPT  INT16U  const  OSFlagMax           = OS_MAX_FLAGS;
+OS_COMPILER_OPT  INT16U  const  OSFlagNameEn        = OS_FLAG_NAME_EN;
+
+OS_COMPILER_OPT  INT16U  const  OSLowestPrio        = OS_LOWEST_PRIO;
+
+OS_COMPILER_OPT  INT16U  const  OSMboxEn            = OS_MBOX_EN;
+
+OS_COMPILER_OPT  INT16U  const  OSMemEn             = OS_MEM_EN;
+OS_COMPILER_OPT  INT16U  const  OSMemMax            = OS_MAX_MEM_PART;           /* Number of memory partitions         */
+OS_COMPILER_OPT  INT16U  const  OSMemNameEn         = OS_MEM_NAME_EN;
+#if (OS_MEM_EN > 0u) && (OS_MAX_MEM_PART > 0u)
+OS_COMPILER_OPT  INT16U  const  OSMemSize           = sizeof(OS_MEM);            /* Mem. Partition header sine (bytes)  */
+OS_COMPILER_OPT  INT16U  const  OSMemTblSize        = sizeof(OSMemTbl);
+#else
+OS_COMPILER_OPT  INT16U  const  OSMemSize           = 0u;
+OS_COMPILER_OPT  INT16U  const  OSMemTblSize        = 0u;
+#endif
+OS_COMPILER_OPT  INT16U  const  OSMutexEn           = OS_MUTEX_EN;
+
+OS_COMPILER_OPT  INT16U  const  OSPtrSize           = sizeof(void *);            /* Size in Bytes of a pointer          */
+
+OS_COMPILER_OPT  INT16U  const  OSQEn               = OS_Q_EN;
+OS_COMPILER_OPT  INT16U  const  OSQMax              = OS_MAX_QS;                 /* Number of queues                    */
+#if (OS_Q_EN > 0u) && (OS_MAX_QS > 0u)
+OS_COMPILER_OPT  INT16U  const  OSQSize             = sizeof(OS_Q);              /* Size in bytes of OS_Q structure     */
+#else
+OS_COMPILER_OPT  INT16U  const  OSQSize             = 0u;
+#endif
+
+OS_COMPILER_OPT  INT16U  const  OSRdyTblSize        = OS_RDY_TBL_SIZE;           /* Number of bytes in the ready table  */
+
+OS_COMPILER_OPT  INT16U  const  OSSemEn             = OS_SEM_EN;
+
+OS_COMPILER_OPT  INT16U  const  OSStkWidth          = sizeof(OS_STK);            /* Size in Bytes of a stack entry      */
+
+OS_COMPILER_OPT  INT16U  const  OSTaskCreateEn      = OS_TASK_CREATE_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskCreateExtEn   = OS_TASK_CREATE_EXT_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskDelEn         = OS_TASK_DEL_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskIdleStkSize   = OS_TASK_IDLE_STK_SIZE;
+OS_COMPILER_OPT  INT16U  const  OSTaskProfileEn     = OS_TASK_PROFILE_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskMax           = OS_MAX_TASKS + OS_N_SYS_TASKS; /* Total max. number of tasks      */
+OS_COMPILER_OPT  INT16U  const  OSTaskNameEn        = OS_TASK_NAME_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskStatEn        = OS_TASK_STAT_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskStatStkSize   = OS_TASK_STAT_STK_SIZE;
+OS_COMPILER_OPT  INT16U  const  OSTaskStatStkChkEn  = OS_TASK_STAT_STK_CHK_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskSwHookEn      = OS_TASK_SW_HOOK_EN;
+OS_COMPILER_OPT  INT16U  const  OSTaskRegTblSize    = OS_TASK_REG_TBL_SIZE;
+
+OS_COMPILER_OPT  INT16U  const  OSTCBPrioTblMax     = OS_LOWEST_PRIO + 1u;       /* Number of entries in OSTCBPrioTbl[] */
+OS_COMPILER_OPT  INT16U  const  OSTCBSize           = sizeof(OS_TCB);            /* Size in Bytes of OS_TCB             */
+OS_COMPILER_OPT  INT16U  const  OSTicksPerSec       = OS_TICKS_PER_SEC;
+OS_COMPILER_OPT  INT16U  const  OSTimeTickHookEn    = OS_TIME_TICK_HOOK_EN;
+OS_COMPILER_OPT  INT16U  const  OSVersionNbr        = OS_VERSION;
+
+OS_COMPILER_OPT  INT16U  const  OSTmrEn             = OS_TMR_EN;
+OS_COMPILER_OPT  INT16U  const  OSTmrCfgMax         = OS_TMR_CFG_MAX;
+OS_COMPILER_OPT  INT16U  const  OSTmrCfgNameEn      = OS_TMR_CFG_NAME_EN;
+OS_COMPILER_OPT  INT16U  const  OSTmrCfgWheelSize   = OS_TMR_CFG_WHEEL_SIZE;
+OS_COMPILER_OPT  INT16U  const  OSTmrCfgTicksPerSec = OS_TMR_CFG_TICKS_PER_SEC;
+
+#if (OS_TMR_EN > 0u) && (OS_TMR_CFG_MAX > 0u)
+OS_COMPILER_OPT  INT16U  const  OSTmrSize           = sizeof(OS_TMR);
+OS_COMPILER_OPT  INT16U  const  OSTmrTblSize        = sizeof(OSTmrTbl);
+OS_COMPILER_OPT  INT16U  const  OSTmrWheelSize      = sizeof(OS_TMR_WHEEL);
+OS_COMPILER_OPT  INT16U  const  OSTmrWheelTblSize   = sizeof(OSTmrWheelTbl);
+#else
+OS_COMPILER_OPT  INT16U  const  OSTmrSize           = 0u;
+OS_COMPILER_OPT  INT16U  const  OSTmrTblSize        = 0u;
+OS_COMPILER_OPT  INT16U  const  OSTmrWheelSize      = 0u;
+OS_COMPILER_OPT  INT16U  const  OSTmrWheelTblSize   = 0u;
+#endif
+
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*                            TOTAL DATA SPACE (i.e. RAM) USED BY uC/OS-II
+*********************************************************************************************************
+*/
+#if OS_DEBUG_EN > 0u
+
+OS_COMPILER_OPT  INT16U  const  OSDataSize = sizeof(OSCtxSwCtr)
+#if (OS_EVENT_EN > 0u) && (OS_MAX_EVENTS > 0u)
+                          + sizeof(OSEventFreeList)
+                          + sizeof(OSEventTbl)
+#endif
+#if (OS_FLAG_EN > 0u) && (OS_MAX_FLAGS > 0u)
+                          + sizeof(OSFlagTbl)
+                          + sizeof(OSFlagFreeList)
+#endif
+#if OS_TASK_STAT_EN > 0u
+                          + sizeof(OSCPUUsage)
+                          + sizeof(OSIdleCtrMax)
+                          + sizeof(OSIdleCtrRun)
+                          + sizeof(OSStatRdy)
+                          + sizeof(OSTaskStatStk)
+#endif
+#if OS_TICK_STEP_EN > 0u
+                          + sizeof(OSTickStepState)
+#endif
+#if (OS_MEM_EN > 0u) && (OS_MAX_MEM_PART > 0u)
+                          + sizeof(OSMemFreeList)
+                          + sizeof(OSMemTbl)
+#endif
+#if (OS_Q_EN > 0u) && (OS_MAX_QS > 0u)
+                          + sizeof(OSQFreeList)
+                          + sizeof(OSQTbl)
+#endif
+#if OS_TIME_GET_SET_EN > 0u
+                          + sizeof(OSTime)
+#endif
+#if (OS_TMR_EN > 0u) && (OS_TMR_CFG_MAX > 0u)
+                          + sizeof(OSTmrFree)
+                          + sizeof(OSTmrUsed)
+                          + sizeof(OSTmrTime)
+                          + sizeof(OSTmrSem)
+                          + sizeof(OSTmrSemSignal)
+                          + sizeof(OSTmrTbl)
+                          + sizeof(OSTmrFreeList)
+                          + sizeof(OSTmrTaskStk)
+                          + sizeof(OSTmrWheelTbl)
+#endif
+                          + sizeof(OSIntNesting)
+                          + sizeof(OSLockNesting)
+                          + sizeof(OSPrioCur)
+                          + sizeof(OSPrioHighRdy)
+                          + sizeof(OSRdyGrp)
+                          + sizeof(OSRdyTbl)
+                          + sizeof(OSRunning)
+                          + sizeof(OSTaskCtr)
+                          + sizeof(OSIdleCtr)
+                          + sizeof(OSTaskIdleStk)
+                          + sizeof(OSTCBCur)
+                          + sizeof(OSTCBFreeList)
+                          + sizeof(OSTCBHighRdy)
+                          + sizeof(OSTCBList)
+                          + sizeof(OSTCBPrioTbl)
+                          + sizeof(OSTCBTbl);
+
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                        OS DEBUG INITIALIZATION
+*
+* Description: This function is used to make sure that debug variables that are unused in the application
+*              are not optimized away.  This function might not be necessary for all compilers.  In this
+*              case, you should simply DELETE the code in this function while still leaving the declaration
+*              of the function itself.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Note(s)    : (1) This code doesn't do anything, it simply prevents the compiler from optimizing out
+*                  the 'const' variables which are declared in this file.
+*              (2) You may decide to 'compile out' the code (by using #if 0/#endif) INSIDE the function
+*                  if your compiler DOES NOT optimize out the 'const' variables above.
+*********************************************************************************************************
+*/
+
+#if OS_DEBUG_EN > 0u
+void  OSDebugInit (void)
+{
+    void  *ptemp;
+
+
+    ptemp = (void *)&OSDebugEn;
+
+    ptemp = (void *)&OSEndiannessTest;
+
+    ptemp = (void *)&OSEventMax;
+    ptemp = (void *)&OSEventNameEn;
+    ptemp = (void *)&OSEventEn;
+    ptemp = (void *)&OSEventSize;
+    ptemp = (void *)&OSEventTblSize;
+    ptemp = (void *)&OSEventMultiEn;
+
+    ptemp = (void *)&OSFlagEn;
+    ptemp = (void *)&OSFlagGrpSize;
+    ptemp = (void *)&OSFlagNodeSize;
+    ptemp = (void *)&OSFlagWidth;
+    ptemp = (void *)&OSFlagMax;
+    ptemp = (void *)&OSFlagNameEn;
+
+    ptemp = (void *)&OSLowestPrio;
+
+    ptemp = (void *)&OSMboxEn;
+
+    ptemp = (void *)&OSMemEn;
+    ptemp = (void *)&OSMemMax;
+    ptemp = (void *)&OSMemNameEn;
+    ptemp = (void *)&OSMemSize;
+    ptemp = (void *)&OSMemTblSize;
+
+    ptemp = (void *)&OSMutexEn;
+
+    ptemp = (void *)&OSPtrSize;
+
+    ptemp = (void *)&OSQEn;
+    ptemp = (void *)&OSQMax;
+    ptemp = (void *)&OSQSize;
+
+    ptemp = (void *)&OSRdyTblSize;
+
+    ptemp = (void *)&OSSemEn;
+
+    ptemp = (void *)&OSStkWidth;
+
+    ptemp = (void *)&OSTaskCreateEn;
+    ptemp = (void *)&OSTaskCreateExtEn;
+    ptemp = (void *)&OSTaskDelEn;
+    ptemp = (void *)&OSTaskIdleStkSize;
+    ptemp = (void *)&OSTaskProfileEn;
+    ptemp = (void *)&OSTaskMax;
+    ptemp = (void *)&OSTaskNameEn;
+    ptemp = (void *)&OSTaskStatEn;
+    ptemp = (void *)&OSTaskStatStkSize;
+    ptemp = (void *)&OSTaskStatStkChkEn;
+    ptemp = (void *)&OSTaskSwHookEn;
+
+    ptemp = (void *)&OSTCBPrioTblMax;
+    ptemp = (void *)&OSTCBSize;
+
+    ptemp = (void *)&OSTicksPerSec;
+    ptemp = (void *)&OSTimeTickHookEn;
+
+#if OS_TMR_EN > 0u
+    ptemp = (void *)&OSTmrTbl[0];
+    ptemp = (void *)&OSTmrWheelTbl[0];
+
+    ptemp = (void *)&OSTmrEn;
+    ptemp = (void *)&OSTmrCfgMax;
+    ptemp = (void *)&OSTmrCfgNameEn;
+    ptemp = (void *)&OSTmrCfgWheelSize;
+    ptemp = (void *)&OSTmrCfgTicksPerSec;
+    ptemp = (void *)&OSTmrSize;
+    ptemp = (void *)&OSTmrTblSize;
+
+    ptemp = (void *)&OSTmrWheelSize;
+    ptemp = (void *)&OSTmrWheelTblSize;
+#endif
+
+    ptemp = (void *)&OSVersionNbr;
+
+    ptemp = (void *)&OSDataSize;
+
+    ptemp = ptemp;                             /* Prevent compiler warning for 'ptemp' not being used! */
+}
+#endif

Core/OS/Source/os.h

@@ -0,0 +1,36 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+* Filename : os.h
+* Version  : V2.93.00
+*********************************************************************************************************
+* Note : This file is included in the uC/OS-II for compatibility with uC/OS-III and should not be used
+*        in normal circumstances.
+*********************************************************************************************************
+*/
+
+#ifndef   OS_H
+#define   OS_H
+
+#include  "ucos_ii.h"
+
+
+typedef  INT8U  OS_ERR;
+
+#endif

Core/OS/Source/os_dbg_r.c

@@ -0,0 +1,342 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                          DEBUGGER CONSTANTS
+*
+* Filename : os_dbg_r.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#define  MICRIUM_SOURCE
+
+#include <ucos_ii.h>
+
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*********************************************************************************************************
+*/
+
+INT16U  const  OSDebugEn             = OS_DEBUG_EN;             /* Debug constants are defined below   */
+
+#if OS_DEBUG_EN > 0u
+
+INT32U  const  OSEndiannessTest      = 0x12345678uL;            /* Variable to test CPU endianness     */
+
+INT16U  const  OSEventEn             = OS_EVENT_EN;
+INT16U  const  OSEventMax            = OS_MAX_EVENTS;           /* Number of event control blocks      */
+INT16U  const  OSEventNameEn         = OS_EVENT_NAME_EN;
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0u)
+INT16U  const  OSEventSize           = sizeof(OS_EVENT);        /* Size in Bytes of OS_EVENT           */
+INT16U  const  OSEventTblSize        = sizeof(OSEventTbl);      /* Size of OSEventTbl[] in bytes       */
+#else
+INT16U  const  OSEventSize           = 0u;
+INT16U  const  OSEventTblSize        = 0u;
+#endif
+INT16U  const  OSEventMultiEn        = OS_EVENT_MULTI_EN;
+
+
+INT16U  const  OSFlagEn              = OS_FLAG_EN;
+#if (OS_FLAG_EN > 0u) && (OS_MAX_FLAGS > 0u)
+INT16U  const  OSFlagGrpSize         = sizeof(OS_FLAG_GRP);     /* Size in Bytes of OS_FLAG_GRP        */
+INT16U  const  OSFlagNodeSize        = sizeof(OS_FLAG_NODE);    /* Size in Bytes of OS_FLAG_NODE       */
+INT16U  const  OSFlagWidth           = sizeof(OS_FLAGS);        /* Width (in bytes) of OS_FLAGS        */
+#else
+INT16U  const  OSFlagGrpSize         = 0u;
+INT16U  const  OSFlagNodeSize        = 0u;
+INT16U  const  OSFlagWidth           = 0u;
+#endif
+INT16U  const  OSFlagMax             = OS_MAX_FLAGS;
+INT16U  const  OSFlagNameEn          = OS_FLAG_NAME_EN;
+
+INT16U  const  OSLowestPrio          = OS_LOWEST_PRIO;
+
+INT16U  const  OSMboxEn              = OS_MBOX_EN;
+
+INT16U  const  OSMemEn               = OS_MEM_EN;
+INT16U  const  OSMemMax              = OS_MAX_MEM_PART;         /* Number of memory partitions         */
+INT16U  const  OSMemNameEn           = OS_MEM_NAME_EN;
+#if (OS_MEM_EN > 0u) && (OS_MAX_MEM_PART > 0u)
+INT16U  const  OSMemSize             = sizeof(OS_MEM);          /* Mem. Partition header sine (bytes)  */
+INT16U  const  OSMemTblSize          = sizeof(OSMemTbl);
+#else
+INT16U  const  OSMemSize             = 0u;
+INT16U  const  OSMemTblSize          = 0u;
+#endif
+INT16U  const  OSMutexEn             = OS_MUTEX_EN;
+
+INT16U  const  OSPtrSize             = sizeof(void *);          /* Size in Bytes of a pointer          */
+
+INT16U  const  OSQEn                 = OS_Q_EN;
+INT16U  const  OSQMax                = OS_MAX_QS;               /* Number of queues                    */
+#if (OS_Q_EN > 0u) && (OS_MAX_QS > 0u)
+INT16U  const  OSQSize               = sizeof(OS_Q);            /* Size in bytes of OS_Q structure     */
+#else
+INT16U  const  OSQSize               = 0u;
+#endif
+
+INT16U  const  OSRdyTblSize          = OS_RDY_TBL_SIZE;         /* Number of bytes in the ready table  */
+
+INT16U  const  OSSemEn               = OS_SEM_EN;
+
+INT16U  const  OSStkWidth            = sizeof(OS_STK);          /* Size in Bytes of a stack entry      */
+
+INT16U  const  OSTaskCreateEn        = OS_TASK_CREATE_EN;
+INT16U  const  OSTaskCreateExtEn     = OS_TASK_CREATE_EXT_EN;
+INT16U  const  OSTaskDelEn           = OS_TASK_DEL_EN;
+INT16U  const  OSTaskIdleStkSize     = OS_TASK_IDLE_STK_SIZE;
+INT16U  const  OSTaskProfileEn       = OS_TASK_PROFILE_EN;
+INT16U  const  OSTaskMax             = OS_MAX_TASKS + OS_N_SYS_TASKS; /* Total max. number of tasks    */
+INT16U  const  OSTaskNameEn          = OS_TASK_NAME_EN;
+INT16U  const  OSTaskStatEn          = OS_TASK_STAT_EN;
+INT16U  const  OSTaskStatStkSize     = OS_TASK_STAT_STK_SIZE;
+INT16U  const  OSTaskStatStkChkEn    = OS_TASK_STAT_STK_CHK_EN;
+INT16U  const  OSTaskSwHookEn        = OS_TASK_SW_HOOK_EN;
+INT16U  const  OSTaskRegTblSize      = OS_TASK_REG_TBL_SIZE;
+
+INT16U  const  OSTCBPrioTblMax       = OS_LOWEST_PRIO + 1u;     /* Number of entries in OSTCBPrioTbl[] */
+INT16U  const  OSTCBSize             = sizeof(OS_TCB);          /* Size in Bytes of OS_TCB             */
+INT16U  const  OSTicksPerSec         = OS_TICKS_PER_SEC;
+INT16U  const  OSTimeTickHookEn      = OS_TIME_TICK_HOOK_EN;
+INT16U  const  OSVersionNbr          = OS_VERSION;
+
+#if OS_TASK_CREATE_EXT_EN > 0u
+#if defined(OS_TLS_TBL_SIZE) && (OS_TLS_TBL_SIZE > 0u)
+INT16U  const  OS_TLS_TblSize        = OS_TLS_TBL_SIZE * sizeof(OS_TLS);
+#else
+INT16U  const  OS_TLS_TblSize        = 0u;
+#endif
+#endif
+
+INT16U  const  OSTmrEn               = OS_TMR_EN;
+INT16U  const  OSTmrCfgMax           = OS_TMR_CFG_MAX;
+INT16U  const  OSTmrCfgNameEn        = OS_TMR_CFG_NAME_EN;
+INT16U  const  OSTmrCfgWheelSize     = OS_TMR_CFG_WHEEL_SIZE;
+INT16U  const  OSTmrCfgTicksPerSec   = OS_TMR_CFG_TICKS_PER_SEC;
+
+#if (OS_TMR_EN > 0u) && (OS_TMR_CFG_MAX > 0u)
+INT16U  const  OSTmrSize             = sizeof(OS_TMR);
+INT16U  const  OSTmrTblSize          = sizeof(OSTmrTbl);
+INT16U  const  OSTmrWheelSize        = sizeof(OS_TMR_WHEEL);
+INT16U  const  OSTmrWheelTblSize     = sizeof(OSTmrWheelTbl);
+#else
+INT16U  const  OSTmrSize             = 0u;
+INT16U  const  OSTmrTblSize          = 0u;
+INT16U  const  OSTmrWheelSize        = 0u;
+INT16U  const  OSTmrWheelTblSize     = 0u;
+#endif
+
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                             DEBUG DATA
+*                            TOTAL DATA SPACE (i.e. RAM) USED BY uC/OS-II
+*********************************************************************************************************
+*/
+#if OS_DEBUG_EN > 0u
+
+INT16U  const  OSDataSize = sizeof(OSCtxSwCtr)
+#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0u)
+                          + sizeof(OSEventFreeList)
+                          + sizeof(OSEventTbl)
+#endif
+
+#if (OS_FLAG_EN > 0u) && (OS_MAX_FLAGS > 0u)
+                          + sizeof(OSFlagTbl)
+                          + sizeof(OSFlagFreeList)
+#endif
+
+#if OS_TASK_STAT_EN > 0u
+                          + sizeof(OSCPUUsage)
+                          + sizeof(OSIdleCtrMax)
+                          + sizeof(OSIdleCtrRun)
+                          + sizeof(OSStatRdy)
+                          + sizeof(OSTaskStatStk)
+#endif
+
+#if OS_TICK_STEP_EN > 0u
+                          + sizeof(OSTickStepState)
+#endif
+
+#if (OS_MEM_EN > 0u) && (OS_MAX_MEM_PART > 0u)
+                          + sizeof(OSMemFreeList)
+                          + sizeof(OSMemTbl)
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+                          + sizeof(OSSafetyCriticalStartFlag)
+#endif
+
+#if (OS_Q_EN > 0u) && (OS_MAX_QS > 0u)
+                          + sizeof(OSQFreeList)
+                          + sizeof(OSQTbl)
+#endif
+
+#if OS_TASK_REG_TBL_SIZE > 0u
+                          + sizeof(OSTaskRegNextAvailID)
+#endif
+
+#if OS_TIME_GET_SET_EN > 0u
+                          + sizeof(OSTime)
+#endif
+
+#if (OS_TMR_EN > 0u) && (OS_TMR_CFG_MAX > 0u)
+                          + sizeof(OSTmrFree)
+                          + sizeof(OSTmrUsed)
+                          + sizeof(OSTmrTime)
+                          + sizeof(OSTmrSem)
+                          + sizeof(OSTmrSemSignal)
+                          + sizeof(OSTmrTbl)
+                          + sizeof(OSTmrFreeList)
+                          + sizeof(OSTmrTaskStk)
+                          + sizeof(OSTmrWheelTbl)
+#endif
+                          + sizeof(OSIntNesting)
+                          + sizeof(OSLockNesting)
+                          + sizeof(OSPrioCur)
+                          + sizeof(OSPrioHighRdy)
+                          + sizeof(OSRdyGrp)
+                          + sizeof(OSRdyTbl)
+                          + sizeof(OSRunning)
+                          + sizeof(OSTaskCtr)
+                          + sizeof(OSIdleCtr)
+                          + sizeof(OSTaskIdleStk)
+                          + sizeof(OSTCBCur)
+                          + sizeof(OSTCBFreeList)
+                          + sizeof(OSTCBHighRdy)
+                          + sizeof(OSTCBList)
+                          + sizeof(OSTCBPrioTbl)
+                          + sizeof(OSTCBTbl);
+
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       OS DEBUG INITIALIZATION
+*
+* Description: This function is used to make sure that debug variables that are unused in the application
+*              are not optimized away.  This function might not be necessary for all compilers.  In this
+*              case, you should simply DELETE the code in this function while still leaving the declaration
+*              of the function itself.
+*
+* Arguments  : none
+*
+* Returns    : none
+*
+* Note(s)    : (1) This code doesn't do anything, it simply prevents the compiler from optimizing out
+*                  the 'const' variables which are declared in this file.
+*              (2) You may decide to 'compile out' the code (by using #if 0/#endif) INSIDE the function
+*                  if your compiler DOES NOT optimize out the 'const' variables above.
+*********************************************************************************************************
+*/
+
+#if OS_DEBUG_EN > 0u
+void  OSDebugInit (void)
+{
+    void  const  *ptemp;
+
+
+    ptemp = (void const *)&OSDebugEn;
+
+    ptemp = (void const *)&OSEndiannessTest;
+
+    ptemp = (void const *)&OSEventMax;
+    ptemp = (void const *)&OSEventNameEn;
+    ptemp = (void const *)&OSEventEn;
+    ptemp = (void const *)&OSEventSize;
+    ptemp = (void const *)&OSEventTblSize;
+    ptemp = (void const *)&OSEventMultiEn;
+
+    ptemp = (void const *)&OSFlagEn;
+    ptemp = (void const *)&OSFlagGrpSize;
+    ptemp = (void const *)&OSFlagNodeSize;
+    ptemp = (void const *)&OSFlagWidth;
+    ptemp = (void const *)&OSFlagMax;
+    ptemp = (void const *)&OSFlagNameEn;
+
+    ptemp = (void const *)&OSLowestPrio;
+
+    ptemp = (void const *)&OSMboxEn;
+
+    ptemp = (void const *)&OSMemEn;
+    ptemp = (void const *)&OSMemMax;
+    ptemp = (void const *)&OSMemNameEn;
+    ptemp = (void const *)&OSMemSize;
+    ptemp = (void const *)&OSMemTblSize;
+
+    ptemp = (void const *)&OSMutexEn;
+
+    ptemp = (void const *)&OSPtrSize;
+
+    ptemp = (void const *)&OSQEn;
+    ptemp = (void const *)&OSQMax;
+    ptemp = (void const *)&OSQSize;
+
+    ptemp = (void const *)&OSRdyTblSize;
+
+    ptemp = (void const *)&OSSemEn;
+
+    ptemp = (void const *)&OSStkWidth;
+
+    ptemp = (void const *)&OSTaskCreateEn;
+    ptemp = (void const *)&OSTaskCreateExtEn;
+    ptemp = (void const *)&OSTaskDelEn;
+    ptemp = (void const *)&OSTaskIdleStkSize;
+    ptemp = (void const *)&OSTaskProfileEn;
+    ptemp = (void const *)&OSTaskMax;
+    ptemp = (void const *)&OSTaskNameEn;
+    ptemp = (void const *)&OSTaskStatEn;
+    ptemp = (void const *)&OSTaskStatStkSize;
+    ptemp = (void const *)&OSTaskStatStkChkEn;
+    ptemp = (void const *)&OSTaskSwHookEn;
+
+    ptemp = (void const *)&OSTCBPrioTblMax;
+    ptemp = (void const *)&OSTCBSize;
+
+    ptemp = (void const *)&OSTicksPerSec;
+    ptemp = (void const *)&OSTimeTickHookEn;
+
+#if OS_TMR_EN > 0u
+    ptemp = (void const *)&OSTmrTbl[0];
+    ptemp = (void const *)&OSTmrWheelTbl[0];
+
+    ptemp = (void const *)&OSTmrEn;
+    ptemp = (void const *)&OSTmrCfgMax;
+    ptemp = (void const *)&OSTmrCfgNameEn;
+    ptemp = (void const *)&OSTmrCfgWheelSize;
+    ptemp = (void const *)&OSTmrCfgTicksPerSec;
+    ptemp = (void const *)&OSTmrSize;
+    ptemp = (void const *)&OSTmrTblSize;
+
+    ptemp = (void const *)&OSTmrWheelSize;
+    ptemp = (void const *)&OSTmrWheelTblSize;
+#endif
+
+    ptemp = (void const *)&OSVersionNbr;
+
+    ptemp = (void const *)&OSDataSize;
+
+    ptemp = ptemp;                             /* Prevent compiler warning for 'ptemp' not being used! */
+}
+#endif

Core/OS/Source/os_mbox.c

@@ -0,0 +1,708 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                      MESSAGE MAILBOX MANAGEMENT
+*
+* Filename : os_mbox.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MBOX_C
+#define  OS_MBOX_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if OS_MBOX_EN > 0u
+/*
+*********************************************************************************************************
+*                                        ACCEPT MESSAGE FROM MAILBOX
+*
+* Description: This function checks the mailbox to see if a message is available.  Unlike OSMboxPend(),
+*              OSMboxAccept() does not suspend the calling task if a message is not available.
+*
+* Arguments  : pevent        is a pointer to the event control block
+*
+* Returns    : != (void *)0  is the message in the mailbox if one is available.  The mailbox is cleared
+*                            so the next time OSMboxAccept() is called, the mailbox will be empty.
+*              == (void *)0  if the mailbox is empty or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass the proper event pointer.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_ACCEPT_EN > 0u
+void  *OSMboxAccept (OS_EVENT *pevent)
+{
+    void      *pmsg;
+#if OS_CRITICAL_METHOD == 3u                              /* Allocate storage for CPU status register  */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                        /* Validate 'pevent'                         */
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {      /* Validate event block type                 */
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pmsg               = pevent->OSEventPtr;
+    pevent->OSEventPtr = (void *)0;                       /* Clear the mailbox                         */
+    OS_EXIT_CRITICAL();
+    return (pmsg);                                        /* Return the message received (or NULL)     */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          CREATE A MESSAGE MAILBOX
+*
+* Description: This function creates a message mailbox if free event control blocks are available.
+*
+* Arguments  : pmsg          is a pointer to a message that you wish to deposit in the mailbox.  If
+*                            you set this value to the NULL pointer (i.e. (void *)0) then the mailbox
+*                            will be considered empty.
+*
+* Returns    : != (OS_EVENT *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                                created mailbox
+*              == (OS_EVENT *)0  if no event control blocks were available
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSMboxCreate (void *pmsg)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+    if (OSIntNesting > 0u) {                     /* See if called from ISR ...                         */
+        return ((OS_EVENT *)0);                  /* ... can't CREATE from an ISR                       */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                    /* Get next free event control block                  */
+    if (OSEventFreeList != (OS_EVENT *)0) {      /* See if pool of free ECB pool was empty             */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {
+        pevent->OSEventType    = OS_EVENT_TYPE_MBOX;
+        pevent->OSEventCnt     = 0u;
+        pevent->OSEventPtr     = pmsg;           /* Deposit message in event control block             */
+#if OS_EVENT_NAME_EN > 0u
+        pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+        OS_EventWaitListInit(pevent);
+
+        OS_TRACE_MBOX_CREATE(pevent, pevent->OSEventName);
+    }
+    return (pevent);                             /* Return pointer to event control block              */
+}
+
+
+/*
+*********************************************************************************************************
+*                                           DELETE A MAIBOX
+*
+* Description: This function deletes a mailbox and readies all tasks pending on the mailbox.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            mailbox.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete the mailbox ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the mailbox even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE                  The call was successful and the mailbox was deleted
+*                            OS_ERR_DEL_ISR               If you attempted to delete the mailbox from an ISR
+*                            OS_ERR_INVALID_OPT           An invalid option was specified
+*                            OS_ERR_ILLEGAL_DEL_RUN_TIME  If you tried to delete a mailbox after safety
+*                                                         critical operation started.
+*                            OS_ERR_TASK_WAITING          One or more tasks were waiting on the mailbox
+*                            OS_ERR_EVENT_TYPE            If you didn't pass a pointer to a mailbox
+*                            OS_ERR_PEVENT_NULL           If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the mailbox was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the mailbox MUST check the return code of OSMboxPend().
+*              2) OSMboxAccept() callers will not know that the intended mailbox has been deleted!
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the mailbox.
+*              4) Because ALL tasks pending on the mailbox will be readied, you MUST be careful in
+*                 applications where the mailbox is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the mailbox.
+*              5) All tasks that were waiting for the mailbox will be readied and returned an
+*                 OS_ERR_PEND_ABORT if OSMboxDel() was called with OS_DEL_ALWAYS
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_DEL_EN > 0u
+OS_EVENT  *OSMboxDel (OS_EVENT  *pevent,
+                      INT8U      opt,
+                      INT8U     *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_DEL_RUN_TIME;
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+
+    OS_TRACE_MBOX_DEL_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_MBOX_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        OS_TRACE_MBOX_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any tasks waiting on mailbox      */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete mailbox only if no task waiting   */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_EN > 0u
+                 pevent->OSEventName = (INT8U *)(void *)"?";
+#endif
+                 pevent->OSEventType = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr  = OSEventFreeList;    /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt  = 0u;
+                 OSEventFreeList     = pevent;             /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_NONE;
+                 pevent_return       = (OS_EVENT *)0;      /* Mailbox has been deleted                 */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr               = OS_ERR_TASK_WAITING;
+                 pevent_return       = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the mailbox                */
+             while (pevent->OSEventGrp != 0u) {            /* Ready ALL tasks waiting for mailbox      */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT);
+             }
+#if OS_EVENT_NAME_EN > 0u
+             pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0u;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr         = OS_ERR_NONE;
+             pevent_return = (OS_EVENT *)0;                /* Mailbox has been deleted                 */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr         = OS_ERR_INVALID_OPT;
+             pevent_return = pevent;
+             break;
+    }
+
+    OS_TRACE_MBOX_DEL_EXIT(*perr);
+
+    return (pevent_return);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                    PEND ON MAILBOX FOR A MESSAGE
+*
+* Description: This function waits for a message to be sent to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for a message to arrive at the mailbox up to the amount of time
+*                            specified by this argument.  If you specify 0, however, your task will wait
+*                            forever at the specified mailbox or, until a message arrives.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_TIMEOUT      A message was not received within the specified 'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the mailbox was aborted.
+*                            OS_ERR_EVENT_TYPE   Invalid event type
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_PEND_LOCKED  If you called this function when the scheduler is locked
+*
+* Returns    : != (void *)0  is a pointer to the message received
+*              == (void *)0  if no message was received or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass the proper pointer to the event control block.
+*********************************************************************************************************
+*/
+
+void  *OSMboxPend (OS_EVENT  *pevent,
+                   INT32U     timeout,
+                   INT8U     *perr)
+{
+    void      *pmsg;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((void *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+
+    OS_TRACE_MBOX_PEND_ENTER(pevent, timeout);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_MBOX_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    if (OSIntNesting > 0u) {                          /* See if called from ISR ...                    */
+        *perr = OS_ERR_PEND_ISR;                      /* ... can't PEND from an ISR                    */
+        OS_TRACE_MBOX_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    if (OSLockNesting > 0u) {                         /* See if called with scheduler locked ...       */
+        *perr = OS_ERR_PEND_LOCKED;                   /* ... can't PEND when locked                    */
+        OS_TRACE_MBOX_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pmsg = pevent->OSEventPtr;
+    if (pmsg != (void *)0) {                          /* See if there is already a message             */
+        pevent->OSEventPtr = (void *)0;               /* Clear the mailbox                             */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        OS_TRACE_MBOX_PEND_EXIT(*perr);
+        return (pmsg);                                /* Return the message received (or NULL)         */
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_MBOX;          /* Message not available, task will pend         */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Load timeout in TCB                           */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready to run  */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             pmsg =  OSTCBCur->OSTCBMsg;
+            *perr =  OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             pmsg = (void *)0;
+            *perr =  OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             pmsg = (void *)0;
+            *perr =  OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0u)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+    OSTCBCur->OSTCBEventMultiRdy = (OS_EVENT  *)0;
+#endif
+    OSTCBCur->OSTCBMsg           = (void      *)0;    /* Clear  received message                       */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_MBOX_PEND_EXIT(*perr);
+
+    return (pmsg);                                    /* Return received message                       */
+}
+
+
+/*
+*********************************************************************************************************
+*                                     ABORT WAITING ON A MESSAGE MAILBOX
+*
+* Description: This function aborts & readies any tasks currently waiting on a mailbox.  This function
+*              should be used to fault-abort the wait on the mailbox, rather than to normally signal
+*              the mailbox via OSMboxPost() or OSMboxPostOpt().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     mailbox
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     mailbox
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the mailbox.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the mailbox was readied
+*                                                and informed of the aborted wait; check return value
+*                                                for the number of tasks whose wait on the mailbox
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a mailbox.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the mailbox, or upon error.
+*              >  0          if one or more tasks waiting on the mailbox are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_PEND_ABORT_EN > 0u
+INT8U  OSMboxPendAbort (OS_EVENT  *pevent,
+                        INT8U      opt,
+                        INT8U     *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return (0u);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0u);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0u);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any task waiting on mailbox?      */
+        nbr_tasks = 0u;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:                    /* Do we need to abort ALL waiting tasks?   */
+                 while (pevent->OSEventGrp != 0u) {        /* Yes, ready ALL tasks waiting on mailbox  */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+
+            case OS_PEND_OPT_NONE:
+            default:                                       /* No,  ready HPT       waiting on mailbox  */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                        /* Find HPT ready to run                    */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0u);                                           /* No tasks waiting on mailbox              */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                      POST MESSAGE TO A MAILBOX
+*
+* Description: This function sends a message to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              pmsg          is a pointer to the message to send.  You MUST NOT send a NULL pointer.
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_MBOX_FULL     If the mailbox already contains a message.  You can can only send one
+*                                   message at a time and thus, the message MUST be consumed before you
+*                                   are allowed to send another one.
+*              OS_ERR_EVENT_TYPE    If you are attempting to post to a non mailbox.
+*              OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer
+*              OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer
+*
+* Note(s)    : 1) HPT means Highest Priority Task
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_POST_EN > 0u
+INT8U  OSMboxPost (OS_EVENT  *pevent,
+                   void      *pmsg)
+{
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pmsg == (void *)0) {                          /* Make sure we are not posting a NULL pointer   */
+        return (OS_ERR_POST_NULL_PTR);
+    }
+#endif
+
+    OS_TRACE_MBOX_POST_ENTER(pevent);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        OS_TRACE_MBOX_POST_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                   /* See if any task pending on mailbox            */
+                                                      /* Ready HPT waiting on event                    */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find highest priority task ready to run       */
+        OS_TRACE_MBOX_POST_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventPtr != (void *)0) {            /* Make sure mailbox doesn't already have a msg  */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_MBOX_POST_EXIT(OS_ERR_MBOX_FULL);
+        return (OS_ERR_MBOX_FULL);
+    }
+    pevent->OSEventPtr = pmsg;                        /* Place message in mailbox                      */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_MBOX_POST_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                      POST MESSAGE TO A MAILBOX
+*
+* Description: This function sends a message to a mailbox
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              pmsg          is a pointer to the message to send.  You MUST NOT send a NULL pointer.
+*
+*              opt           determines the type of POST performed:
+*                            OS_POST_OPT_NONE         POST to a single waiting task
+*                                                     (Identical to OSMboxPost())
+*                            OS_POST_OPT_BROADCAST    POST to ALL tasks that are waiting on the mailbox
+*
+*                            OS_POST_OPT_NO_SCHED     Indicates that the scheduler will NOT be invoked
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_MBOX_FULL     If the mailbox already contains a message.  You can can only send one
+*                                   message at a time and thus, the message MUST be consumed before you
+*                                   are allowed to send another one.
+*              OS_ERR_EVENT_TYPE    If you are attempting to post to a non mailbox.
+*              OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer
+*              OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer
+*
+* Note(s)    : 1) HPT means Highest Priority Task
+*
+* Warning    : Interrupts can be disabled for a long time if you do a 'broadcast'.  In fact, the
+*              interrupt disable time is proportional to the number of tasks waiting on the mailbox.
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_POST_OPT_EN > 0u
+INT8U  OSMboxPostOpt (OS_EVENT  *pevent,
+                      void      *pmsg,
+                      INT8U      opt)
+{
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pmsg == (void *)0) {                          /* Make sure we are not posting a NULL pointer   */
+        return (OS_ERR_POST_NULL_PTR);
+    }
+#endif
+
+    OS_TRACE_MBOX_POST_OPT_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {  /* Validate event block type                     */
+        OS_TRACE_MBOX_POST_OPT_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                   /* See if any task pending on mailbox            */
+        if ((opt & OS_POST_OPT_BROADCAST) != 0x00u) { /* Do we need to post msg to ALL waiting tasks ? */
+            while (pevent->OSEventGrp != 0u) {        /* Yes, Post to ALL tasks waiting on mailbox     */
+                (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+            }
+        } else {                                      /* No,  Post to HPT waiting on mbox              */
+            (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK);
+        }
+        OS_EXIT_CRITICAL();
+        if ((opt & OS_POST_OPT_NO_SCHED) == 0u) {     /* See if scheduler needs to be invoked          */
+            OS_Sched();                               /* Find HPT ready to run                         */
+        }
+        OS_TRACE_MBOX_POST_OPT_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventPtr != (void *)0) {            /* Make sure mailbox doesn't already have a msg  */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_MBOX_POST_OPT_EXIT(OS_ERR_MBOX_FULL);
+        return (OS_ERR_MBOX_FULL);
+    }
+    pevent->OSEventPtr = pmsg;                        /* Place message in mailbox                      */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_MBOX_POST_OPT_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       QUERY A MESSAGE MAILBOX
+*
+* Description: This function obtains information about a message mailbox.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mailbox
+*
+*              p_mbox_data   is a pointer to a structure that will contain information about the message
+*                            mailbox.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non mailbox.
+*              OS_ERR_PEVENT_NULL  If 'pevent'      is a NULL pointer
+*              OS_ERR_PDATA_NULL   If 'p_mbox_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_MBOX_QUERY_EN > 0u
+INT8U  OSMboxQuery (OS_EVENT      *pevent,
+                    OS_MBOX_DATA  *p_mbox_data)
+{
+    INT8U       i;
+    OS_PRIO    *psrc;
+    OS_PRIO    *pdest;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR   cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_mbox_data == (OS_MBOX_DATA *)0) {                /* Validate 'p_mbox_data'                   */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) {       /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_mbox_data->OSEventGrp = pevent->OSEventGrp;          /* Copy message mailbox wait list           */
+    psrc                    = &pevent->OSEventTbl[0];
+    pdest                   = &p_mbox_data->OSEventTbl[0];
+    for (i = 0u; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    p_mbox_data->OSMsg = pevent->OSEventPtr;               /* Get message from mailbox                 */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_MBOX_QUERY_EN                         */
+#endif                                                     /* OS_MBOX_EN                               */
+#endif                                                     /* OS_MBOX_C                                */

Core/OS/Source/os_mem.c

@@ -0,0 +1,489 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                           MEMORY MANAGEMENT
+*
+* Filename : os_mem.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MEM_C
+#define  OS_MEM_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if (OS_MEM_EN > 0u) && (OS_MAX_MEM_PART > 0u)
+/*
+*********************************************************************************************************
+*                                      CREATE A MEMORY PARTITION
+*
+* Description : Create a fixed-sized memory partition that will be managed by uC/OS-II.
+*
+* Arguments   : addr     is the starting address of the memory partition
+*
+*               nblks    is the number of memory blocks to create from the partition.
+*
+*               blksize  is the size (in bytes) of each block in the memory partition.
+*
+*               perr     is a pointer to a variable containing an error message which will be set by
+*                        this function to either:
+*
+*                        OS_ERR_NONE                     if the memory partition has been created correctly.
+*                        OS_ERR_ILLEGAL_CREATE_RUN_TIME  if you tried to create a memory partition after
+*                                                        safety critical operation started.
+*                        OS_ERR_MEM_INVALID_ADDR         if you are specifying an invalid address for the memory
+*                                                        storage of the partition or, the block does not align
+*                                                        on a pointer boundary
+*                        OS_ERR_MEM_INVALID_PART         no free partitions available
+*                        OS_ERR_MEM_INVALID_BLKS         user specified an invalid number of blocks (must be >= 2)
+*                        OS_ERR_MEM_INVALID_SIZE         user specified an invalid block size
+*                                                          - must be greater than the size of a pointer
+*                                                          - must be able to hold an integral number of pointers
+* Returns    : != (OS_MEM *)0  is the partition was created
+*              == (OS_MEM *)0  if the partition was not created because of invalid arguments or, no
+*                              free partition is available.
+*********************************************************************************************************
+*/
+
+OS_MEM  *OSMemCreate (void   *addr,
+                      INT32U  nblks,
+                      INT32U  blksize,
+                      INT8U  *perr)
+{
+    OS_MEM    *pmem;
+    INT8U     *pblk;
+    void     **plink;
+    INT32U     loops;
+    INT32U     i;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_MEM *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_CREATE_RUN_TIME;
+        return ((OS_MEM *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (addr == (void *)0) {                          /* Must pass a valid address for the memory part.*/
+        *perr = OS_ERR_MEM_INVALID_ADDR;
+        return ((OS_MEM *)0);
+    }
+    if (((INT32U)addr & (sizeof(void *) - 1u)) != 0u){  /* Must be pointer size aligned                */
+        *perr = OS_ERR_MEM_INVALID_ADDR;
+        return ((OS_MEM *)0);
+    }
+    if (nblks < 2u) {                                 /* Must have at least 2 blocks per partition     */
+        *perr = OS_ERR_MEM_INVALID_BLKS;
+        return ((OS_MEM *)0);
+    }
+    if (blksize < sizeof(void *)) {                   /* Must contain space for at least a pointer     */
+        *perr = OS_ERR_MEM_INVALID_SIZE;
+        return ((OS_MEM *)0);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    pmem = OSMemFreeList;                             /* Get next free memory partition                */
+    if (OSMemFreeList != (OS_MEM *)0) {               /* See if pool of free partitions was empty      */
+        OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList;
+    }
+    OS_EXIT_CRITICAL();
+    if (pmem == (OS_MEM *)0) {                        /* See if we have a memory partition             */
+        *perr = OS_ERR_MEM_INVALID_PART;
+        return ((OS_MEM *)0);
+    }
+    plink = (void **)addr;                            /* Create linked list of free memory blocks      */
+    pblk  = (INT8U *)addr;
+    loops  = nblks - 1u;
+    for (i = 0u; i < loops; i++) {
+        pblk +=  blksize;                             /* Point to the FOLLOWING block                  */
+       *plink = (void  *)pblk;                        /* Save pointer to NEXT block in CURRENT block   */
+        plink = (void **)pblk;                        /* Position to  NEXT      block                  */
+    }
+    *plink              = (void *)0;                  /* Last memory block points to NULL              */
+    pmem->OSMemAddr     = addr;                       /* Store start address of memory partition       */
+    pmem->OSMemFreeList = addr;                       /* Initialize pointer to pool of free blocks     */
+    pmem->OSMemNFree    = nblks;                      /* Store number of free blocks in MCB            */
+    pmem->OSMemNBlks    = nblks;
+    pmem->OSMemBlkSize  = blksize;                    /* Store block size of each memory blocks        */
+
+    OS_TRACE_MEM_CREATE(pmem);
+
+    *perr               = OS_ERR_NONE;
+    return (pmem);
+}
+
+
+/*
+*********************************************************************************************************
+*                                         GET A MEMORY BLOCK
+*
+* Description : Get a memory block from a partition
+*
+* Arguments   : pmem    is a pointer to the memory partition control block
+*
+*               perr    is a pointer to a variable containing an error message which will be set by this
+*                       function to either:
+*
+*                       OS_ERR_NONE             if the memory partition has been created correctly.
+*                       OS_ERR_MEM_NO_FREE_BLKS if there are no more free memory blocks to allocate to caller
+*                       OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem'
+*
+* Returns     : A pointer to a memory block if no error is detected
+*               A pointer to NULL if an error is detected
+*********************************************************************************************************
+*/
+
+void  *OSMemGet (OS_MEM  *pmem,
+                 INT8U   *perr)
+{
+    void      *pblk;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((void *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pmem == (OS_MEM *)0) {                        /* Must point to a valid memory partition        */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return ((void *)0);
+    }
+#endif
+
+    OS_TRACE_MEM_GET_ENTER(pmem);
+
+    OS_ENTER_CRITICAL();
+    if (pmem->OSMemNFree > 0u) {                      /* See if there are any free memory blocks       */
+        pblk                = pmem->OSMemFreeList;    /* Yes, point to next free memory block          */
+        pmem->OSMemFreeList = *(void **)pblk;         /*      Adjust pointer to new free list          */
+        pmem->OSMemNFree--;                           /*      One less memory block in this partition  */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;                          /*      No error                                 */
+        OS_TRACE_MEM_GET_EXIT(*perr);
+        return (pblk);                                /*      Return memory block to caller            */
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_MEM_NO_FREE_BLKS;                  /* No,  Notify caller of empty memory partition  */
+    OS_TRACE_MEM_GET_EXIT(*perr);
+    return ((void *)0);                               /*      Return NULL pointer to caller            */
+}
+
+
+/*
+*********************************************************************************************************
+*                                 GET THE NAME OF A MEMORY PARTITION
+*
+* Description: This function is used to obtain the name assigned to a memory partition.
+*
+* Arguments  : pmem      is a pointer to the memory partition
+*
+*              pname     is a pointer to a pointer to an ASCII string that will receive the name of the memory partition.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the name was copied to 'pname'
+*                        OS_ERR_MEM_INVALID_PMEM    if you passed a NULL pointer for 'pmem'
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_NAME_GET_ISR        You called this function from an ISR
+*
+* Returns    : The length of the string or 0 if 'pmem' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_EN > 0u
+INT8U  OSMemNameGet (OS_MEM   *pmem,
+                     INT8U   **pname,
+                     INT8U    *perr)
+{
+    INT8U      len;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return (0u);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pmem == (OS_MEM *)0) {                   /* Is 'pmem' a NULL pointer?                          */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return (0u);
+    }
+    if (pname == (INT8U **)0) {                  /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return (0u);
+    }
+#endif
+    if (OSIntNesting > 0u) {                     /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_GET_ISR;
+        return (0u);
+    }
+    OS_ENTER_CRITICAL();
+    *pname = pmem->OSMemName;
+    len    = OS_StrLen(*pname);
+    OS_EXIT_CRITICAL();
+    *perr  = OS_ERR_NONE;
+    return (len);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                 ASSIGN A NAME TO A MEMORY PARTITION
+*
+* Description: This function assigns a name to a memory partition.
+*
+* Arguments  : pmem      is a pointer to the memory partition
+*
+*              pname     is a pointer to an ASCII string that contains the name of the memory partition.
+*
+*              perr      is a pointer to an error code that can contain one of the following values:
+*
+*                        OS_ERR_NONE                if the name was copied to 'pname'
+*                        OS_ERR_MEM_INVALID_PMEM    if you passed a NULL pointer for 'pmem'
+*                        OS_ERR_PNAME_NULL          You passed a NULL pointer for 'pname'
+*                        OS_ERR_MEM_NAME_TOO_LONG   if the name doesn't fit in the storage area
+*                        OS_ERR_NAME_SET_ISR        if you called this function from an ISR
+*
+* Returns    : None
+*********************************************************************************************************
+*/
+
+#if OS_MEM_NAME_EN > 0u
+void  OSMemNameSet (OS_MEM  *pmem,
+                    INT8U   *pname,
+                    INT8U   *perr)
+{
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return;
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pmem == (OS_MEM *)0) {                   /* Is 'pmem' a NULL pointer?                          */
+        *perr = OS_ERR_MEM_INVALID_PMEM;
+        return;
+    }
+    if (pname == (INT8U *)0) {                   /* Is 'pname' a NULL pointer?                         */
+        *perr = OS_ERR_PNAME_NULL;
+        return;
+    }
+#endif
+    if (OSIntNesting > 0u) {                     /* See if trying to call from an ISR                  */
+        *perr = OS_ERR_NAME_SET_ISR;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    pmem->OSMemName = pname;
+    OS_EXIT_CRITICAL();
+    OS_TRACE_EVENT_NAME_SET(pmem, pname);
+    *perr           = OS_ERR_NONE;
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       RELEASE A MEMORY BLOCK
+*
+* Description : Returns a memory block to a partition
+*
+* Arguments   : pmem    is a pointer to the memory partition control block
+*
+*               pblk    is a pointer to the memory block being released.
+*
+* Returns     : OS_ERR_NONE              if the memory block was inserted into the partition
+*               OS_ERR_MEM_FULL          if you are returning a memory block to an already FULL memory
+*                                        partition (You freed more blocks than you allocated!)
+*               OS_ERR_MEM_INVALID_PMEM  if you passed a NULL pointer for 'pmem'
+*               OS_ERR_MEM_INVALID_PBLK  if you passed a NULL pointer for the block to release.
+*********************************************************************************************************
+*/
+
+INT8U  OSMemPut (OS_MEM  *pmem,
+                 void    *pblk)
+{
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pmem == (OS_MEM *)0) {                   /* Must point to a valid memory partition             */
+        return (OS_ERR_MEM_INVALID_PMEM);
+    }
+    if (pblk == (void *)0) {                     /* Must release a valid block                         */
+        return (OS_ERR_MEM_INVALID_PBLK);
+    }
+#endif
+
+    OS_TRACE_MEM_PUT_ENTER(pmem, pblk);
+
+    OS_ENTER_CRITICAL();
+    if (pmem->OSMemNFree >= pmem->OSMemNBlks) {  /* Make sure all blocks not already returned          */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_MEM_PUT_EXIT(OS_ERR_MEM_FULL);
+        return (OS_ERR_MEM_FULL);
+    }
+    *(void **)pblk      = pmem->OSMemFreeList;   /* Insert released block into free block list         */
+    pmem->OSMemFreeList = pblk;
+    pmem->OSMemNFree++;                          /* One more memory block in this partition            */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_MEM_PUT_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);                        /* Notify caller that memory block was released       */
+}
+
+
+/*
+*********************************************************************************************************
+*                                       QUERY MEMORY PARTITION
+*
+* Description : This function is used to determine the number of free memory blocks and the number of
+*               used memory blocks from a memory partition.
+*
+* Arguments   : pmem        is a pointer to the memory partition control block
+*
+*               p_mem_data  is a pointer to a structure that will contain information about the memory
+*                           partition.
+*
+* Returns     : OS_ERR_NONE               if no errors were found.
+*               OS_ERR_MEM_INVALID_PMEM   if you passed a NULL pointer for 'pmem'
+*               OS_ERR_MEM_INVALID_PDATA  if you passed a NULL pointer to the data recipient.
+*********************************************************************************************************
+*/
+
+#if OS_MEM_QUERY_EN > 0u
+INT8U  OSMemQuery (OS_MEM       *pmem,
+                   OS_MEM_DATA  *p_mem_data)
+{
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pmem == (OS_MEM *)0) {                   /* Must point to a valid memory partition             */
+        return (OS_ERR_MEM_INVALID_PMEM);
+    }
+    if (p_mem_data == (OS_MEM_DATA *)0) {        /* Must release a valid storage area for the data     */
+        return (OS_ERR_MEM_INVALID_PDATA);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    p_mem_data->OSAddr     = pmem->OSMemAddr;
+    p_mem_data->OSFreeList = pmem->OSMemFreeList;
+    p_mem_data->OSBlkSize  = pmem->OSMemBlkSize;
+    p_mem_data->OSNBlks    = pmem->OSMemNBlks;
+    p_mem_data->OSNFree    = pmem->OSMemNFree;
+    OS_EXIT_CRITICAL();
+    p_mem_data->OSNUsed    = p_mem_data->OSNBlks - p_mem_data->OSNFree;
+    return (OS_ERR_NONE);
+}
+#endif                                           /* OS_MEM_QUERY_EN                                    */
+
+
+/*
+*********************************************************************************************************
+*                                 INITIALIZE MEMORY PARTITION MANAGER
+*
+* Description : This function is called by uC/OS-II to initialize the memory partition manager.  Your
+*               application MUST NOT call this function.
+*
+* Arguments   : none
+*
+* Returns     : none
+*
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_MemInit (void)
+{
+#if OS_MAX_MEM_PART == 1u
+    OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl));   /* Clear the memory partition table          */
+    OSMemFreeList               = (OS_MEM *)&OSMemTbl[0]; /* Point to beginning of free list           */
+#if OS_MEM_NAME_EN > 0u
+    OSMemFreeList->OSMemName    = (INT8U *)"?";           /* Unknown name                              */
+#endif
+#endif
+
+#if OS_MAX_MEM_PART >= 2u
+    OS_MEM  *pmem;
+    INT16U   i;
+
+
+    OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl));   /* Clear the memory partition table          */
+    for (i = 0u; i < (OS_MAX_MEM_PART - 1u); i++) {       /* Init. list of free memory partitions      */
+        pmem                = &OSMemTbl[i];               /* Point to memory control block (MCB)       */
+        pmem->OSMemFreeList = (void *)&OSMemTbl[i + 1u];  /* Chain list of free partitions             */
+#if OS_MEM_NAME_EN > 0u
+        pmem->OSMemName  = (INT8U *)(void *)"?";
+#endif
+    }
+    pmem                = &OSMemTbl[i];
+    pmem->OSMemFreeList = (void *)0;                      /* Initialize last node                      */
+#if OS_MEM_NAME_EN > 0u
+    pmem->OSMemName = (INT8U *)(void *)"?";
+#endif
+
+    OSMemFreeList   = &OSMemTbl[0];                       /* Point to beginning of free list           */
+#endif
+}
+#endif                                                    /* OS_MEM_EN                                 */
+#endif                                                    /* OS_MEM_C                                  */

Core/OS/Source/os_mutex.c

@@ -0,0 +1,818 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                 MUTUAL EXCLUSION SEMAPHORE MANAGEMENT
+*
+* Filename : os_mutex.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_MUTEX_C
+#define  OS_MUTEX_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+
+#if OS_MUTEX_EN > 0u
+/*
+*********************************************************************************************************
+*                                           LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+#define  OS_MUTEX_KEEP_LOWER_8   ((INT16U)0x00FFu)
+#define  OS_MUTEX_KEEP_UPPER_8   ((INT16U)0xFF00u)
+
+#define  OS_MUTEX_AVAILABLE      ((INT16U)0x00FFu)
+
+/*
+*********************************************************************************************************
+*                                           LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+static  void  OSMutex_RdyAtPrio(OS_TCB *ptcb, INT8U prio);
+
+
+/*
+*********************************************************************************************************
+*                                  ACCEPT MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This  function checks the mutual exclusion semaphore to see if a resource is available.
+*              Unlike OSMutexPend(), OSMutexAccept() does not suspend the calling task if the resource is
+*              not available or the event did not occur.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+*              perr       is a pointer to an error code which will be returned to your application:
+*                            OS_ERR_NONE         if the call was successful.
+*                            OS_ERR_EVENT_TYPE   if 'pevent' is not a pointer to a mutex
+*                            OS_ERR_PEVENT_NULL  'pevent' is a NULL pointer
+*                            OS_ERR_PEND_ISR     if you called this function from an ISR
+*                            OS_ERR_PCP_LOWER    If the priority of the task that owns the Mutex is
+*                                                HIGHER (i.e. a lower number) than the PCP.  This error
+*                                                indicates that you did not set the PCP higher (lower
+*                                                number) than ALL the tasks that compete for the Mutex.
+*                                                Unfortunately, this is something that could not be
+*                                                detected when the Mutex is created because we don't know
+*                                                what tasks will be using the Mutex.
+*
+* Returns    : == OS_TRUE    if the resource is available, the mutual exclusion semaphore is acquired
+*              == OS_FALSE   a) if the resource is not available
+*                            b) you didn't pass a pointer to a mutual exclusion semaphore
+*                            c) you called this function from an ISR
+*
+* Warning(s) : This function CANNOT be called from an ISR because mutual exclusion semaphores are
+*              intended to be used by tasks only.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_ACCEPT_EN > 0u
+BOOLEAN  OSMutexAccept (OS_EVENT  *pevent,
+                        INT8U     *perr)
+{
+    INT8U      pcp;                                    /* Priority Ceiling Priority (PCP)              */
+#if OS_CRITICAL_METHOD == 3u                           /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return (OS_FALSE);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (OS_FALSE);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {  /* Validate event block type                    */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (OS_FALSE);
+    }
+    if (OSIntNesting > 0u) {                           /* Make sure it's not called from an ISR        */
+        *perr = OS_ERR_PEND_ISR;
+        return (OS_FALSE);
+    }
+    OS_ENTER_CRITICAL();                               /* Get value (0 or 1) of Mutex                  */
+    pcp = (INT8U)(pevent->OSEventCnt >> 8u);           /* Get PCP from mutex                           */
+    if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;   /*      Mask off LSByte (Acquire Mutex)         */
+        pevent->OSEventCnt |= (INT16U)OSTCBCur->OSTCBPrio;  /* Save current task priority in LSByte    */
+        pevent->OSEventPtr  = (void *)OSTCBCur;        /*      Link TCB of task owning Mutex           */
+        if ((pcp != OS_PRIO_MUTEX_CEIL_DIS) &&
+            (OSTCBCur->OSTCBPrio <= pcp)) {            /*      PCP 'must' have a SMALLER prio ...      */
+             OS_EXIT_CRITICAL();                       /*      ... than current task!                  */
+            *perr = OS_ERR_PCP_LOWER;
+        } else {
+             OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+        }
+        return (OS_TRUE);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (OS_FALSE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                 CREATE A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function creates a mutual exclusion semaphore.
+*
+* Arguments  : prio          is the priority to use when accessing the mutual exclusion semaphore.  In
+*                            other words, when the semaphore is acquired and a higher priority task
+*                            attempts to obtain the semaphore then the priority of the task owning the
+*                            semaphore is raised to this priority.  It is assumed that you will specify
+*                            a priority that is LOWER in value than ANY of the tasks competing for the
+*                            mutex. If the priority is specified as OS_PRIO_MUTEX_CEIL_DIS, then the
+*                            priority ceiling promotion is disabled. This way, the tasks accessing the
+*                            semaphore do not have their priority promoted.
+*
+*              perr          is a pointer to an error code which will be returned to your application:
+*                               OS_ERR_NONE                     if the call was successful.
+*                               OS_ERR_CREATE_ISR               if you attempted to create a MUTEX from an
+*                                                               ISR
+*                               OS_ERR_ILLEGAL_CREATE_RUN_TIME  if you tried to create a mutex after
+*                                                               safety critical operation started.
+*                               OS_ERR_PRIO_EXIST               if a task at the priority ceiling priority
+*                                                               already exist.
+*                               OS_ERR_PEVENT_NULL              No more event control blocks available.
+*                               OS_ERR_PRIO_INVALID             if the priority you specify is higher that
+*                                                               the maximum allowed (i.e. > OS_LOWEST_PRIO)
+*
+* Returns    : != (void *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                            created mutex.
+*              == (void *)0  if an error is detected.
+*
+* Note(s)    : 1) The LEAST significant 8 bits of '.OSEventCnt' hold the priority number of the task
+*                 owning the mutex or 0xFF if no task owns the mutex.
+*
+*              2) The MOST  significant 8 bits of '.OSEventCnt' hold the priority number used to
+*                 reduce priority inversion or 0xFF (OS_PRIO_MUTEX_CEIL_DIS) if priority ceiling
+*                 promotion is disabled.
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSMutexCreate (INT8U   prio,
+                          INT8U  *perr)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_CREATE_RUN_TIME;
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (prio != OS_PRIO_MUTEX_CEIL_DIS) {
+        if (prio >= OS_LOWEST_PRIO) {                      /* Validate PCP                             */
+           *perr = OS_ERR_PRIO_INVALID;
+            return ((OS_EVENT *)0);
+        }
+    }
+#endif
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_CREATE_ISR;                         /* ... can't CREATE mutex from an ISR       */
+        return ((OS_EVENT *)0);
+    }
+    OS_ENTER_CRITICAL();
+    if (prio != OS_PRIO_MUTEX_CEIL_DIS) {
+        if (OSTCBPrioTbl[prio] != (OS_TCB *)0) {           /* Mutex priority must not already exist    */
+            OS_EXIT_CRITICAL();                            /* Task already exist at priority ...       */
+           *perr = OS_ERR_PRIO_EXIST;                      /* ... ceiling priority                     */
+            return ((OS_EVENT *)0);
+        }
+        OSTCBPrioTbl[prio] = OS_TCB_RESERVED;              /* Reserve the table entry                  */
+    }
+
+    pevent = OSEventFreeList;                              /* Get next free event control block        */
+    if (pevent == (OS_EVENT *)0) {                         /* See if an ECB was available              */
+        if (prio != OS_PRIO_MUTEX_CEIL_DIS) {
+            OSTCBPrioTbl[prio] = (OS_TCB *)0;              /* No, Release the table entry              */
+        }
+        OS_EXIT_CRITICAL();
+       *perr = OS_ERR_PEVENT_NULL;                         /* No more event control blocks             */
+        return (pevent);
+    }
+    OSEventFreeList     = (OS_EVENT *)OSEventFreeList->OSEventPtr; /* Adjust the free list             */
+    OS_EXIT_CRITICAL();
+    pevent->OSEventType = OS_EVENT_TYPE_MUTEX;
+    pevent->OSEventCnt  = (INT16U)((INT16U)prio << 8u) | OS_MUTEX_AVAILABLE; /* Resource is avail.     */
+    pevent->OSEventPtr  = (void *)0;                       /* No task owning the mutex                 */
+#if OS_EVENT_NAME_EN > 0u
+    pevent->OSEventName = (INT8U *)(void *)"?";
+#endif
+    OS_EventWaitListInit(pevent);
+    OS_TRACE_MUTEX_CREATE(pevent, pevent->OSEventName);
+   *perr = OS_ERR_NONE;
+    return (pevent);
+}
+
+
+/*
+*********************************************************************************************************
+*                                           DELETE A MUTEX
+*
+* Description: This function deletes a mutual exclusion semaphore and readies all tasks pending on the it.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired mutex.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete mutex ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the mutex even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE                  The call was successful and the mutex was deleted
+*                            OS_ERR_DEL_ISR               If you attempted to delete the MUTEX from an ISR
+*                            OS_ERR_INVALID_OPT           An invalid option was specified
+*                            OS_ERR_ILLEGAL_DEL_RUN_TIME  If you tried to delete a mutex after safety
+*                                                         critical operation started.
+*                            OS_ERR_TASK_WAITING          One or more tasks were waiting on the mutex
+*                            OS_ERR_EVENT_TYPE            If you didn't pass a pointer to a mutex
+*                            OS_ERR_PEVENT_NULL           If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the mutex was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the mutex MUST check the return code of OSMutexPend().
+*
+*              2) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the mutex.
+*
+*              3) Because ALL tasks pending on the mutex will be readied, you MUST be careful because the
+*                 resource(s) will no longer be guarded by the mutex.
+*
+*              4) IMPORTANT: In the 'OS_DEL_ALWAYS' case, we assume that the owner of the Mutex (if there
+*                            is one) is ready-to-run and is thus NOT pending on another kernel object or
+*                            has delayed itself.  In other words, if a task owns the mutex being deleted,
+*                            that task will be made ready-to-run at its original priority.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_DEL_EN > 0u
+OS_EVENT  *OSMutexDel (OS_EVENT  *pevent,
+                       INT8U      opt,
+                       INT8U     *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+    INT8U      pcp;                                        /* Priority ceiling priority                */
+    INT8U      prio;
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_DEL_RUN_TIME;
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+
+    OS_TRACE_MUTEX_DEL_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_MUTEX_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        OS_TRACE_MUTEX_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any tasks waiting on mutex        */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* DELETE MUTEX ONLY IF NO TASK WAITING --- */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_EN > 0u
+                 pevent->OSEventName   = (INT8U *)(void *)"?";
+#endif
+                 pcp                   = (INT8U)(pevent->OSEventCnt >> 8u);
+                 if (pcp != OS_PRIO_MUTEX_CEIL_DIS) {
+                     OSTCBPrioTbl[pcp] = (OS_TCB *)0;      /* Free up the PCP                          */
+                 }
+                 pevent->OSEventType   = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr    = OSEventFreeList;  /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt    = 0u;
+                 OSEventFreeList       = pevent;
+                 OS_EXIT_CRITICAL();
+                 *perr                 = OS_ERR_NONE;
+                 pevent_return         = (OS_EVENT *)0;    /* Mutex has been deleted                   */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                 = OS_ERR_TASK_WAITING;
+                 pevent_return         = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* ALWAYS DELETE THE MUTEX ---------------- */
+             pcp  = (INT8U)(pevent->OSEventCnt >> 8u);                       /* Get PCP of mutex       */
+             if (pcp != OS_PRIO_MUTEX_CEIL_DIS) {
+                 prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's orig prio  */
+                 ptcb = (OS_TCB *)pevent->OSEventPtr;
+                 if (ptcb != (OS_TCB *)0) {                /* See if any task owns the mutex           */
+                     if (ptcb->OSTCBPrio == pcp) {         /* See if original prio was changed         */
+                         OS_TRACE_MUTEX_TASK_PRIO_DISINHERIT(OSTCBCur, prio);
+                         OSMutex_RdyAtPrio(ptcb, prio);    /* Yes, Restore the task's original prio    */
+                     }
+                 }
+             }
+             while (pevent->OSEventGrp != 0u) {            /* Ready ALL tasks waiting for mutex        */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_ABORT);
+             }
+#if OS_EVENT_NAME_EN > 0u
+             pevent->OSEventName   = (INT8U *)(void *)"?";
+#endif
+             pcp                   = (INT8U)(pevent->OSEventCnt >> 8u);
+             if (pcp != OS_PRIO_MUTEX_CEIL_DIS) {
+                 OSTCBPrioTbl[pcp] = (OS_TCB *)0;          /* Free up the PCP                          */
+             }
+             pevent->OSEventType   = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr    = OSEventFreeList;      /* Return Event Control Block to free list  */
+             pevent->OSEventCnt    = 0u;
+             OSEventFreeList       = pevent;               /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr         = OS_ERR_NONE;
+             pevent_return = (OS_EVENT *)0;                /* Mutex has been deleted                   */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr         = OS_ERR_INVALID_OPT;
+             pevent_return = pevent;
+             break;
+    }
+
+    OS_TRACE_MUTEX_DEL_EXIT(*perr);
+
+    return (pevent_return);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                 PEND ON MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function waits for a mutual exclusion semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            mutex.
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for the resource up to the amount of time specified by this argument.
+*                            If you specify 0, however, your task will wait forever at the specified
+*                            mutex or, until the resource becomes available.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*                               OS_ERR_NONE        The call was successful and your task owns the mutex
+*                               OS_ERR_TIMEOUT     The mutex was not available within the specified 'timeout'.
+*                               OS_ERR_PEND_ABORT  The wait on the mutex was aborted.
+*                               OS_ERR_EVENT_TYPE  If you didn't pass a pointer to a mutex
+*                               OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer
+*                               OS_ERR_PEND_ISR    If you called this function from an ISR and the result
+*                                                  would lead to a suspension.
+*                               OS_ERR_PCP_LOWER   If the priority of the task that owns the Mutex is
+*                                                  HIGHER (i.e. a lower number) than the PCP.  This error
+*                                                  indicates that you did not set the PCP higher (lower
+*                                                  number) than ALL the tasks that compete for the Mutex.
+*                                                  Unfortunately, this is something that could not be
+*                                                  detected when the Mutex is created because we don't know
+*                                                  what tasks will be using the Mutex.
+*                               OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked
+*
+* Returns    : none
+*
+* Note(s)    : 1) The task that owns the Mutex MUST NOT pend on any other event while it owns the mutex.
+*
+*              2) You MUST NOT change the priority of the task that owns the mutex
+*********************************************************************************************************
+*/
+
+void  OSMutexPend (OS_EVENT  *pevent,
+                   INT32U     timeout,
+                   INT8U     *perr)
+{
+    INT8U      pcp;                                        /* Priority Ceiling Priority (PCP)          */
+    INT8U      mprio;                                      /* Mutex owner priority                     */
+    BOOLEAN    rdy;                                        /* Flag indicating task was ready           */
+    OS_TCB    *ptcb;
+    OS_EVENT  *pevent2;
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return;
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+
+    OS_TRACE_MUTEX_PEND_ENTER(pevent, timeout);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_MUTEX_PEND_EXIT(*perr);
+        return;
+    }
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_PEND_ISR;                           /* ... can't PEND from an ISR               */
+        OS_TRACE_MUTEX_PEND_EXIT(*perr);
+        return;
+    }
+    if (OSLockNesting > 0u) {                              /* See if called with scheduler locked ...  */
+        *perr = OS_ERR_PEND_LOCKED;                        /* ... can't PEND when locked               */
+        OS_TRACE_MUTEX_PEND_EXIT(*perr);
+        return;
+    }
+
+    OS_ENTER_CRITICAL();
+    pcp = (INT8U)(pevent->OSEventCnt >> 8u);               /* Get PCP from mutex                       */
+                                                           /* Is Mutex available?                      */
+    if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) {
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;       /* Yes, Acquire the resource                */
+        pevent->OSEventCnt |= (INT16U)OSTCBCur->OSTCBPrio; /*      Save priority of owning task        */
+        pevent->OSEventPtr  = (void *)OSTCBCur;            /*      Point to owning task's OS_TCB       */
+        if ((pcp != OS_PRIO_MUTEX_CEIL_DIS) &&
+            (OSTCBCur->OSTCBPrio <= pcp)) {                /*      PCP 'must' have a SMALLER prio ...  */
+             OS_EXIT_CRITICAL();                           /*      ... than current task!              */
+            *perr = OS_ERR_PCP_LOWER;
+        } else {
+             OS_EXIT_CRITICAL();
+            *perr = OS_ERR_NONE;
+        }
+        OS_TRACE_MUTEX_PEND_EXIT(*perr);
+        return;
+    }
+    if (pcp != OS_PRIO_MUTEX_CEIL_DIS) {
+        mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /*  Get priority of mutex owner   */
+        ptcb  = (OS_TCB *)(pevent->OSEventPtr);                   /*     Point to TCB of mutex owner   */
+        if (ptcb->OSTCBPrio > pcp) {                              /*     Need to promote prio of owner?*/
+            if (mprio > OSTCBCur->OSTCBPrio) {
+                y = ptcb->OSTCBY;
+                if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0u) {      /*     See if mutex owner is ready   */
+                    OSRdyTbl[y] &= (OS_PRIO)~ptcb->OSTCBBitX;     /*     Yes, Remove owner from Rdy ...*/
+                    if (OSRdyTbl[y] == 0u) {                      /*          ... list at current prio */
+                        OSRdyGrp &= (OS_PRIO)~ptcb->OSTCBBitY;
+                    }
+                    rdy = OS_TRUE;
+                } else {
+                    pevent2 = ptcb->OSTCBEventPtr;
+                    if (pevent2 != (OS_EVENT *)0) {               /* Remove from event wait list       */
+                        y = ptcb->OSTCBY;
+                        pevent2->OSEventTbl[y] &= (OS_PRIO)~ptcb->OSTCBBitX;
+                        if (pevent2->OSEventTbl[y] == 0u) {
+                            pevent2->OSEventGrp &= (OS_PRIO)~ptcb->OSTCBBitY;
+                        }
+                    }
+                    rdy = OS_FALSE;                        /* No                                       */
+                }
+                ptcb->OSTCBPrio = pcp;                     /* Change owner task prio to PCP            */
+
+                OS_TRACE_MUTEX_TASK_PRIO_INHERIT(ptcb, pcp);
+
+#if OS_LOWEST_PRIO <= 63u
+                ptcb->OSTCBY    = (INT8U)( ptcb->OSTCBPrio >> 3u);
+                ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x07u);
+#else
+                ptcb->OSTCBY    = (INT8U)((INT8U)(ptcb->OSTCBPrio >> 4u) & 0xFFu);
+                ptcb->OSTCBX    = (INT8U)( ptcb->OSTCBPrio & 0x0Fu);
+#endif
+                ptcb->OSTCBBitY = (OS_PRIO)(1uL << ptcb->OSTCBY);
+                ptcb->OSTCBBitX = (OS_PRIO)(1uL << ptcb->OSTCBX);
+
+                if (rdy == OS_TRUE) {                      /* If task was ready at owner's priority ...*/
+                    OSRdyGrp               |= ptcb->OSTCBBitY; /* ... make it ready at new priority.   */
+                    OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+                } else {
+                    pevent2 = ptcb->OSTCBEventPtr;
+                    if (pevent2 != (OS_EVENT *)0) {        /* Add to event wait list                   */
+                        pevent2->OSEventGrp               |= ptcb->OSTCBBitY;
+                        pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+                    }
+                }
+                OSTCBPrioTbl[pcp] = ptcb;
+            }
+        }
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_MUTEX;         /* Mutex not available, pend current task        */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Store timeout in current task's TCB           */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted getting mutex        */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get mutex within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0u)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+    OSTCBCur->OSTCBEventMultiRdy = (OS_EVENT  *)0;
+#endif
+    OS_EXIT_CRITICAL();
+
+    OS_TRACE_MUTEX_PEND_EXIT(*perr);
+}
+
+
+/*
+*********************************************************************************************************
+*                                POST TO A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function signals a mutual exclusion semaphore
+*
+* Arguments  : pevent              is a pointer to the event control block associated with the desired
+*                                  mutex.
+*
+* Returns    : OS_ERR_NONE             The call was successful and the mutex was signaled.
+*              OS_ERR_EVENT_TYPE       If you didn't pass a pointer to a mutex
+*              OS_ERR_PEVENT_NULL      'pevent' is a NULL pointer
+*              OS_ERR_POST_ISR         Attempted to post from an ISR (not valid for MUTEXes)
+*              OS_ERR_NOT_MUTEX_OWNER  The task that did the post is NOT the owner of the MUTEX.
+*              OS_ERR_PCP_LOWER        If the priority of the new task that owns the Mutex is
+*                                      HIGHER (i.e. a lower number) than the PCP.  This error
+*                                      indicates that you did not set the PCP higher (lower
+*                                      number) than ALL the tasks that compete for the Mutex.
+*                                      Unfortunately, this is something that could not be
+*                                      detected when the Mutex is created because we don't know
+*                                      what tasks will be using the Mutex.
+*********************************************************************************************************
+*/
+
+INT8U  OSMutexPost (OS_EVENT *pevent)
+{
+    INT8U      pcp;                                   /* Priority ceiling priority                     */
+    INT8U      prio;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+    if (OSIntNesting > 0u) {                          /* See if called from ISR ...                    */
+        return (OS_ERR_POST_ISR);                     /* ... can't POST mutex from an ISR              */
+    }
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+
+    OS_TRACE_MUTEX_POST_ENTER(pevent);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type                     */
+        OS_TRACE_MUTEX_POST_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    pcp  = (INT8U)(pevent->OSEventCnt >> 8u);         /* Get priority ceiling priority of mutex        */
+    prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);  /* Get owner's original priority      */
+    if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) {   /* See if posting task owns the MUTEX            */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_MUTEX_POST_EXIT(OS_ERR_NOT_MUTEX_OWNER);
+        return (OS_ERR_NOT_MUTEX_OWNER);
+    }
+    if (pcp != OS_PRIO_MUTEX_CEIL_DIS) {
+        if (OSTCBCur->OSTCBPrio == pcp) {             /* Did we have to raise current task's priority? */
+            OS_TRACE_MUTEX_TASK_PRIO_DISINHERIT(OSTCBCur, prio);
+            OSMutex_RdyAtPrio(OSTCBCur, prio);        /* Restore the task's original priority          */
+        }
+        OSTCBPrioTbl[pcp] = OS_TCB_RESERVED;          /* Reserve table entry                           */
+    }
+    if (pevent->OSEventGrp != 0u) {                   /* Any task waiting for the mutex?               */
+                                                      /* Yes, Make HPT waiting for mutex ready         */
+        prio                = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK);
+        pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8;  /*      Save priority of mutex's new owner       */
+        pevent->OSEventCnt |= (INT16U)prio;
+        pevent->OSEventPtr  = OSTCBPrioTbl[prio];     /*      Link to new mutex owner's OS_TCB         */
+        if ((pcp  != OS_PRIO_MUTEX_CEIL_DIS) &&
+            (prio <= pcp)) {                          /*      PCP 'must' have a SMALLER prio ...       */
+            OS_EXIT_CRITICAL();                       /*      ... than current task!                   */
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+            OS_TRACE_MUTEX_POST_EXIT(OS_ERR_PCP_LOWER);
+            return (OS_ERR_PCP_LOWER);
+        } else {
+            OS_EXIT_CRITICAL();
+            OS_Sched();                               /*      Find highest priority task ready to run  */
+            OS_TRACE_MUTEX_POST_EXIT(OS_ERR_NONE);
+            return (OS_ERR_NONE);
+        }
+    }
+    pevent->OSEventCnt |= OS_MUTEX_AVAILABLE;         /* No,  Mutex is now available                   */
+    pevent->OSEventPtr  = (void *)0;
+    OS_EXIT_CRITICAL();
+    OS_TRACE_MUTEX_POST_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);
+}
+
+
+/*
+*********************************************************************************************************
+*                                 QUERY A MUTUAL EXCLUSION SEMAPHORE
+*
+* Description: This function obtains information about a mutex
+*
+* Arguments  : pevent          is a pointer to the event control block associated with the desired mutex
+*
+*              p_mutex_data    is a pointer to a structure that will contain information about the mutex
+*
+* Returns    : OS_ERR_NONE          The call was successful and the message was sent
+*              OS_ERR_QUERY_ISR     If you called this function from an ISR
+*              OS_ERR_PEVENT_NULL   If 'pevent'       is a NULL pointer
+*              OS_ERR_PDATA_NULL    If 'p_mutex_data' is a NULL pointer
+*              OS_ERR_EVENT_TYPE    If you are attempting to obtain data from a non mutex.
+*********************************************************************************************************
+*/
+
+#if OS_MUTEX_QUERY_EN > 0u
+INT8U  OSMutexQuery (OS_EVENT       *pevent,
+                     OS_MUTEX_DATA  *p_mutex_data)
+{
+    INT8U       i;
+    OS_PRIO    *psrc;
+    OS_PRIO    *pdest;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR   cpu_sr = 0u;
+#endif
+
+
+
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        return (OS_ERR_QUERY_ISR);                         /* ... can't QUERY mutex from an ISR        */
+    }
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_mutex_data == (OS_MUTEX_DATA *)0) {              /* Validate 'p_mutex_data'                  */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) {      /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_mutex_data->OSMutexPCP  = (INT8U)(pevent->OSEventCnt >> 8u);
+    p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8);
+    if (p_mutex_data->OSOwnerPrio == 0xFFu) {
+        p_mutex_data->OSValue = OS_TRUE;
+    } else {
+        p_mutex_data->OSValue = OS_FALSE;
+    }
+    p_mutex_data->OSEventGrp  = pevent->OSEventGrp;        /* Copy wait list                           */
+    psrc                      = &pevent->OSEventTbl[0];
+    pdest                     = &p_mutex_data->OSEventTbl[0];
+    for (i = 0u; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_MUTEX_QUERY_EN                        */
+
+
+/*
+*********************************************************************************************************
+*                            RESTORE A TASK BACK TO ITS ORIGINAL PRIORITY
+*
+* Description: This function makes a task ready at the specified priority
+*
+* Arguments  : ptcb            is a pointer to OS_TCB of the task to make ready
+*
+*              prio            is the desired priority
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+static  void  OSMutex_RdyAtPrio (OS_TCB  *ptcb,
+                                 INT8U    prio)
+{
+    INT8U  y;
+
+
+    y            =  ptcb->OSTCBY;                          /* Remove owner from ready list at 'pcp'    */
+    OSRdyTbl[y] &= (OS_PRIO)~ptcb->OSTCBBitX;
+    OS_TRACE_TASK_SUSPENDED(ptcb);
+    if (OSRdyTbl[y] == 0u) {
+        OSRdyGrp &= (OS_PRIO)~ptcb->OSTCBBitY;
+    }
+    ptcb->OSTCBPrio         = prio;
+    OSPrioCur               = prio;                        /* The current task is now at this priority */
+#if OS_LOWEST_PRIO <= 63u
+    ptcb->OSTCBY            = (INT8U)((INT8U)(prio >> 3u) & 0x07u);
+    ptcb->OSTCBX            = (INT8U)(prio & 0x07u);
+#else
+    ptcb->OSTCBY            = (INT8U)((INT8U)(prio >> 4u) & 0x0Fu);
+    ptcb->OSTCBX            = (INT8U) (prio & 0x0Fu);
+#endif
+    ptcb->OSTCBBitY         = (OS_PRIO)(1uL << ptcb->OSTCBY);
+    ptcb->OSTCBBitX         = (OS_PRIO)(1uL << ptcb->OSTCBX);
+    OSRdyGrp               |= ptcb->OSTCBBitY;             /* Make task ready at original priority     */
+    OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+    OSTCBPrioTbl[prio]      = ptcb;
+    OS_TRACE_TASK_READY(ptcb);
+}
+
+
+#endif                                                     /* OS_MUTEX_EN                              */
+#endif                                                     /* OS_MUTEX_C                               */

Core/OS/Source/os_q.c

@@ -0,0 +1,964 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                       MESSAGE QUEUE MANAGEMENT
+*
+* Filename : os_q.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_Q_C
+#define  OS_Q_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if (OS_Q_EN > 0u) && (OS_MAX_QS > 0u)
+/*
+*********************************************************************************************************
+*                                      ACCEPT MESSAGE FROM QUEUE
+*
+* Description: This function checks the queue to see if a message is available.  Unlike OSQPend(),
+*              OSQAccept() does not suspend the calling task if a message is not available.
+*
+* Arguments  : pevent        is a pointer to the event control block
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_EVENT_TYPE   You didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_Q_EMPTY      The queue did not contain any messages
+*
+* Returns    : != (void *)0  is the message in the queue if one is available.  The message is removed
+*                            from the so the next time OSQAccept() is called, the queue will contain
+*                            one less entry.
+*              == (void *)0  if you received a NULL pointer message
+*                            if the queue is empty or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you passed an invalid event type
+*
+* Note(s)    : As of V2.60, you can now pass NULL pointers through queues.  Because of this, the argument
+*              'perr' has been added to the API to tell you about the outcome of the call.
+*********************************************************************************************************
+*/
+
+#if OS_Q_ACCEPT_EN > 0u
+void  *OSQAccept (OS_EVENT  *pevent,
+                  INT8U     *perr)
+{
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((void *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+        *perr = OS_ERR_EVENT_TYPE;
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+    if (pq->OSQEntries > 0u) {                   /* See if any messages in the queue                   */
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+            pq->OSQOut = pq->OSQStart;
+        }
+        *perr = OS_ERR_NONE;
+    } else {
+        *perr = OS_ERR_Q_EMPTY;
+        pmsg  = (void *)0;                       /* Queue is empty                                     */
+    }
+    OS_EXIT_CRITICAL();
+    return (pmsg);                               /* Return message received (or NULL)                  */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       CREATE A MESSAGE QUEUE
+*
+* Description: This function creates a message queue if free event control blocks are available.
+*
+* Arguments  : start         is a pointer to the base address of the message queue storage area.  The
+*                            storage area MUST be declared as an array of pointers to 'void' as follows
+*
+*                            void *MessageStorage[size]
+*
+*              size          is the number of elements in the storage area
+*
+* Returns    : != (OS_EVENT *)0  is a pointer to the event control clock (OS_EVENT) associated with the
+*                                created queue
+*              == (OS_EVENT *)0  if no event control blocks were available or an error was detected
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSQCreate (void    **start,
+                      INT16U    size)
+{
+    OS_EVENT  *pevent;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+    if (OSIntNesting > 0u) {                     /* See if called from ISR ...                         */
+        return ((OS_EVENT *)0);                  /* ... can't CREATE from an ISR                       */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                    /* Get next free event control block                  */
+    if (OSEventFreeList != (OS_EVENT *)0) {      /* See if pool of free ECB pool was empty             */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {               /* See if we have an event control block              */
+        OS_ENTER_CRITICAL();
+        pq = OSQFreeList;                        /* Get a free queue control block                     */
+        if (pq != (OS_Q *)0) {                   /* Were we able to get a queue control block ?        */
+            OSQFreeList            = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/
+            OS_EXIT_CRITICAL();
+            pq->OSQStart           = start;               /*      Initialize the queue                 */
+            pq->OSQEnd             = &start[size];
+            pq->OSQIn              = start;
+            pq->OSQOut             = start;
+            pq->OSQSize            = size;
+            pq->OSQEntries         = 0u;
+            pevent->OSEventType    = OS_EVENT_TYPE_Q;
+            pevent->OSEventCnt     = 0u;
+            pevent->OSEventPtr     = pq;
+#if OS_EVENT_NAME_EN > 0u
+            pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+            OS_EventWaitListInit(pevent);                 /*      Initialize the wait list             */
+
+            OS_TRACE_Q_CREATE(pevent, pevent->OSEventName);
+        } else {
+            pevent->OSEventPtr = (void *)OSEventFreeList; /* No,  Return event control block on error  */
+            OSEventFreeList    = pevent;
+            OS_EXIT_CRITICAL();
+            pevent = (OS_EVENT *)0;
+        }
+    }
+    return (pevent);
+}
+
+
+/*
+*********************************************************************************************************
+*                                       DELETE A MESSAGE QUEUE
+*
+* Description: This function deletes a message queue and readies all tasks pending on the queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            queue.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete the queue ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the queue even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE                  The call was successful and the queue was deleted
+*                            OS_ERR_DEL_ISR               If you tried to delete the queue from an ISR
+*                            OS_ERR_ILLEGAL_DEL_RUN_TIME  If you tried to delete the queue after safety
+*                                                         critical operation started.
+*                            OS_ERR_INVALID_OPT           An invalid option was specified
+*                            OS_ERR_TASK_WAITING          One or more tasks were waiting on the queue
+*                            OS_ERR_EVENT_TYPE            If you didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL           If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the queue was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the queue MUST check the return code of OSQPend().
+*              2) OSQAccept() callers will not know that the intended queue has been deleted unless
+*                 they check 'pevent' to see that it's a NULL pointer.
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the queue.
+*              4) Because ALL tasks pending on the queue will be readied, you MUST be careful in
+*                 applications where the queue is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the queue.
+*              5) If the storage for the message queue was allocated dynamically (i.e. using a malloc()
+*                 type call) then your application MUST release the memory storage by call the counterpart
+*                 call of the dynamic allocation scheme used.  If the queue storage was created statically
+*                 then, the storage can be reused.
+*              6) All tasks that were waiting for the queue will be readied and returned an
+*                 OS_ERR_PEND_ABORT if OSQDel() was called with OS_DEL_ALWAYS
+*********************************************************************************************************
+*/
+
+#if OS_Q_DEL_EN > 0u
+OS_EVENT  *OSQDel (OS_EVENT  *pevent,
+                   INT8U      opt,
+                   INT8U     *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_DEL_RUN_TIME;
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+
+    OS_TRACE_Q_DEL_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_Q_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        OS_TRACE_Q_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any tasks waiting on queue        */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete queue only if no task waiting     */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_EN > 0u
+                 pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+                 pq                     = (OS_Q *)pevent->OSEventPtr;  /* Return OS_Q to free list     */
+                 pq->OSQPtr             = OSQFreeList;
+                 OSQFreeList            = pq;
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt     = 0u;
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+                 pevent_return          = (OS_EVENT *)0;   /* Queue has been deleted                   */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the queue                  */
+             while (pevent->OSEventGrp != 0u) {            /* Ready ALL tasks waiting for queue        */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+             }
+#if OS_EVENT_NAME_EN > 0u
+             pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+             pq                     = (OS_Q *)pevent->OSEventPtr;   /* Return OS_Q to free list        */
+             pq->OSQPtr             = OSQFreeList;
+             OSQFreeList            = pq;
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0u;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr                  = OS_ERR_NONE;
+             pevent_return          = (OS_EVENT *)0;       /* Queue has been deleted                   */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+             pevent_return          = pevent;
+             break;
+    }
+
+    OS_TRACE_Q_DEL_EXIT(*perr);
+
+    return (pevent_return);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                             FLUSH QUEUE
+*
+* Description : This function is used to flush the contents of the message queue.
+*
+* Arguments   : none
+*
+* Returns     : OS_ERR_NONE         upon success
+*               OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a queue
+*               OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*
+* WARNING     : You should use this function with great care because, when to flush the queue, you LOOSE
+*               the references to what the queue entries are pointing to and thus, you could cause
+*               'memory leaks'.  In other words, the data you are pointing to that's being referenced
+*               by the queue entries should, most likely, need to be de-allocated (i.e. freed).
+*********************************************************************************************************
+*/
+
+#if OS_Q_FLUSH_EN > 0u
+INT8U  OSQFlush (OS_EVENT *pevent)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        return (OS_ERR_EVENT_TYPE);
+    }
+#endif
+    OS_ENTER_CRITICAL();
+    pq             = (OS_Q *)pevent->OSEventPtr;      /* Point to queue storage structure              */
+    pq->OSQIn      = pq->OSQStart;
+    pq->OSQOut     = pq->OSQStart;
+    pq->OSQEntries = 0u;
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                    PEND ON A QUEUE FOR A MESSAGE
+*
+* Description: This function waits for a message to be sent to a queue
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for a message to arrive at the queue up to the amount of time
+*                            specified by this argument.  If you specify 0, however, your task will wait
+*                            forever at the specified queue or, until a message arrives.
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task received a
+*                                                message.
+*                            OS_ERR_TIMEOUT      A message was not received within the specified 'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the queue was aborted.
+*                            OS_ERR_EVENT_TYPE   You didn't pass a pointer to a queue
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEND_LOCKED  If you called this function with the scheduler is locked
+*
+* Returns    : != (void *)0  is a pointer to the message received
+*              == (void *)0  if you received a NULL pointer message or,
+*                            if no message was received or,
+*                            if 'pevent' is a NULL pointer or,
+*                            if you didn't pass a pointer to a queue.
+*
+* Note(s)    : As of V2.60, this function allows you to receive NULL pointer messages.
+*********************************************************************************************************
+*/
+
+void  *OSQPend (OS_EVENT  *pevent,
+                INT32U     timeout,
+                INT8U     *perr)
+{
+    void      *pmsg;
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((void *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {               /* Validate 'pevent'                                  */
+        *perr = OS_ERR_PEVENT_NULL;
+        return ((void *)0);
+    }
+#endif
+
+    OS_TRACE_Q_PEND_ENTER(pevent, timeout);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type                          */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_Q_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    if (OSIntNesting > 0u) {                     /* See if called from ISR ...                         */
+        *perr = OS_ERR_PEND_ISR;                 /* ... can't PEND from an ISR                         */
+        OS_TRACE_Q_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    if (OSLockNesting > 0u) {                    /* See if called with scheduler locked ...            */
+        *perr = OS_ERR_PEND_LOCKED;              /* ... can't PEND when locked                         */
+        OS_TRACE_Q_PEND_EXIT(*perr);
+        return ((void *)0);
+    }
+    OS_ENTER_CRITICAL();
+    pq = (OS_Q *)pevent->OSEventPtr;             /* Point at queue control block                       */
+    if (pq->OSQEntries > 0u) {                   /* See if any messages in the queue                   */
+        pmsg = *pq->OSQOut++;                    /* Yes, extract oldest message from the queue         */
+        pq->OSQEntries--;                        /* Update the number of entries in the queue          */
+        if (pq->OSQOut == pq->OSQEnd) {          /* Wrap OUT pointer if we are at the end of the queue */
+            pq->OSQOut = pq->OSQStart;
+        }
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        OS_TRACE_Q_PEND_EXIT(*perr);
+        return (pmsg);                           /* Return message received                            */
+    }
+    OSTCBCur->OSTCBStat     |= OS_STAT_Q;        /* Task will have to pend for a message to be posted  */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;          /* Load timeout into TCB                              */
+    OS_EventTaskWait(pevent);                    /* Suspend task until event or timeout occurs         */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                  /* Find next highest priority task ready to run       */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:                         /* Extract message from TCB (Put there by QPost) */
+             pmsg =  OSTCBCur->OSTCBMsg;
+            *perr =  OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             pmsg = (void *)0;
+            *perr =  OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             pmsg = (void *)0;
+            *perr =  OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0u)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+    OSTCBCur->OSTCBEventMultiRdy = (OS_EVENT  *)0;
+#endif
+    OSTCBCur->OSTCBMsg           = (void      *)0;    /* Clear  received message                       */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_Q_PEND_EXIT(*perr);
+
+    return (pmsg);                                    /* Return received message                       */
+}
+
+
+/*
+*********************************************************************************************************
+*                                  ABORT WAITING ON A MESSAGE QUEUE
+*
+* Description: This function aborts & readies any tasks currently waiting on a queue.  This function
+*              should be used to fault-abort the wait on the queue, rather than to normally signal
+*              the queue via OSQPost(), OSQPostFront() or OSQPostOpt().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     queue
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     queue
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the queue.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the queue was readied
+*                                                and informed of the aborted wait; check return value
+*                                                for the number of tasks whose wait on the queue
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a queue.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the queue, or upon error.
+*              >  0          if one or more tasks waiting on the queue are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_Q_PEND_ABORT_EN > 0u
+INT8U  OSQPendAbort (OS_EVENT  *pevent,
+                     INT8U      opt,
+                     INT8U     *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return (0u);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0u);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {          /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0u);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any task waiting on queue?        */
+        nbr_tasks = 0u;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:                    /* Do we need to abort ALL waiting tasks?   */
+                 while (pevent->OSEventGrp != 0u) {        /* Yes, ready ALL tasks waiting on queue    */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+
+            case OS_PEND_OPT_NONE:
+            default:                                       /* No,  ready HPT       waiting on queue    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                        /* Find HPT ready to run                    */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0u);                                           /* No tasks waiting on queue                */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       POST MESSAGE TO A QUEUE
+*
+* Description: This function sends a message to a queue
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Note(s)    : As of V2.60, this function allows you to send NULL pointer messages.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_EN > 0u
+INT8U  OSQPost (OS_EVENT  *pevent,
+                void      *pmsg)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                           /* Allocate storage for CPU status register     */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+
+    OS_TRACE_Q_POST_ENTER(pevent);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+        OS_TRACE_Q_POST_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                    /* See if any task pending on queue             */
+                                                       /* Ready highest priority task waiting on event */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                    /* Find highest priority task ready to run      */
+        OS_TRACE_Q_POST_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                   /* Point to queue control block                 */
+    if (pq->OSQEntries >= pq->OSQSize) {               /* Make sure queue is not full                  */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_Q_POST_EXIT(OS_ERR_Q_FULL);
+        return (OS_ERR_Q_FULL);
+    }
+    *pq->OSQIn++ = pmsg;                               /* Insert message into queue                    */
+    pq->OSQEntries++;                                  /* Update the nbr of entries in the queue       */
+    if (pq->OSQIn == pq->OSQEnd) {                     /* Wrap IN ptr if we are at end of queue        */
+        pq->OSQIn = pq->OSQStart;
+    }
+    OS_EXIT_CRITICAL();
+    OS_TRACE_Q_POST_EXIT(OS_ERR_NONE);
+
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                POST MESSAGE TO THE FRONT OF A QUEUE
+*
+* Description: This function sends a message to a queue but unlike OSQPost(), the message is posted at
+*              the front instead of the end of the queue.  Using OSQPostFront() allows you to send
+*              'priority' messages.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Note(s)    : As of V2.60, this function allows you to send NULL pointer messages.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_FRONT_EN > 0u
+INT8U  OSQPostFront (OS_EVENT  *pevent,
+                     void      *pmsg)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+
+    OS_TRACE_Q_POST_FRONT_ENTER(pevent);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        OS_TRACE_Q_POST_FRONT_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                   /* See if any task pending on queue              */
+                                                      /* Ready highest priority task waiting on event  */
+        (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find highest priority task ready to run       */
+        OS_TRACE_Q_POST_FRONT_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_Q_POST_FRONT_EXIT(OS_ERR_Q_FULL);
+        return (OS_ERR_Q_FULL);
+    }
+    if (pq->OSQOut == pq->OSQStart) {                 /* Wrap OUT ptr if we are at the 1st queue entry */
+        pq->OSQOut = pq->OSQEnd;
+    }
+    pq->OSQOut--;
+    *pq->OSQOut = pmsg;                               /* Insert message into queue                     */
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_Q_POST_FRONT_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       POST MESSAGE TO A QUEUE
+*
+* Description: This function sends a message to a queue.  This call has been added to reduce code size
+*              since it can replace both OSQPost() and OSQPostFront().  Also, this function adds the
+*              capability to broadcast a message to ALL tasks waiting on the message queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              pmsg          is a pointer to the message to send.
+*
+*              opt           determines the type of POST performed:
+*                            OS_POST_OPT_NONE         POST to a single waiting task
+*                                                     (Identical to OSQPost())
+*                            OS_POST_OPT_BROADCAST    POST to ALL tasks that are waiting on the queue
+*                            OS_POST_OPT_FRONT        POST as LIFO (Simulates OSQPostFront())
+*                            OS_POST_OPT_NO_SCHED     Indicates that the scheduler will NOT be invoked
+*
+* Returns    : OS_ERR_NONE           The call was successful and the message was sent
+*              OS_ERR_Q_FULL         If the queue cannot accept any more messages because it is full.
+*              OS_ERR_EVENT_TYPE     If you didn't pass a pointer to a queue.
+*              OS_ERR_PEVENT_NULL    If 'pevent' is a NULL pointer
+*
+* Warning    : Interrupts can be disabled for a long time if you do a 'broadcast'.  In fact, the
+*              interrupt disable time is proportional to the number of tasks waiting on the queue.
+*********************************************************************************************************
+*/
+
+#if OS_Q_POST_OPT_EN > 0u
+INT8U  OSQPostOpt (OS_EVENT  *pevent,
+                   void      *pmsg,
+                   INT8U      opt)
+{
+    OS_Q      *pq;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+
+    OS_TRACE_Q_POST_OPT_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {     /* Validate event block type                     */
+        OS_TRACE_Q_POST_OPT_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0x00u) {                /* See if any task pending on queue              */
+        if ((opt & OS_POST_OPT_BROADCAST) != 0x00u) { /* Do we need to post msg to ALL waiting tasks ? */
+            while (pevent->OSEventGrp != 0u) {        /* Yes, Post to ALL tasks waiting on queue       */
+                (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+            }
+        } else {                                      /* No,  Post to HPT waiting on queue             */
+            (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK);
+        }
+        OS_EXIT_CRITICAL();
+        if ((opt & OS_POST_OPT_NO_SCHED) == 0u) {     /* See if scheduler needs to be invoked          */
+            OS_Sched();                               /* Find highest priority task ready to run       */
+        }
+        OS_TRACE_Q_POST_OPT_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;                  /* Point to queue control block                  */
+    if (pq->OSQEntries >= pq->OSQSize) {              /* Make sure queue is not full                   */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_Q_POST_OPT_EXIT(OS_ERR_Q_FULL);
+        return (OS_ERR_Q_FULL);
+    }
+    if ((opt & OS_POST_OPT_FRONT) != 0x00u) {         /* Do we post to the FRONT of the queue?         */
+        if (pq->OSQOut == pq->OSQStart) {             /* Yes, Post as LIFO, Wrap OUT pointer if we ... */
+            pq->OSQOut = pq->OSQEnd;                  /*      ... are at the 1st queue entry           */
+        }
+        pq->OSQOut--;
+        *pq->OSQOut = pmsg;                           /*      Insert message into queue                */
+    } else {                                          /* No,  Post as FIFO                             */
+        *pq->OSQIn++ = pmsg;                          /*      Insert message into queue                */
+        if (pq->OSQIn == pq->OSQEnd) {                /*      Wrap IN ptr if we are at end of queue    */
+            pq->OSQIn = pq->OSQStart;
+        }
+    }
+    pq->OSQEntries++;                                 /* Update the nbr of entries in the queue        */
+    OS_EXIT_CRITICAL();
+    OS_TRACE_Q_POST_OPT_EXIT(OS_ERR_NONE);
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                        QUERY A MESSAGE QUEUE
+*
+* Description: This function obtains information about a message queue.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired queue
+*
+*              p_q_data      is a pointer to a structure that will contain information about the message
+*                            queue.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non queue.
+*              OS_ERR_PEVENT_NULL  If 'pevent'   is a NULL pointer
+*              OS_ERR_PDATA_NULL   If 'p_q_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_Q_QUERY_EN > 0u
+INT8U  OSQQuery (OS_EVENT  *pevent,
+                 OS_Q_DATA *p_q_data)
+{
+    OS_Q       *pq;
+    INT8U       i;
+    OS_PRIO    *psrc;
+    OS_PRIO    *pdest;
+#if OS_CRITICAL_METHOD == 3u                           /* Allocate storage for CPU status register     */
+    OS_CPU_SR   cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                     /* Validate 'pevent'                            */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_q_data == (OS_Q_DATA *)0) {                  /* Validate 'p_q_data'                          */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_Q) {      /* Validate event block type                    */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_q_data->OSEventGrp = pevent->OSEventGrp;         /* Copy message queue wait list                 */
+    psrc                 = &pevent->OSEventTbl[0];
+    pdest                = &p_q_data->OSEventTbl[0];
+    for (i = 0u; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    pq = (OS_Q *)pevent->OSEventPtr;
+    if (pq->OSQEntries > 0u) {
+        p_q_data->OSMsg = *pq->OSQOut;                 /* Get next message to return if available      */
+    } else {
+        p_q_data->OSMsg = (void *)0;
+    }
+    p_q_data->OSNMsgs = pq->OSQEntries;
+    p_q_data->OSQSize = pq->OSQSize;
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                 /* OS_Q_QUERY_EN                                */
+
+
+/*
+*********************************************************************************************************
+*                                     QUEUE MODULE INITIALIZATION
+*
+* Description : This function is called by uC/OS-II to initialize the message queue module.  Your
+*               application MUST NOT call this function.
+*
+* Arguments   :  none
+*
+* Returns     : none
+*
+* Note(s)    : This function is INTERNAL to uC/OS-II and your application should not call it.
+*********************************************************************************************************
+*/
+
+void  OS_QInit (void)
+{
+#if OS_MAX_QS == 1u
+    OSQFreeList         = &OSQTbl[0];                /* Only ONE queue!                                */
+    OSQFreeList->OSQPtr = (OS_Q *)0;
+#endif
+
+#if OS_MAX_QS >= 2u
+    INT16U   ix;
+    INT16U   ix_next;
+    OS_Q    *pq1;
+    OS_Q    *pq2;
+
+
+
+    OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl));  /* Clear the queue table                          */
+    for (ix = 0u; ix < (OS_MAX_QS - 1u); ix++) {     /* Init. list of free QUEUE control blocks        */
+        ix_next = ix + 1u;
+        pq1 = &OSQTbl[ix];
+        pq2 = &OSQTbl[ix_next];
+        pq1->OSQPtr = pq2;
+    }
+    pq1         = &OSQTbl[ix];
+    pq1->OSQPtr = (OS_Q *)0;
+    OSQFreeList = &OSQTbl[0];
+#endif
+}
+#endif                                               /* OS_Q_EN                                        */
+#endif                                               /* OS_Q_C                                         */

Core/OS/Source/os_sem.c

@@ -0,0 +1,679 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                         SEMAPHORE MANAGEMENT
+*
+* Filename : os_sem.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_SEM_C
+#define  OS_SEM_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+#if OS_SEM_EN > 0u
+/*
+*********************************************************************************************************
+*                                          ACCEPT SEMAPHORE
+*
+* Description: This function checks the semaphore to see if a resource is available or, if an event
+*              occurred.  Unlike OSSemPend(), OSSemAccept() does not suspend the calling task if the
+*              resource is not available or the event did not occur.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+* Returns    : >  0       if the resource is available or the event did not occur the semaphore is
+*                         decremented to obtain the resource.
+*              == 0       if the resource is not available or the event did not occur or,
+*                         if 'pevent' is a NULL pointer or,
+*                         if you didn't pass a pointer to a semaphore
+*********************************************************************************************************
+*/
+
+#if OS_SEM_ACCEPT_EN > 0u
+INT16U  OSSemAccept (OS_EVENT *pevent)
+{
+    INT16U     cnt;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (0u);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        return (0u);
+    }
+    OS_ENTER_CRITICAL();
+    cnt = pevent->OSEventCnt;
+    if (cnt > 0u) {                                   /* See if resource is available                  */
+        pevent->OSEventCnt--;                         /* Yes, decrement semaphore and notify caller    */
+    }
+    OS_EXIT_CRITICAL();
+    return (cnt);                                     /* Return semaphore count                        */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                         CREATE A SEMAPHORE
+*
+* Description: This function creates a semaphore.
+*
+* Arguments  : cnt           is the initial value for the semaphore.  If the value is 0, no resource is
+*                            available (or no event has occurred).  You initialize the semaphore to a
+*                            non-zero value to specify how many resources are available (e.g. if you have
+*                            10 resources, you would initialize the semaphore to 10).
+*
+* Returns    : != (void *)0  is a pointer to the event control block (OS_EVENT) associated with the
+*                            created semaphore
+*              == (void *)0  if no event control blocks were available
+*********************************************************************************************************
+*/
+
+OS_EVENT  *OSSemCreate (INT16U cnt)
+{
+    OS_EVENT  *pevent;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        return ((OS_EVENT *)0);                            /* ... can't CREATE from an ISR             */
+    }
+    OS_ENTER_CRITICAL();
+    pevent = OSEventFreeList;                              /* Get next free event control block        */
+    if (OSEventFreeList != (OS_EVENT *)0) {                /* See if pool of free ECB pool was empty   */
+        OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr;
+    }
+    OS_EXIT_CRITICAL();
+    if (pevent != (OS_EVENT *)0) {                         /* Get an event control block               */
+        pevent->OSEventType    = OS_EVENT_TYPE_SEM;
+        pevent->OSEventCnt     = cnt;                      /* Set semaphore value                      */
+        pevent->OSEventPtr     = (void *)0;                /* Unlink from ECB free list                */
+#if OS_EVENT_NAME_EN > 0u
+        pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+        OS_EventWaitListInit(pevent);                      /* Initialize to 'nobody waiting' on sem.   */
+
+        OS_TRACE_SEM_CREATE(pevent, pevent->OSEventName);
+    }
+    return (pevent);
+}
+
+
+/*
+*********************************************************************************************************
+*                                         DELETE A SEMAPHORE
+*
+* Description: This function deletes a semaphore and readies all tasks pending on the semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              opt           determines delete options as follows:
+*                            opt == OS_DEL_NO_PEND   Delete semaphore ONLY if no task pending
+*                            opt == OS_DEL_ALWAYS    Deletes the semaphore even if tasks are waiting.
+*                                                    In this case, all the tasks pending will be readied.
+*
+*              perr          is a pointer to an error code that can contain one of the following values:
+*                            OS_ERR_NONE                  The call was successful and the semaphore was
+*                                                         deleted
+*                            OS_ERR_DEL_ISR               If you attempted to delete the semaphore from an
+*                                                         ISR
+*                            OS_ERR_ILLEGAL_DEL_RUN_TIME  If you tried to delete the semaphore after
+*                                                         safety critical operation started.
+*                            OS_ERR_INVALID_OPT           An invalid option was specified
+*                            OS_ERR_TASK_WAITING          One or more tasks were waiting on the semaphore
+*                            OS_ERR_EVENT_TYPE            If you didn't pass a pointer to a semaphore
+*                            OS_ERR_PEVENT_NULL           If 'pevent' is a NULL pointer.
+*
+* Returns    : pevent        upon error
+*              (OS_EVENT *)0 if the semaphore was successfully deleted.
+*
+* Note(s)    : 1) This function must be used with care.  Tasks that would normally expect the presence of
+*                 the semaphore MUST check the return code of OSSemPend().
+*              2) OSSemAccept() callers will not know that the intended semaphore has been deleted unless
+*                 they check 'pevent' to see that it's a NULL pointer.
+*              3) This call can potentially disable interrupts for a long time.  The interrupt disable
+*                 time is directly proportional to the number of tasks waiting on the semaphore.
+*              4) Because ALL tasks pending on the semaphore will be readied, you MUST be careful in
+*                 applications where the semaphore is used for mutual exclusion because the resource(s)
+*                 will no longer be guarded by the semaphore.
+*              5) All tasks that were waiting for the semaphore will be readied and returned an
+*                 OS_ERR_PEND_ABORT if OSSemDel() was called with OS_DEL_ALWAYS
+*********************************************************************************************************
+*/
+
+#if OS_SEM_DEL_EN > 0u
+OS_EVENT  *OSSemDel (OS_EVENT  *pevent,
+                     INT8U      opt,
+                     INT8U     *perr)
+{
+    BOOLEAN    tasks_waiting;
+    OS_EVENT  *pevent_return;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#ifdef OS_SAFETY_CRITICAL_IEC61508
+    if (OSSafetyCriticalStartFlag == OS_TRUE) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        *perr = OS_ERR_ILLEGAL_DEL_RUN_TIME;
+        return ((OS_EVENT *)0);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (pevent);
+    }
+#endif
+
+    OS_TRACE_SEM_DEL_ENTER(pevent, opt);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_SEM_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    if (OSIntNesting > 0u) {                               /* See if called from ISR ...               */
+        *perr = OS_ERR_DEL_ISR;                            /* ... can't DELETE from an ISR             */
+        OS_TRACE_SEM_DEL_EXIT(*perr);
+        return (pevent);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                        /* See if any tasks waiting on semaphore    */
+        tasks_waiting = OS_TRUE;                           /* Yes                                      */
+    } else {
+        tasks_waiting = OS_FALSE;                          /* No                                       */
+    }
+    switch (opt) {
+        case OS_DEL_NO_PEND:                               /* Delete semaphore only if no task waiting */
+             if (tasks_waiting == OS_FALSE) {
+#if OS_EVENT_NAME_EN > 0u
+                 pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+                 pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+                 pevent->OSEventPtr     = OSEventFreeList; /* Return Event Control Block to free list  */
+                 pevent->OSEventCnt     = 0u;
+                 OSEventFreeList        = pevent;          /* Get next free event control block        */
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_NONE;
+                 pevent_return          = (OS_EVENT *)0;   /* Semaphore has been deleted               */
+             } else {
+                 OS_EXIT_CRITICAL();
+                 *perr                  = OS_ERR_TASK_WAITING;
+                 pevent_return          = pevent;
+             }
+             break;
+
+        case OS_DEL_ALWAYS:                                /* Always delete the semaphore              */
+             while (pevent->OSEventGrp != 0u) {            /* Ready ALL tasks waiting for semaphore    */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+             }
+#if OS_EVENT_NAME_EN > 0u
+             pevent->OSEventName    = (INT8U *)(void *)"?";
+#endif
+             pevent->OSEventType    = OS_EVENT_TYPE_UNUSED;
+             pevent->OSEventPtr     = OSEventFreeList;     /* Return Event Control Block to free list  */
+             pevent->OSEventCnt     = 0u;
+             OSEventFreeList        = pevent;              /* Get next free event control block        */
+             OS_EXIT_CRITICAL();
+             if (tasks_waiting == OS_TRUE) {               /* Reschedule only if task(s) were waiting  */
+                 OS_Sched();                               /* Find highest priority task ready to run  */
+             }
+             *perr                  = OS_ERR_NONE;
+             pevent_return          = (OS_EVENT *)0;       /* Semaphore has been deleted               */
+             break;
+
+        default:
+             OS_EXIT_CRITICAL();
+             *perr                  = OS_ERR_INVALID_OPT;
+             pevent_return          = pevent;
+             break;
+    }
+
+    OS_TRACE_SEM_DEL_EXIT(*perr);
+
+    return (pevent_return);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          PEND ON SEMAPHORE
+*
+* Description: This function waits for a semaphore.
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              timeout       is an optional timeout period (in clock ticks).  If non-zero, your task will
+*                            wait for the resource up to the amount of time specified by this argument.
+*                            If you specify 0, however, your task will wait forever at the specified
+*                            semaphore or, until the resource becomes available (or the event occurs).
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         The call was successful and your task owns the resource
+*                                                or, the event you are waiting for occurred.
+*                            OS_ERR_TIMEOUT      The semaphore was not received within the specified
+*                                                'timeout'.
+*                            OS_ERR_PEND_ABORT   The wait on the semaphore was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEND_ISR     If you called this function from an ISR and the result
+*                                                would lead to a suspension.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*                            OS_ERR_PEND_LOCKED  If you called this function when the scheduler is locked
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSSemPend (OS_EVENT  *pevent,
+                 INT32U     timeout,
+                 INT8U     *perr)
+{
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return;
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+
+    OS_TRACE_SEM_PEND_ENTER(pevent, timeout);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        OS_TRACE_SEM_PEND_EXIT(*perr);
+        return;
+    }
+    if (OSIntNesting > 0u) {                          /* See if called from ISR ...                    */
+        *perr = OS_ERR_PEND_ISR;                      /* ... can't PEND from an ISR                    */
+        OS_TRACE_SEM_PEND_EXIT(*perr);
+        return;
+    }
+    if (OSLockNesting > 0u) {                         /* See if called with scheduler locked ...       */
+        *perr = OS_ERR_PEND_LOCKED;                   /* ... can't PEND when locked                    */
+        OS_TRACE_SEM_PEND_EXIT(*perr);
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventCnt > 0u) {                    /* If sem. is positive, resource available ...   */
+        pevent->OSEventCnt--;                         /* ... decrement semaphore only if positive.     */
+        OS_EXIT_CRITICAL();
+        *perr = OS_ERR_NONE;
+        OS_TRACE_SEM_PEND_EXIT(*perr);
+        return;
+    }
+                                                      /* Otherwise, must wait until event occurs       */
+    OSTCBCur->OSTCBStat     |= OS_STAT_SEM;           /* Resource not available, pend on semaphore     */
+    OSTCBCur->OSTCBStatPend  = OS_STAT_PEND_OK;
+    OSTCBCur->OSTCBDly       = timeout;               /* Store pend timeout in TCB                     */
+    OS_EventTaskWait(pevent);                         /* Suspend task until event or timeout occurs    */
+    OS_EXIT_CRITICAL();
+    OS_Sched();                                       /* Find next highest priority task ready         */
+    OS_ENTER_CRITICAL();
+    switch (OSTCBCur->OSTCBStatPend) {                /* See if we timed-out or aborted                */
+        case OS_STAT_PEND_OK:
+             *perr = OS_ERR_NONE;
+             break;
+
+        case OS_STAT_PEND_ABORT:
+             *perr = OS_ERR_PEND_ABORT;               /* Indicate that we aborted                      */
+             break;
+
+        case OS_STAT_PEND_TO:
+        default:
+             OS_EventTaskRemove(OSTCBCur, pevent);
+             *perr = OS_ERR_TIMEOUT;                  /* Indicate that we didn't get event within TO   */
+             break;
+    }
+    OSTCBCur->OSTCBStat          =  OS_STAT_RDY;      /* Set   task  status to ready                   */
+    OSTCBCur->OSTCBStatPend      =  OS_STAT_PEND_OK;  /* Clear pend  status                            */
+    OSTCBCur->OSTCBEventPtr      = (OS_EVENT  *)0;    /* Clear event pointers                          */
+#if (OS_EVENT_MULTI_EN > 0u)
+    OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0;
+    OSTCBCur->OSTCBEventMultiRdy = (OS_EVENT  *)0;
+#endif
+    OS_EXIT_CRITICAL();
+
+    OS_TRACE_SEM_PEND_EXIT(*perr);
+}
+
+
+/*
+*********************************************************************************************************
+*                                    ABORT WAITING ON A SEMAPHORE
+*
+* Description: This function aborts & readies any tasks currently waiting on a semaphore.  This function
+*              should be used to fault-abort the wait on the semaphore, rather than to normally signal
+*              the semaphore via OSSemPost().
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+*              opt           determines the type of ABORT performed:
+*                            OS_PEND_OPT_NONE         ABORT wait for a single task (HPT) waiting on the
+*                                                     semaphore
+*                            OS_PEND_OPT_BROADCAST    ABORT wait for ALL tasks that are  waiting on the
+*                                                     semaphore
+*
+*              perr          is a pointer to where an error message will be deposited.  Possible error
+*                            messages are:
+*
+*                            OS_ERR_NONE         No tasks were     waiting on the semaphore.
+*                            OS_ERR_PEND_ABORT   At least one task waiting on the semaphore was readied
+*                                                and informed of the aborted wait; check return value
+*                                                for the number of tasks whose wait on the semaphore
+*                                                was aborted.
+*                            OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*
+* Returns    : == 0          if no tasks were waiting on the semaphore, or upon error.
+*              >  0          if one or more tasks waiting on the semaphore are now readied and informed.
+*********************************************************************************************************
+*/
+
+#if OS_SEM_PEND_ABORT_EN > 0u
+INT8U  OSSemPendAbort (OS_EVENT  *pevent,
+                       INT8U      opt,
+                       INT8U     *perr)
+{
+    INT8U      nbr_tasks;
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return (0u);
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return (0u);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return (0u);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                   /* See if any task waiting on semaphore?         */
+        nbr_tasks = 0u;
+        switch (opt) {
+            case OS_PEND_OPT_BROADCAST:               /* Do we need to abort ALL waiting tasks?        */
+                 while (pevent->OSEventGrp != 0u) {   /* Yes, ready ALL tasks waiting on semaphore     */
+                     (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+                     nbr_tasks++;
+                 }
+                 break;
+
+            case OS_PEND_OPT_NONE:
+            default:                                  /* No,  ready HPT       waiting on semaphore     */
+                 (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT);
+                 nbr_tasks++;
+                 break;
+        }
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+        *perr = OS_ERR_PEND_ABORT;
+        return (nbr_tasks);
+    }
+    OS_EXIT_CRITICAL();
+    *perr = OS_ERR_NONE;
+    return (0u);                                      /* No tasks waiting on semaphore                 */
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                         POST TO A SEMAPHORE
+*
+* Description: This function signals a semaphore
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the semaphore was signaled.
+*              OS_ERR_SEM_OVF      If the semaphore count exceeded its limit. In other words, you have
+*                                  signaled the semaphore more often than you waited on it with either
+*                                  OSSemAccept() or OSSemPend().
+*              OS_ERR_EVENT_TYPE   If you didn't pass a pointer to a semaphore
+*              OS_ERR_PEVENT_NULL  If 'pevent' is a NULL pointer.
+*********************************************************************************************************
+*/
+
+INT8U  OSSemPost (OS_EVENT *pevent)
+{
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        return (OS_ERR_PEVENT_NULL);
+    }
+#endif
+
+    OS_TRACE_SEM_POST_ENTER(pevent);
+
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        OS_TRACE_SEM_POST_EXIT(OS_ERR_EVENT_TYPE);
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    if (pevent->OSEventGrp != 0u) {                   /* See if any task waiting for semaphore         */
+                                                      /* Ready HPT waiting on event                    */
+        (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                   /* Find HPT ready to run                         */
+        OS_TRACE_SEM_POST_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    if (pevent->OSEventCnt < 65535u) {                /* Make sure semaphore will not overflow         */
+        pevent->OSEventCnt++;                         /* Increment semaphore count to register event   */
+        OS_EXIT_CRITICAL();
+        OS_TRACE_SEM_POST_EXIT(OS_ERR_NONE);
+        return (OS_ERR_NONE);
+    }
+    OS_EXIT_CRITICAL();                               /* Semaphore value has reached its maximum       */
+    OS_TRACE_SEM_POST_EXIT(OS_ERR_SEM_OVF);
+
+    return (OS_ERR_SEM_OVF);
+}
+
+
+/*
+*********************************************************************************************************
+*                                          QUERY A SEMAPHORE
+*
+* Description: This function obtains information about a semaphore
+*
+* Arguments  : pevent        is a pointer to the event control block associated with the desired
+*                            semaphore
+*
+*              p_sem_data    is a pointer to a structure that will contain information about the
+*                            semaphore.
+*
+* Returns    : OS_ERR_NONE         The call was successful and the message was sent
+*              OS_ERR_EVENT_TYPE   If you are attempting to obtain data from a non semaphore.
+*              OS_ERR_PEVENT_NULL  If 'pevent'     is a NULL pointer.
+*              OS_ERR_PDATA_NULL   If 'p_sem_data' is a NULL pointer
+*********************************************************************************************************
+*/
+
+#if OS_SEM_QUERY_EN > 0u
+INT8U  OSSemQuery (OS_EVENT     *pevent,
+                   OS_SEM_DATA  *p_sem_data)
+{
+    INT8U       i;
+    OS_PRIO    *psrc;
+    OS_PRIO    *pdest;
+#if OS_CRITICAL_METHOD == 3u                               /* Allocate storage for CPU status register */
+    OS_CPU_SR   cpu_sr = 0u;
+#endif
+
+
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                         /* Validate 'pevent'                        */
+        return (OS_ERR_PEVENT_NULL);
+    }
+    if (p_sem_data == (OS_SEM_DATA *)0) {                  /* Validate 'p_sem_data'                    */
+        return (OS_ERR_PDATA_NULL);
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {        /* Validate event block type                */
+        return (OS_ERR_EVENT_TYPE);
+    }
+    OS_ENTER_CRITICAL();
+    p_sem_data->OSEventGrp = pevent->OSEventGrp;           /* Copy message mailbox wait list           */
+    psrc                   = &pevent->OSEventTbl[0];
+    pdest                  = &p_sem_data->OSEventTbl[0];
+    for (i = 0u; i < OS_EVENT_TBL_SIZE; i++) {
+        *pdest++ = *psrc++;
+    }
+    p_sem_data->OSCnt = pevent->OSEventCnt;                /* Get semaphore count                      */
+    OS_EXIT_CRITICAL();
+    return (OS_ERR_NONE);
+}
+#endif                                                     /* OS_SEM_QUERY_EN                          */
+
+
+/*
+*********************************************************************************************************
+*                                            SET SEMAPHORE
+*
+* Description: This function sets the semaphore count to the value specified as an argument.  Typically,
+*              this value would be 0.
+*
+*              You would typically use this function when a semaphore is used as a signaling mechanism
+*              and, you want to reset the count value.
+*
+* Arguments  : pevent     is a pointer to the event control block
+*
+*              cnt        is the new value for the semaphore count.  You would pass 0 to reset the
+*                         semaphore count.
+*
+*              perr       is a pointer to an error code returned by the function as follows:
+*
+*                            OS_ERR_NONE          The call was successful and the semaphore value was set.
+*                            OS_ERR_EVENT_TYPE    If you didn't pass a pointer to a semaphore.
+*                            OS_ERR_PEVENT_NULL   If 'pevent' is a NULL pointer.
+*                            OS_ERR_TASK_WAITING  If tasks are waiting on the semaphore.
+*********************************************************************************************************
+*/
+
+#if OS_SEM_SET_EN > 0u
+void  OSSemSet (OS_EVENT  *pevent,
+                INT16U     cnt,
+                INT8U     *perr)
+{
+#if OS_CRITICAL_METHOD == 3u                          /* Allocate storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+#ifdef OS_SAFETY_CRITICAL
+    if (perr == (INT8U *)0) {
+        OS_SAFETY_CRITICAL_EXCEPTION();
+        return;
+    }
+#endif
+
+#if OS_ARG_CHK_EN > 0u
+    if (pevent == (OS_EVENT *)0) {                    /* Validate 'pevent'                             */
+        *perr = OS_ERR_PEVENT_NULL;
+        return;
+    }
+#endif
+    if (pevent->OSEventType != OS_EVENT_TYPE_SEM) {   /* Validate event block type                     */
+        *perr = OS_ERR_EVENT_TYPE;
+        return;
+    }
+    OS_ENTER_CRITICAL();
+    *perr = OS_ERR_NONE;
+    if (pevent->OSEventCnt > 0u) {                    /* See if semaphore already has a count          */
+        pevent->OSEventCnt = cnt;                     /* Yes, set it to the new value specified.       */
+    } else {                                          /* No                                            */
+        if (pevent->OSEventGrp == 0u) {               /*      See if task(s) waiting?                  */
+            pevent->OSEventCnt = cnt;                 /*      No, OK to set the value                  */
+        } else {
+            *perr              = OS_ERR_TASK_WAITING;
+        }
+    }
+    OS_EXIT_CRITICAL();
+}
+#endif
+
+#endif                                                /* OS_SEM_EN                                     */
+#endif                                                /* OS_SEM_C                                      */

Core/OS/Source/os_time.c

@@ -0,0 +1,280 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                            TIME MANAGEMENT
+*
+* Filename : os_time.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#ifndef  OS_TIME_C
+#define  OS_TIME_C
+
+#define  MICRIUM_SOURCE
+
+#ifndef  OS_MASTER_FILE
+#include <ucos_ii.h>
+#endif
+
+/*
+*********************************************************************************************************
+*                                        DELAY TASK 'n' TICKS
+*
+* Description: This function is called to delay execution of the currently running task until the
+*              specified number of system ticks expires.  This, of course, directly equates to delaying
+*              the current task for some time to expire.  No delay will result If the specified delay is
+*              0.  If the specified delay is greater than 0 then, a context switch will result.
+*
+* Arguments  : ticks     is the time delay that the task will be suspended in number of clock 'ticks'.
+*                        Note that by specifying 0, the task will not be delayed.
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+void  OSTimeDly (INT32U ticks)
+{
+    INT8U      y;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+    if (OSIntNesting > 0u) {                     /* See if trying to call from an ISR                  */
+        return;
+    }
+    if (OSLockNesting > 0u) {                    /* See if called with scheduler locked                */
+        return;
+    }
+    if (ticks > 0u) {                            /* 0 means no delay!                                  */
+        OS_ENTER_CRITICAL();
+        y            =  OSTCBCur->OSTCBY;        /* Delay current task                                 */
+        OSRdyTbl[y] &= (OS_PRIO)~OSTCBCur->OSTCBBitX;
+        OS_TRACE_TASK_SUSPENDED(OSTCBCur);
+        if (OSRdyTbl[y] == 0u) {
+            OSRdyGrp &= (OS_PRIO)~OSTCBCur->OSTCBBitY;
+        }
+        OSTCBCur->OSTCBDly = ticks;              /* Load ticks in TCB                                  */
+        OS_TRACE_TASK_DLY(ticks);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                              /* Find next task to run!                             */
+    }
+}
+
+
+/*
+*********************************************************************************************************
+*                                    DELAY TASK FOR SPECIFIED TIME
+*
+* Description: This function is called to delay execution of the currently running task until some time
+*              expires.  This call allows you to specify the delay time in HOURS, MINUTES, SECONDS and
+*              MILLISECONDS instead of ticks.
+*
+* Arguments  : hours     specifies the number of hours that the task will be delayed (max. is 255)
+*              minutes   specifies the number of minutes (max. 59)
+*              seconds   specifies the number of seconds (max. 59)
+*              ms        specifies the number of milliseconds (max. 999)
+*
+* Returns    : OS_ERR_NONE
+*              OS_ERR_TIME_INVALID_MINUTES
+*              OS_ERR_TIME_INVALID_SECONDS
+*              OS_ERR_TIME_INVALID_MS
+*              OS_ERR_TIME_ZERO_DLY
+*              OS_ERR_TIME_DLY_ISR
+*
+* Note(s)    : The resolution on the milliseconds depends on the tick rate.  For example, you can't do
+*              a 10 mS delay if the ticker interrupts every 100 mS.  In this case, the delay would be
+*              set to 0.  The actual delay is rounded to the nearest tick.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_HMSM_EN > 0u
+INT8U  OSTimeDlyHMSM (INT8U   hours,
+                      INT8U   minutes,
+                      INT8U   seconds,
+                      INT16U  ms)
+{
+    INT32U ticks;
+
+
+    if (OSIntNesting > 0u) {                     /* See if trying to call from an ISR                  */
+        return (OS_ERR_TIME_DLY_ISR);
+    }
+    if (OSLockNesting > 0u) {                    /* See if called with scheduler locked                */
+        return (OS_ERR_SCHED_LOCKED);
+    }
+#if OS_ARG_CHK_EN > 0u
+    if (hours == 0u) {
+        if (minutes == 0u) {
+            if (seconds == 0u) {
+                if (ms == 0u) {
+                    return (OS_ERR_TIME_ZERO_DLY);
+                }
+            }
+        }
+    }
+    if (minutes > 59u) {
+        return (OS_ERR_TIME_INVALID_MINUTES);    /* Validate arguments to be within range              */
+    }
+    if (seconds > 59u) {
+        return (OS_ERR_TIME_INVALID_SECONDS);
+    }
+    if (ms > 999u) {
+        return (OS_ERR_TIME_INVALID_MS);
+    }
+#endif
+                                                 /* Compute the total number of clock ticks required.. */
+                                                 /* .. (rounded to the nearest tick)                   */
+    ticks = ((INT32U)hours * 3600uL + (INT32U)minutes * 60uL + (INT32U)seconds) * OS_TICKS_PER_SEC
+          + OS_TICKS_PER_SEC * ((INT32U)ms + 500uL / OS_TICKS_PER_SEC) / 1000uL;
+    OSTimeDly(ticks);
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                        RESUME A DELAYED TASK
+*
+* Description: This function is used resume a task that has been delayed through a call to either
+*              OSTimeDly() or OSTimeDlyHMSM().  Note that you can call this function to resume a
+*              task that is waiting for an event with timeout.  This would make the task look
+*              like a timeout occurred.
+*
+* Arguments  : prio                      specifies the priority of the task to resume
+*
+* Returns    : OS_ERR_NONE               Task has been resumed
+*              OS_ERR_PRIO_INVALID       if the priority you specify is higher that the maximum allowed
+*                                        (i.e. >= OS_LOWEST_PRIO)
+*              OS_ERR_TIME_NOT_DLY       Task is not waiting for time to expire
+*              OS_ERR_TASK_NOT_EXIST     The desired task has not been created or has been assigned to a Mutex.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_DLY_RESUME_EN > 0u
+INT8U  OSTimeDlyResume (INT8U prio)
+{
+    OS_TCB    *ptcb;
+#if OS_CRITICAL_METHOD == 3u                                   /* Storage for CPU status register      */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+    if (prio >= OS_LOWEST_PRIO) {
+        return (OS_ERR_PRIO_INVALID);
+    }
+    OS_ENTER_CRITICAL();
+    ptcb = OSTCBPrioTbl[prio];                                 /* Make sure that task exist            */
+    if (ptcb == (OS_TCB *)0) {
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+    }
+    if (ptcb == OS_TCB_RESERVED) {
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TASK_NOT_EXIST);                        /* The task does not exist              */
+    }
+    if (ptcb->OSTCBDly == 0u) {                                /* See if task is delayed               */
+        OS_EXIT_CRITICAL();
+        return (OS_ERR_TIME_NOT_DLY);                          /* Indicate that task was not delayed   */
+    }
+
+    ptcb->OSTCBDly = 0u;                                       /* Clear the time delay                 */
+    if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) {
+        ptcb->OSTCBStat     &= ~OS_STAT_PEND_ANY;              /* Yes, Clear status flag               */
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_TO;               /* Indicate PEND timeout                */
+    } else {
+        ptcb->OSTCBStatPend  =  OS_STAT_PEND_OK;
+    }
+    if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) {  /* Is task suspended?                   */
+        OSRdyGrp               |= ptcb->OSTCBBitY;             /* No,  Make ready                      */
+        OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX;
+        OS_TRACE_TASK_READY(ptcb);
+        OS_EXIT_CRITICAL();
+        OS_Sched();                                            /* See if this is new highest priority  */
+    } else {
+        OS_EXIT_CRITICAL();                                    /* Task may be suspended                */
+    }
+    return (OS_ERR_NONE);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                       GET CURRENT SYSTEM TIME
+*
+* Description: This function is used by your application to obtain the current value of the 32-bit
+*              counter which keeps track of the number of clock ticks.
+*
+* Arguments  : none
+*
+* Returns    : The current value of OSTime
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0u
+INT32U  OSTimeGet (void)
+{
+    INT32U     ticks;
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    ticks = OSTime;
+    OS_EXIT_CRITICAL();
+    return (ticks);
+}
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          SET SYSTEM CLOCK
+*
+* Description: This function sets the 32-bit counter which keeps track of the number of clock ticks.
+*
+* Arguments  : ticks      specifies the new value that OSTime needs to take.
+*
+* Returns    : none
+*********************************************************************************************************
+*/
+
+#if OS_TIME_GET_SET_EN > 0u
+void  OSTimeSet (INT32U ticks)
+{
+#if OS_CRITICAL_METHOD == 3u                     /* Allocate storage for CPU status register           */
+    OS_CPU_SR  cpu_sr = 0u;
+#endif
+
+
+
+    OS_ENTER_CRITICAL();
+    OSTime = ticks;
+    OS_EXIT_CRITICAL();
+}
+#endif
+#endif                                           /* OS_TIME_C                                          */

Core/OS/Source/os_trace.h

@@ -0,0 +1,474 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*
+*                                             TRACE SUPPORT
+*
+* Filename : os_trace.h
+* Version  : V2.93.00
+*********************************************************************************************************
+* Note(s) : (1) The header file os_trace_events.h is the interface between uC/OS-II and your trace
+*               recorder of choice.
+*               To support trace recording, include one of the sub-folders at uCOS-II/Trace/ into
+*               your project.
+*********************************************************************************************************
+*/
+
+#ifndef   OS_TRACE_H
+#define   OS_TRACE_H
+
+#include  <os_cfg.h>
+
+#if (defined(OS_TRACE_EN) && (OS_TRACE_EN > 0u))
+#include  <os_trace_events.h>                                   /* See Note #1.                                         */
+#endif
+
+
+/*
+**************************************************************************************************************************
+*                                        uC/OS-II Trace Default Macros (Empty)
+**************************************************************************************************************************
+*/
+
+#ifndef  OS_TRACE_INIT
+#define  OS_TRACE_INIT()
+#endif
+#ifndef  OS_TRACE_START
+#define  OS_TRACE_START()
+#endif
+#ifndef  OS_TRACE_STOP
+#define  OS_TRACE_STOP()
+#endif
+#ifndef  OS_TRACE_CLEAR
+#define  OS_TRACE_CLEAR()
+#endif
+
+#ifndef  OS_TRACE_ISR_ENTER
+#define  OS_TRACE_ISR_ENTER()
+#endif
+#ifndef  OS_TRACE_ISR_EXIT
+#define  OS_TRACE_ISR_EXIT()
+#endif
+#ifndef  OS_TRACE_ISR_EXIT_TO_SCHEDULER
+#define  OS_TRACE_ISR_EXIT_TO_SCHEDULER()
+#endif
+
+#ifndef  OS_TRACE_TICK_INCREMENT
+#define  OS_TRACE_TICK_INCREMENT(OSTickCtr)
+#endif
+
+#ifndef  OS_TRACE_TASK_CREATE
+#define  OS_TRACE_TASK_CREATE(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_CREATE_FAILED
+#define  OS_TRACE_TASK_CREATE_FAILED(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_DEL
+#define  OS_TRACE_TASK_DEL(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_READY
+#define  OS_TRACE_TASK_READY(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_SWITCHED_IN
+#define  OS_TRACE_TASK_SWITCHED_IN(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_DLY
+#define  OS_TRACE_TASK_DLY(dly_ticks)
+#endif
+
+#ifndef  OS_TRACE_TASK_SUSPEND
+#define  OS_TRACE_TASK_SUSPEND(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_SUSPENDED
+#define  OS_TRACE_TASK_SUSPENDED(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_RESUME
+#define  OS_TRACE_TASK_RESUME(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_TASK_PRIO_CHANGE
+#define  OS_TRACE_TASK_PRIO_CHANGE(p_tcb, prio)
+#endif
+
+#ifndef  OS_TRACE_TASK_NAME_SET
+#define  OS_TRACE_TASK_NAME_SET(p_tcb)
+#endif
+
+#ifndef  OS_TRACE_EVENT_NAME_SET
+#define  OS_TRACE_EVENT_NAME_SET(p_event, p_name)
+#endif
+
+#ifndef  OS_TRACE_ISR_REGISTER
+#define  OS_TRACE_ISR_REGISTER(isr_id, isr_name, isr_prio)
+#endif
+
+#ifndef  OS_TRACE_ISR_BEGIN
+#define  OS_TRACE_ISR_BEGIN(isr_id)
+#endif
+
+#ifndef  OS_TRACE_ISR_END
+#define  OS_TRACE_ISR_END()
+#endif
+
+#ifndef  OS_TRACE_MBOX_CREATE
+#define  OS_TRACE_MBOX_CREATE(p_mbox, p_name)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_CREATE
+#define  OS_TRACE_MUTEX_CREATE(p_mutex, p_name)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_DEL
+#define  OS_TRACE_MUTEX_DEL(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_POST
+#define  OS_TRACE_MUTEX_POST(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_POST_FAILED
+#define  OS_TRACE_MUTEX_POST_FAILED(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_PEND
+#define  OS_TRACE_MUTEX_PEND(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_PEND_FAILED
+#define  OS_TRACE_MUTEX_PEND_FAILED(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_PEND_BLOCK
+#define  OS_TRACE_MUTEX_PEND_BLOCK(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_TASK_PRIO_INHERIT
+#define  OS_TRACE_MUTEX_TASK_PRIO_INHERIT(p_tcb, prio)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_TASK_PRIO_DISINHERIT
+#define  OS_TRACE_MUTEX_TASK_PRIO_DISINHERIT(p_tcb, prio)
+#endif
+
+#ifndef  OS_TRACE_SEM_CREATE
+#define  OS_TRACE_SEM_CREATE(p_sem, p_name)
+#endif
+
+#ifndef  OS_TRACE_SEM_DEL
+#define  OS_TRACE_SEM_DEL(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_POST
+#define  OS_TRACE_SEM_POST(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_POST_FAILED
+#define  OS_TRACE_SEM_POST_FAILED(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_PEND
+#define  OS_TRACE_SEM_PEND(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_PEND_FAILED
+#define  OS_TRACE_SEM_PEND_FAILED(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_PEND_BLOCK
+#define  OS_TRACE_SEM_PEND_BLOCK(p_sem)
+#endif
+
+#ifndef  OS_TRACE_Q_CREATE
+#define  OS_TRACE_Q_CREATE(p_q, p_name)
+#endif
+
+#ifndef  OS_TRACE_Q_DEL
+#define  OS_TRACE_Q_DEL(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_POST
+#define  OS_TRACE_Q_POST(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_FAILED
+#define  OS_TRACE_Q_POST_FAILED(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_PEND
+#define  OS_TRACE_Q_PEND(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_PEND_FAILED
+#define  OS_TRACE_Q_PEND_FAILED(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_PEND_BLOCK
+#define  OS_TRACE_Q_PEND_BLOCK(p_q)
+#endif
+
+#ifndef  OS_TRACE_FLAG_CREATE
+#define  OS_TRACE_FLAG_CREATE(p_grp, p_name)
+#endif
+
+#ifndef  OS_TRACE_FLAG_DEL
+#define  OS_TRACE_FLAG_DEL(p_grp)
+#endif
+
+#ifndef  OS_TRACE_FLAG_POST
+#define  OS_TRACE_FLAG_POST(p_grp)
+#endif
+
+#ifndef  OS_TRACE_FLAG_POST_FAILED
+#define  OS_TRACE_FLAG_POST_FAILED(p_grp)
+#endif
+
+#ifndef  OS_TRACE_FLAG_PEND
+#define  OS_TRACE_FLAG_PEND(p_grp)
+#endif
+
+#ifndef  OS_TRACE_FLAG_PEND_FAILED
+#define  OS_TRACE_FLAG_PEND_FAILED(p_grp)
+#endif
+
+#ifndef  OS_TRACE_FLAG_PEND_BLOCK
+#define  OS_TRACE_FLAG_PEND_BLOCK(p_grp)
+#endif
+
+#ifndef  OS_TRACE_MEM_CREATE
+#define  OS_TRACE_MEM_CREATE(p_mem)
+#endif
+
+#ifndef  OS_TRACE_MEM_PUT
+#define  OS_TRACE_MEM_PUT(p_mem)
+#endif
+
+#ifndef  OS_TRACE_MEM_PUT_FAILED
+#define  OS_TRACE_MEM_PUT_FAILED(p_mem)
+#endif
+
+#ifndef  OS_TRACE_MEM_GET
+#define  OS_TRACE_MEM_GET(p_mem)
+#endif
+
+#ifndef  OS_TRACE_MEM_GET_FAILED
+#define  OS_TRACE_MEM_GET_FAILED(p_mem)
+#endif
+
+#ifndef  OS_TRACE_TMR_CREATE
+#define  OS_TRACE_TMR_CREATE(p_tmr, p_name)
+#endif
+
+
+
+#ifndef  OS_TRACE_MBOX_DEL_ENTER
+#define  OS_TRACE_MBOX_DEL_ENTER(p_mbox, opt)
+#endif
+
+#ifndef  OS_TRACE_MBOX_POST_ENTER
+#define  OS_TRACE_MBOX_POST_ENTER(p_mbox)
+#endif
+
+#ifndef  OS_TRACE_MBOX_POST_OPT_ENTER
+#define  OS_TRACE_MBOX_POST_OPT_ENTER(p_mbox, opt)
+#endif
+
+#ifndef  OS_TRACE_MBOX_PEND_ENTER
+#define  OS_TRACE_MBOX_PEND_ENTER(p_mbox, timeout)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_DEL_ENTER
+#define  OS_TRACE_MUTEX_DEL_ENTER(p_mutex, opt)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_POST_ENTER
+#define  OS_TRACE_MUTEX_POST_ENTER(p_mutex)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_PEND_ENTER
+#define  OS_TRACE_MUTEX_PEND_ENTER(p_mutex, timeout)
+#endif
+
+#ifndef  OS_TRACE_SEM_DEL_ENTER
+#define  OS_TRACE_SEM_DEL_ENTER(p_sem, opt)
+#endif
+
+#ifndef  OS_TRACE_SEM_POST_ENTER
+#define  OS_TRACE_SEM_POST_ENTER(p_sem)
+#endif
+
+#ifndef  OS_TRACE_SEM_PEND_ENTER
+#define  OS_TRACE_SEM_PEND_ENTER(p_sem, timeout)
+#endif
+
+#ifndef  OS_TRACE_Q_DEL_ENTER
+#define  OS_TRACE_Q_DEL_ENTER(p_q, opt)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_ENTER
+#define  OS_TRACE_Q_POST_ENTER(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_FRONT_ENTER
+#define  OS_TRACE_Q_POST_FRONT_ENTER(p_q)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_OPT_ENTER
+#define  OS_TRACE_Q_POST_OPT_ENTER(p_q, opt)
+#endif
+
+#ifndef  OS_TRACE_Q_PEND_ENTER
+#define  OS_TRACE_Q_PEND_ENTER(p_q, timeout)
+#endif
+
+#ifndef  OS_TRACE_FLAG_DEL_ENTER
+#define  OS_TRACE_FLAG_DEL_ENTER(p_grp, opt)
+#endif
+
+#ifndef  OS_TRACE_TMR_DEL_ENTER
+#define  OS_TRACE_TMR_DEL_ENTER(p_tmr)
+#endif
+
+#ifndef  OS_TRACE_TMR_START_ENTER
+#define  OS_TRACE_TMR_START_ENTER(p_tmr)
+#endif
+
+#ifndef  OS_TRACE_TMR_STOP_ENTER
+#define  OS_TRACE_TMR_STOP_ENTER(p_tmr)
+#endif
+
+#ifndef  OS_TRACE_TMR_EXPIRED
+#define  OS_TRACE_TMR_EXPIRED(p_tmr)
+#endif
+
+#ifndef  OS_TRACE_FLAG_POST_ENTER
+#define  OS_TRACE_FLAG_POST_ENTER(p_grp, flags, opt)
+#endif
+
+#ifndef  OS_TRACE_FLAG_PEND_ENTER
+#define  OS_TRACE_FLAG_PEND_ENTER(p_grp, flags, timeout, opt)
+#endif
+
+#ifndef  OS_TRACE_MEM_PUT_ENTER
+#define  OS_TRACE_MEM_PUT_ENTER(p_mem, p_blk)
+#endif
+
+#ifndef  OS_TRACE_MEM_GET_ENTER
+#define  OS_TRACE_MEM_GET_ENTER(p_mem)
+#endif
+
+#ifndef  OS_TRACE_MBOX_DEL_EXIT
+#define  OS_TRACE_MBOX_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MBOX_POST_EXIT
+#define  OS_TRACE_MBOX_POST_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MBOX_POST_OPT_EXIT
+#define  OS_TRACE_MBOX_POST_OPT_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MBOX_PEND_EXIT
+#define  OS_TRACE_MBOX_PEND_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_DEL_EXIT
+#define  OS_TRACE_MUTEX_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_POST_EXIT
+#define  OS_TRACE_MUTEX_POST_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MUTEX_PEND_EXIT
+#define  OS_TRACE_MUTEX_PEND_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_SEM_DEL_EXIT
+#define  OS_TRACE_SEM_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_SEM_POST_EXIT
+#define  OS_TRACE_SEM_POST_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_SEM_PEND_EXIT
+#define  OS_TRACE_SEM_PEND_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_Q_DEL_EXIT
+#define  OS_TRACE_Q_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_EXIT
+#define  OS_TRACE_Q_POST_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_FRONT_EXIT
+#define  OS_TRACE_Q_POST_FRONT_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_Q_POST_OPT_EXIT
+#define  OS_TRACE_Q_POST_OPT_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_Q_PEND_EXIT
+#define  OS_TRACE_Q_PEND_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_FLAG_DEL_EXIT
+#define  OS_TRACE_FLAG_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_FLAG_POST_EXIT
+#define  OS_TRACE_FLAG_POST_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_FLAG_PEND_EXIT
+#define  OS_TRACE_FLAG_PEND_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MEM_PUT_EXIT
+#define  OS_TRACE_MEM_PUT_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_MEM_GET_EXIT
+#define  OS_TRACE_MEM_GET_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_TMR_DEL_EXIT
+#define  OS_TRACE_TMR_DEL_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_TMR_START_EXIT
+#define  OS_TRACE_TMR_START_EXIT(RetVal)
+#endif
+
+#ifndef  OS_TRACE_TMR_STOP_EXIT
+#define  OS_TRACE_TMR_STOP_EXIT(RetVal)
+#endif
+
+#endif

Core/OS/Source/ucos_ii.c

@@ -0,0 +1,39 @@
+/*
+*********************************************************************************************************
+*                                              uC/OS-II
+*                                        The Real-Time Kernel
+*
+*                    Copyright 1992-2020 Silicon Laboratories Inc. www.silabs.com
+*
+*                                 SPDX-License-Identifier: APACHE-2.0
+*
+*               This software is subject to an open source license and is distributed by
+*                Silicon Laboratories Inc. pursuant to the terms of the Apache License,
+*                    Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
+*
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+* Filename : ucos_ii.c
+* Version  : V2.93.00
+*********************************************************************************************************
+*/
+
+#define  OS_GLOBALS                           /* Declare GLOBAL variables                              */
+#include <ucos_ii.h>
+
+
+#define  OS_MASTER_FILE                       /* Prevent the following files from including includes.h */
+#include <os_core.c>
+#include <os_flag.c>
+#include <os_mbox.c>
+#include <os_mem.c>
+#include <os_mutex.c>
+#include <os_q.c>
+#include <os_sem.c>
+#include <os_task.c>
+#include <os_time.c>
+#include <os_tmr.c>

Core/Src/main.c

@@ -0,0 +1,433 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "modbus.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/*   uC/OS-II Task Stacks   */
+static OS_STK  App_TaskStartStk[APP_TASK_START_STK_SIZE];
+static OS_STK  App_TaskLedStk[APP_TASK_LED_STK_SIZE];
+static OS_STK  App_TaskModbusStk[256u];
+static OS_STK  App_TaskT35CheckStk[128u];
+
+/*   USART1 & Modbus   */
+UART_HandleTypeDef      huart1;
+static Modbus_Slave_t   ModbusSlave;
+static OS_EVENT        *ModbusSem;          /* 信号量: 通知 Modbus 任务有新帧 */
+
+/*   Modbus RX 缓冲区   */
+static uint8_t  ModbusRxBuf[MODBUS_RX_BUF_SIZE];
+static uint16_t ModbusRxLen  = 0u;
+static uint32_t ModbusRxTick = 0u;          /* 最后收到字节的 tick */
+
+/*   Modbus TX 缓冲区   */
+static uint8_t  ModbusTxBuf[MODBUS_TX_BUF_SIZE];
+static uint16_t ModbusTxLen = 0u;
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+/* USER CODE BEGIN PFP */
+
+/*   uC/OS-II Task Prototypes   */
+static void  App_TaskStart(void *p_arg);
+static void  App_TaskLed(void *p_arg);
+static void  App_TaskModbus(void *p_arg);
+
+/*   Local Functions   */
+static void  MX_USART1_UART_Init(void);
+static void  USART1_StartRx(void);
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/*
+*********************************************************************************************************
+*                                          LED 闪烁任务
+*********************************************************************************************************
+*/
+static void App_TaskLed(void *p_arg)
+{
+    (void)p_arg;
+
+    while (1) {
+        LED_TOGGLE();
+        OSTimeDlyHMSM(0, 0, 0, 100);                     /* 100ms 闪烁，Modbus 通信时更明显 */
+    }
+}
+
+/*
+*********************************************************************************************************
+*                                      MODBUS 从站任务
+*
+*  等待信号量 → 处理 Modbus 帧 → 发送响应 → 重新启动接收
+*********************************************************************************************************
+*/
+static void App_TaskModbus(void *p_arg)
+{
+    uint8_t  err;
+    uint16_t tx_len;
+    INT8U    os_err;
+
+    (void)p_arg;
+
+    Modbus_SlaveInit(&ModbusSlave, MODBUS_SLAVE_ADDR_DEFAULT);
+    USART1_StartRx();                                     /* 启动第一次接收 */
+
+    while (1) {
+        /* 等待帧接收完成信号（超时 10ms，用于检测 T3.5 超时） */
+        OSSemPend(ModbusSem, MODBUS_T35_TIMEOUT, &os_err);
+
+        /* 检查是否收到完整帧 */
+        if (ModbusRxLen > 0u) {
+            /* 处理 Modbus 帧 */
+            err = Modbus_ProcessFrame(&ModbusSlave,
+                                      ModbusRxBuf, ModbusRxLen,
+                                      ModbusTxBuf, &tx_len);
+
+            /* 发送响应（成功或异常响应都需要发送） */
+            if (err >= 0 && tx_len > 0u) {
+                HAL_UART_Transmit(&huart1, ModbusTxBuf, tx_len, 50u);
+            }
+
+            ModbusRxLen = 0u;                             /* 清空接收缓冲 */
+        }
+
+        /* 重新启动 UART 接收 */
+        USART1_StartRx();
+    }
+}
+
+/*
+*********************************************************************************************************
+*                                      RX 字节接收回调
+*********************************************************************************************************
+*/
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    if (huart->Instance == USART1) {
+        ModbusRxLen++;
+        ModbusRxTick = OSTimeGet();                       /* 记录最后接收时间 */
+
+        if (ModbusRxLen < MODBUS_RX_BUF_SIZE) {
+            HAL_UART_Receive_IT(&huart1, &ModbusRxBuf[ModbusRxLen], 1u);
+        } else {
+            /* 缓冲区溢出，重置 */
+            ModbusRxLen = 0u;
+            HAL_UART_Receive_IT(&huart1, &ModbusRxBuf[0], 1u);
+        }
+    }
+}
+
+/*
+*********************************************************************************************************
+*                                      启动 USART1 接收
+*********************************************************************************************************
+*/
+static void USART1_StartRx(void)
+{
+    ModbusRxLen  = 0u;
+    ModbusRxTick = OSTimeGet();
+    HAL_UART_Receive_IT(&huart1, &ModbusRxBuf[0], 1u);
+}
+
+/*
+*********************************************************************************************************
+*                                        T3.5 超时检测任务
+*
+*  周期性检查接收超时，超时后发送信号量给 Modbus 任务
+*********************************************************************************************************
+*/
+static void App_TaskT35Check(void *p_arg)
+{
+    INT8U os_err;
+
+    (void)p_arg;
+
+    while (1) {
+        OSTimeDly(MODBUS_T35_TIMEOUT);                    /* 每隔 T3.5 时间检查一次 */
+
+        if (ModbusRxLen > 0u) {
+            uint32_t elapsed = OSTimeGet() - ModbusRxTick;
+
+            /* 如果超过 T3.5 没有收到新数据，认为帧结束 */
+            if (elapsed >= MODBUS_T35_TIMEOUT) {
+                OSSemPost(ModbusSem);                     /* 通知 Modbus 任务处理 */
+            }
+        }
+    }
+}
+
+/*
+*********************************************************************************************************
+*                                        STARTUP TASK
+*********************************************************************************************************
+*/
+static void App_TaskStart(void *p_arg)
+{
+    (void)p_arg;
+
+    /* 创建信号量 (初始计数值 = 0) */
+    ModbusSem = OSSemCreate(0u);
+
+    /* 创建 LED 闪烁任务 */
+    OSTaskCreateExt(App_TaskLed,
+                    (void *)0,
+                    (OS_STK *)&App_TaskLedStk[APP_TASK_LED_STK_SIZE - 1u],
+                    APP_TASK_LED_PRIO,
+                    APP_TASK_LED_PRIO,
+                    (OS_STK *)&App_TaskLedStk[0],
+                    APP_TASK_LED_STK_SIZE,
+                    (void *)0,
+                    OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
+
+    /* 创建 Modbus 从站处理任务 */
+    OSTaskCreateExt(App_TaskModbus,
+                    (void *)0,
+                    (OS_STK *)&App_TaskModbusStk[255u],
+                    APP_TASK_MODBUS_PRIO,
+                    APP_TASK_MODBUS_PRIO,
+                    (OS_STK *)&App_TaskModbusStk[0],
+                    256u,
+                    (void *)0,
+                    OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
+
+    /* T3.5 超时检测任务 */
+    OSTaskCreateExt(App_TaskT35Check,
+                    (void *)0,
+                    (OS_STK *)&App_TaskT35CheckStk[127u],
+                    APP_TASK_MODBUS_PRIO + 1u,
+                    APP_TASK_MODBUS_PRIO + 1u,
+                    (OS_STK *)&App_TaskT35CheckStk[0],
+                    128u,
+                    (void *)0,
+                    OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
+
+    /* 挂起自身 */
+    while (1) {
+        OSTaskSuspend(OS_PRIO_SELF);
+    }
+}
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();    /* 初始化 Modbus 通信串口 (USART1, 9600-8-N-1) */
+  /* USER CODE BEGIN 2 */
+
+  /* uC/OS-II 初始化 */
+  OSInit();
+
+  /* 创建启动任务 */
+  OSTaskCreateExt(App_TaskStart,
+                  (void *)0,
+                  (OS_STK *)&App_TaskStartStk[APP_TASK_START_STK_SIZE - 1u],
+                  APP_TASK_START_PRIO,
+                  APP_TASK_START_PRIO,
+                  (OS_STK *)&App_TaskStartStk[0],
+                  APP_TASK_START_STK_SIZE,
+                  (void *)0,
+                  OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);
+
+  /* 启动 uC/OS-II 多任务调度 */
+  OSStart();
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+
+  /*Configure GPIO pin : PF6 */
+  GPIO_InitStruct.Pin = GPIO_PIN_6;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/*
+*********************************************************************************************************
+*                                       USART1 初始化
+*********************************************************************************************************
+*/
+static void MX_USART1_UART_Init(void)
+{
+    huart1.Instance          = USART1;
+    huart1.Init.BaudRate     = 9600u;
+    huart1.Init.WordLength   = UART_WORDLENGTH_8B;
+    huart1.Init.StopBits     = UART_STOPBITS_1;
+    huart1.Init.Parity       = UART_PARITY_NONE;
+    huart1.Init.Mode         = UART_MODE_TX_RX;
+    huart1.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
+    huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+    HAL_UART_Init(&huart1);
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Src/stm32f4xx_hal_msp.c

@@ -0,0 +1,119 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32f4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/*
+*********************************************************************************************************
+*                                       USART1 MSP 初始化
+*********************************************************************************************************
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+    GPIO_InitTypeDef  GPIO_InitStruct = {0};
+
+    if (huart->Instance == USART1) {
+        /* 使能 USART1 和 GPIOA 时钟 */
+        __HAL_RCC_USART1_CLK_ENABLE();
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+
+        /* PA9: USART1_TX (AF7, Push-Pull) */
+        GPIO_InitStruct.Pin       = GPIO_PIN_9;
+        GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+        GPIO_InitStruct.Pull      = GPIO_PULLUP;
+        GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_LOW;
+        GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        /* PA10: USART1_RX (AF7, Input) */
+        GPIO_InitStruct.Pin       = GPIO_PIN_10;
+        GPIO_InitStruct.Mode      = GPIO_MODE_AF_OD;
+        GPIO_InitStruct.Pull      = GPIO_PULLUP;
+        GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        /* 使能 USART1 中断 */
+        HAL_NVIC_SetPriority(USART1_IRQn, 6u, 0u);
+        HAL_NVIC_EnableIRQ(USART1_IRQn);
+    }
+}
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Src/stm32f4xx_it.c

@@ -0,0 +1,216 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2026 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <ucos_ii.h>
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  if (OSRunning == OS_TRUE) {
+    OSIntEnter();
+    OSTimeTick();
+    OSIntExit();
+  }
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f4xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+void USART1_IRQHandler(void)
+{
+    HAL_UART_IRQHandler(&huart1);
+}
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Core/Src/system_stm32f4xx.c

@@ -0,0 +1,749 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+          STM32F479xx */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+                                                     This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
+                                                     This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+  
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+  (void)(tmp); 
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+      clock */
+  RCC->AHB1ENR |= 0x0000007D;
+#else
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+#if defined(STM32F446xx)
+  /* Connect PAx pins to FMC Alternate function */
+  GPIOA->AFR[0]  |= 0xC0000000;
+  GPIOA->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOA->MODER   |= 0x00008000;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOA->OSPEEDR |= 0x00008000;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOA->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOA->PUPDR   |= 0x00000000;
+
+  /* Connect PCx pins to FMC Alternate function */
+  GPIOC->AFR[0]  |= 0x00CC0000;
+  GPIOC->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOC->MODER   |= 0x00000A00;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOC->OSPEEDR |= 0x00000A00;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOC->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOC->PUPDR   |= 0x00000000;
+#endif /* STM32F446xx */
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else  
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x00044014;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else    
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
+  (void)(tmp); 
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Drivers/CMSIS/Core/Include/cmsis_armcc.h

@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Drivers/CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Drivers/CMSIS/Core/Include/cmsis_iccarm.h

@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

Drivers/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

Drivers/CMSIS/Core/Include/core_cm0.h

@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/core_cm1.h

@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Drivers/CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

Drivers/CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

Drivers/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c

@@ -0,0 +1,58 @@
+/******************************************************************************
+ * @file     main_s.c
+ * @brief    Code template for secure main function
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Use CMSE intrinsics */
+#include <arm_cmse.h>
+ 
+#include "RTE_Components.h"
+#include CMSIS_device_header
+ 
+/* TZ_START_NS: Start address of non-secure application */
+#ifndef TZ_START_NS
+#define TZ_START_NS (0x200000U)
+#endif
+ 
+/* typedef for non-secure callback functions */
+typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
+ 
+/* Secure main() */
+int main(void) {
+  funcptr_void NonSecure_ResetHandler;
+ 
+  /* Add user setup code for secure part here*/
+ 
+  /* Set non-secure main stack (MSP_NS) */
+  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
+ 
+  /* Get non-secure reset handler */
+  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
+ 
+  /* Start non-secure state software application */
+  NonSecure_ResetHandler();
+ 
+  /* Non-secure software does not return, this code is not executed */
+  while (1) {
+    __NOP();
+  }
+}

Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c

@@ -0,0 +1,200 @@
+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "tz_context.h"
+
+/// Number of process slots (threads may call secure library code)
+#ifndef TZ_PROCESS_STACK_SLOTS
+#define TZ_PROCESS_STACK_SLOTS     8U
+#endif
+
+/// Stack size of the secure library code
+#ifndef TZ_PROCESS_STACK_SIZE
+#define TZ_PROCESS_STACK_SIZE      256U
+#endif
+
+typedef struct {
+  uint32_t sp_top;      // stack space top
+  uint32_t sp_limit;    // stack space limit
+  uint32_t sp;          // current stack pointer
+} stack_info_t;
+
+static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
+static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
+static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
+
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_InitContextSystem_S (void) {
+  uint32_t n;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
+    ProcessStackInfo[n].sp = 0U;
+    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
+    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
+    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
+  }
+  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
+
+  ProcessStackFreeSlot = 0U;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  // Privileged Thread Mode using PSP
+  __set_CONTROL(0x02U);
+
+  return 1U;    // Success
+}
+
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+__attribute__((cmse_nonsecure_entry))
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
+  uint32_t slot;
+
+  (void)module; // Ignore (fixed Stack size)
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
+    return 0U;  // No slot available
+  }
+
+  slot = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
+
+  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
+
+  return (slot + 1U);
+}
+
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if (__get_IPSR() == 0U) {
+    return 0U;  // Thread Mode
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+  ProcessStackInfo[slot].sp = 0U;
+
+  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
+  ProcessStackFreeSlot = slot;
+
+  return 1U;    // Success
+}
+
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  // Setup process stack pointer and stack limit
+  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
+  __set_PSP   (ProcessStackInfo[slot].sp);
+
+  return 1U;    // Success
+}
+
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+__attribute__((cmse_nonsecure_entry))
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
+  uint32_t slot;
+  uint32_t sp;
+
+  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
+    return 0U;  // Thread Mode or using Main Stack for threads
+  }
+
+  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
+    return 0U;  // Invalid ID
+  }
+
+  slot = id - 1U;
+
+  if (ProcessStackInfo[slot].sp == 0U) {
+    return 0U;  // Inactive slot
+  }
+
+  sp = __get_PSP();
+  if ((sp < ProcessStackInfo[slot].sp_limit) ||
+      (sp > ProcessStackInfo[slot].sp_top)) {
+    return 0U;  // SP out of range
+  }
+  ProcessStackInfo[slot].sp = sp;
+
+  // Default process stack pointer and stack limit
+  __set_PSPLIM((uint32_t)ProcessStackMemory);
+  __set_PSP   ((uint32_t)ProcessStackMemory);
+
+  return 1U;    // Success
+}

Drivers/CMSIS/Core_A/Include/cmsis_armcc.h

@@ -0,0 +1,544 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
+  #define __ARM_ARCH_7A__           1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __forceinline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                     __breakpoint(value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR (Floating Point Status/Control)
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+/**
+  \brief   Set FPSCR (Floating Point Status/Control)
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+/** \brief  Get CPSR (Current Program Status Register)
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+
+/** \brief  Set CPSR (Current Program Status Register)
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  __regCPSR = cpsr;
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_INLINE uint32_t __get_mode(void)
+{
+  return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
+{
+  MOV  r1, lr
+  MSR  CPSR_C, r0
+  BX   r1
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP(void)
+{
+  MOV  r0, sp
+  BX   lr
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
+{
+  MOV  sp, r0
+  BX   lr
+}
+
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYSStack Pointer
+ */
+__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     R0, SP
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
+{
+  ARM
+  PRESERVE8
+
+  MRS     R1, CPSR
+  CPS     #0x1F       ;no effect in USR mode
+  MOV     SP, R0
+  MSR     CPSR_c, R1  ;no effect in USR mode
+  ISB
+  BX      LR
+}
+
+/** \brief  Get FPEXC (Floating Point Exception Control Register)
+    \return               Floating Point Exception Control Register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC (Floating Point Exception Control Register)
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+#define __get_CP64(cp, op1, Rt, CRm) \
+  do { \
+    uint32_t ltmp, htmp; \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
+  } while(0)
+
+#define __set_CP64(cp, op1, Rt, CRm) \
+  do { \
+    const uint64_t tmp = (Rt); \
+    const uint32_t ltmp = (uint32_t)(tmp); \
+    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
+  } while(0)
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE __ASM void __FPU_Enable(void)
+{
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+
+  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+  ENDIF
+
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+
+#endif /* __CMSIS_ARMCC_H */

Drivers/CMSIS/Core_A/Include/cmsis_armclang.h

@@ -0,0 +1,503 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP                             __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI                             __builtin_arm_wfi
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE                             __builtin_arm_wfe
+
+/**
+  \brief   Send Event
+ */
+#define __SEV                             __builtin_arm_sev
+
+/**
+  \brief   Instruction Synchronization Barrier
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __builtin_arm_dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)   __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT          __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ           (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#define __get_FPSCR      __builtin_arm_get_fpscr
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#define __set_FPSCR      __builtin_arm_set_fpscr
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+	return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP()
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#endif /* __CMSIS_ARMCLANG_H */

Drivers/CMSIS/Core_A/Include/cmsis_compiler.h

@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include "cmsis_iccarm.h"
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __attribute__((aligned(x)))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __attribute__((packed))
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                     __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN               __attribute__((noreturn))
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #define CMSIS_DEPRECATED          __attribute__((deprecated))
+  #endif
+  #ifndef   __USED
+    #define __USED                    __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __attribute__((weak))
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  __packed__
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                     _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                  inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE           static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE      __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   CMSIS_DEPRECATED
+    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
+    #define CMSIS_DEPRECATED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                    __weak
+  #endif
+  #ifndef   __UNALIGNED_UINT32
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                  @packed
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

Drivers/CMSIS/Core_A/Include/cmsis_cp15.h

@@ -0,0 +1,514 @@
+/**************************************************************************//**
+ * @file     cmsis_cp15.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.1
+ * @date     07. Sep 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_CP15_H
+#define __CMSIS_CP15_H
+
+/** \brief  Get ACTLR
+    \return               Auxiliary Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return(result);
+}
+
+/** \brief  Set ACTLR
+    \param [in]    actlr  Auxiliary Control value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
+{
+  __set_CP(15, 0, actlr, 1, 0, 1);
+}
+
+/** \brief  Get CPACR
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 2);
+  return result;
+}
+
+/** \brief  Set CPACR
+    \param [in]    cpacr  Coprocessor Access Control value to set
+ */
+__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
+{
+  __set_CP(15, 0, cpacr, 1, 0, 2);
+}
+
+/** \brief  Get DFSR
+    \return               Data Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 0);
+  return result;
+}
+
+/** \brief  Set DFSR
+    \param [in]    dfsr  Data Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
+{
+  __set_CP(15, 0, dfsr, 5, 0, 0);
+}
+
+/** \brief  Get IFSR
+    \return               Instruction Fault Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 5, 0, 1);
+  return result;
+}
+
+/** \brief  Set IFSR
+    \param [in]    ifsr  Instruction Fault Status value to set
+ */
+__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
+{
+  __set_CP(15, 0, ifsr, 5, 0, 1);
+}
+
+/** \brief  Get ISR
+    \return               Interrupt Status Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ISR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 1, 0);
+  return result;
+}
+
+/** \brief  Get CBAR
+    \return               Configuration Base Address register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 4, result, 15, 0, 0);
+  return result;
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 2, 0, 0);
+  return result;
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
+{
+  __set_CP(15, 0, ttbr0, 2, 0, 0);
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 3, 0, 0);
+  return result;
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
+{
+  __set_CP(15, 0, dacr, 3, 0, 0);
+}
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
+{
+  __set_CP(15, 0, sctlr, 1, 0, 0);
+}
+
+/** \brief  Get SCTLR
+    \return               System Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 0);
+  return result;
+}
+
+/** \brief  Set ACTRL
+    \param [in]    actrl  Auxiliary Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
+{
+  __set_CP(15, 0, actrl, 1, 0, 1);
+}
+
+/** \brief  Get ACTRL
+    \return               Auxiliary Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 1, 0, 1);
+  return result;
+}
+
+/** \brief  Get MPIDR
+
+    This function returns the value of the Multiprocessor Affinity Register.
+
+    \return               Multiprocessor Affinity Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 0, 0, 5);
+  return result;
+}
+
+/** \brief  Get VBAR
+
+    This function returns the value of the Vector Base Address Register.
+
+    \return               Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 0);
+  return result;
+}
+
+/** \brief  Set VBAR
+
+    This function assigns the given value to the Vector Base Address Register.
+
+    \param [in]    vbar  Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
+{
+  __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief  Get MVBAR
+
+    This function returns the value of the Monitor Vector Base Address Register.
+
+    \return               Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 1);
+  return result;
+}
+
+/** \brief  Set MVBAR
+
+    This function assigns the given value to the Monitor Vector Base Address Register.
+
+    \param [in]    mvbar  Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+  __set_CP(15, 0, mvbar, 12, 0, 1);
+}
+
+#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
+    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
+    defined(DOXYGEN)
+
+/** \brief  Set CNTFRQ
+
+  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+  \param [in]    value  CNTFRQ Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 0, 0);
+}
+
+/** \brief  Get CNTFRQ
+
+    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
+
+    \return               CNTFRQ Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 0 , 0);
+  return result;
+}
+
+/** \brief  Set CNTP_TVAL
+
+  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
+
+  \param [in]    value  CNTP_TVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 0);
+}
+
+/** \brief  Get CNTP_TVAL
+
+    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
+
+    \return               CNTP_TVAL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 0);
+  return result;
+}
+
+/** \brief  Get CNTPCT
+
+    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
+
+    \return               CNTPCT Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
+{
+  uint64_t result;
+  __get_CP64(15, 0, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CVAL
+
+  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+  \param [in]    value  CNTP_CVAL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
+{
+  __set_CP64(15, 2, value, 14);
+}
+
+/** \brief  Get CNTP_CVAL
+
+    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
+
+    \return               CNTP_CVAL Register value
+ */
+__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
+{
+  uint64_t result;
+  __get_CP64(15, 2, result, 14);
+  return result;
+}
+
+/** \brief  Set CNTP_CTL
+
+  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
+
+  \param [in]    value  CNTP_CTL Register value to set
+*/
+__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
+{
+  __set_CP(15, 0, value, 14, 2, 1);
+}
+
+/** \brief  Get CNTP_CTL register
+    \return               CNTP_CTL Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 14, 2, 1);
+  return result;
+}
+
+#endif
+
+/** \brief  Set TLBIALL
+
+  TLB Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 8, 7, 0);
+}
+
+/** \brief  Set BPIALL.
+
+  Branch Predictor Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 6);
+}
+
+/** \brief  Set ICIALLU
+
+  Instruction Cache Invalidate All
+ */
+__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 0);
+}
+
+/** \brief  Set DCCMVAC
+
+  Data cache clean
+ */
+__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 10, 1);
+}
+
+/** \brief  Set DCIMVAC
+
+  Data cache invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 6, 1);
+}
+
+/** \brief  Set DCCIMVAC
+
+  Data cache clean and invalidate
+ */
+__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 14, 1);
+}
+
+/** \brief  Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get CSSELR
+    \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 2, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Set CCSIDR
+    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ */
+CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
+  __set_CSSELR(value);
+}
+
+/** \brief  Get CCSIDR
+    \return CCSIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 0);
+  return result;
+}
+
+/** \brief  Get CLIDR
+    \return CLIDR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
+  __get_CP(15, 1, result, 0, 0, 1);
+  return result;
+}
+
+/** \brief  Set DCISW
+ */
+__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 6, 2);
+}
+
+/** \brief  Set DCCSW
+ */
+__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 10, 2);
+}
+
+/** \brief  Set DCCISW
+ */
+__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
+  __set_CP(15, 0, value, 7, 14, 2);
+}
+
+#endif

Drivers/CMSIS/Core_A/Include/cmsis_gcc.h

@@ -0,0 +1,679 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V1.0.2
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE                          __attribute__((always_inline))
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   CMSIS_DEPRECATED
+ #define  CMSIS_DEPRECATED                       __attribute__((deprecated))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+
+/* ##########################  Core Instruction Access  ######################### */
+/**
+  \brief   No Operation
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+/**
+  \brief   Wait For Event
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+/**
+  \brief   Send Event
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
+  return result;
+}
+#endif
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE  uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U) {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+/**
+  \brief   Count leading zeros
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             (uint8_t)__builtin_clz
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE  void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+/* ###########################  Core Function Access  ########################### */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE  void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return Floating Point Status/Control register value
+*/
+__STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_get_fpscr) 
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    return __builtin_arm_get_fpscr();
+  #else
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+  #endif
+  #else
+    return(0U);
+  #endif
+}
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in] fpscr  Floating Point Status/Control value to set
+*/
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  #if __has_builtin(__builtin_arm_set_fpscr)
+  // Re-enable using built-in when GCC has been fixed
+  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+    __builtin_arm_set_fpscr(fpscr);
+  #else
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+  #endif
+  #else
+    (void)fpscr;
+  #endif
+}
+
+/** \brief  Get CPSR Register
+    \return               CPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
+{
+  uint32_t result;
+  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
+  return(result);
+}
+
+/** \brief  Set CPSR Register
+    \param [in]    cpsr  CPSR value to set
+ */
+__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
+{
+__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
+}
+
+/** \brief  Get Mode
+    \return                Processor Mode
+ */
+__STATIC_FORCEINLINE uint32_t __get_mode(void)
+{
+    return (__get_CPSR() & 0x1FU);
+}
+
+/** \brief  Set Mode
+    \param [in]    mode  Mode value to set
+ */
+__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
+{
+  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+}
+
+/** \brief  Get Stack Pointer
+    \return Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
+{
+  uint32_t result;
+  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
+  return result;
+}
+
+/** \brief  Set Stack Pointer
+    \param [in]    stack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
+{
+  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
+}
+
+/** \brief  Get USR/SYS Stack Pointer
+    \return USR/SYS Stack Pointer value
+ */
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr = __get_CPSR();
+  uint32_t result;
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+  return result;
+}
+
+/** \brief  Set USR/SYS Stack Pointer
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr = __get_CPSR();
+  __ASM volatile(
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
+   );
+  __set_CPSR(cpsr);
+  __ISB();
+}
+
+/** \brief  Get FPEXC
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
+  return(result);
+#else
+  return(0);
+#endif
+}
+
+/** \brief  Set FPEXC
+    \param [in]    fpexc  Floating Point Exception Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+#endif
+}
+
+/*
+ * Include common core functions to access Coprocessor 15 registers
+ */
+
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+#include "cmsis_cp15.h"
+
+/** \brief  Enable Floating Point Unit
+
+  Critical section, called from undef handler, so systick is disabled
+ */
+__STATIC_INLINE void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2            "
+  );
+}
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h

@@ -0,0 +1,559 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.6
+ * @date     02. March 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#pragma language=extended
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_7A__
+/* Macro already defined */
+#else
+  #if defined(__ARM7A__)
+    #define __ARM_ARCH_7A__ 1
+  #endif
+#endif
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  /* Needs IAR language extensions */
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef   CMSIS_DEPRECATED
+  #define CMSIS_DEPRECATED      __attribute__((deprecated))
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+  {
+    return *(__packed uint16_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+  {
+    *(__packed uint16_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+  {
+    return *(__packed uint32_t*)(ptr);
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+  #pragma language=save
+  #pragma language=extended
+  __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+  {
+    *(__packed uint32_t*)(ptr) = val;;
+  }
+  #pragma language=restore
+  #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#if 0
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+  #pragma language=save
+  #pragma language=extended
+  __packed struct  __iar_u32 { uint32_t v; };
+  #pragma language=restore
+  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq    __iar_builtin_enable_fiq
+  #define __disable_fault_irq   __iar_builtin_disable_fiq
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+  #if __FPU_PRESENT
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+  #else
+    #define __get_FPSCR()             ( 0 )
+  #endif
+
+  #define __set_FPSCR(VALUE)          (__arm_wsr("FPSCR", VALUE))
+
+  #define __get_CPSR()                (__arm_rsr("CPSR"))
+  #define __get_mode()                (__get_CPSR() & 0x1FU)
+
+  #define __set_CPSR(VALUE)           (__arm_wsr("CPSR", (VALUE)))
+  #define __set_mode(VALUE)           (__arm_wsr("CPSR_c", (VALUE)))
+
+
+  #define __get_FPEXC()       (__arm_rsr("FPEXC"))
+  #define __set_FPEXC(VALUE)    (__arm_wsr("FPEXC", VALUE))
+
+  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+
+  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
+
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #define __SSAT    __iar_builtin_SSAT
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #define __USAT    __iar_builtin_USAT
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #define __SADD8   __iar_builtin_SADD8
+  #define __QADD8   __iar_builtin_QADD8
+  #define __SHADD8  __iar_builtin_SHADD8
+  #define __UADD8   __iar_builtin_UADD8
+  #define __UQADD8  __iar_builtin_UQADD8
+  #define __UHADD8  __iar_builtin_UHADD8
+  #define __SSUB8   __iar_builtin_SSUB8
+  #define __QSUB8   __iar_builtin_QSUB8
+  #define __SHSUB8  __iar_builtin_SHSUB8
+  #define __USUB8   __iar_builtin_USUB8
+  #define __UQSUB8  __iar_builtin_UQSUB8
+  #define __UHSUB8  __iar_builtin_UHSUB8
+  #define __SADD16  __iar_builtin_SADD16
+  #define __QADD16  __iar_builtin_QADD16
+  #define __SHADD16 __iar_builtin_SHADD16
+  #define __UADD16  __iar_builtin_UADD16
+  #define __UQADD16 __iar_builtin_UQADD16
+  #define __UHADD16 __iar_builtin_UHADD16
+  #define __SSUB16  __iar_builtin_SSUB16
+  #define __QSUB16  __iar_builtin_QSUB16
+  #define __SHSUB16 __iar_builtin_SHSUB16
+  #define __USUB16  __iar_builtin_USUB16
+  #define __UQSUB16 __iar_builtin_UQSUB16
+  #define __UHSUB16 __iar_builtin_UHSUB16
+  #define __SASX    __iar_builtin_SASX
+  #define __QASX    __iar_builtin_QASX
+  #define __SHASX   __iar_builtin_SHASX
+  #define __UASX    __iar_builtin_UASX
+  #define __UQASX   __iar_builtin_UQASX
+  #define __UHASX   __iar_builtin_UHASX
+  #define __SSAX    __iar_builtin_SSAX
+  #define __QSAX    __iar_builtin_QSAX
+  #define __SHSAX   __iar_builtin_SHSAX
+  #define __USAX    __iar_builtin_USAX
+  #define __UQSAX   __iar_builtin_UQSAX
+  #define __UHSAX   __iar_builtin_UHSAX
+  #define __USAD8   __iar_builtin_USAD8
+  #define __USADA8  __iar_builtin_USADA8
+  #define __SSAT16  __iar_builtin_SSAT16
+  #define __USAT16  __iar_builtin_USAT16
+  #define __UXTB16  __iar_builtin_UXTB16
+  #define __UXTAB16 __iar_builtin_UXTAB16
+  #define __SXTB16  __iar_builtin_SXTB16
+  #define __SXTAB16 __iar_builtin_SXTAB16
+  #define __SMUAD   __iar_builtin_SMUAD
+  #define __SMUADX  __iar_builtin_SMUADX
+  #define __SMMLA   __iar_builtin_SMMLA
+  #define __SMLAD   __iar_builtin_SMLAD
+  #define __SMLADX  __iar_builtin_SMLADX
+  #define __SMLALD  __iar_builtin_SMLALD
+  #define __SMLALDX __iar_builtin_SMLALDX
+  #define __SMUSD   __iar_builtin_SMUSD
+  #define __SMUSDX  __iar_builtin_SMUSDX
+  #define __SMLSD   __iar_builtin_SMLSD
+  #define __SMLSDX  __iar_builtin_SMLSDX
+  #define __SMLSLD  __iar_builtin_SMLSLD
+  #define __SMLSLDX __iar_builtin_SMLSLDX
+  #define __SEL     __iar_builtin_SEL
+  #define __QADD    __iar_builtin_QADD
+  #define __QSUB    __iar_builtin_QSUB
+  #define __PKHBT   __iar_builtin_PKHBT
+  #define __PKHTB   __iar_builtin_PKHTB
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if !__FPU_PRESENT
+  #define __get_FPSCR() (0)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq        __enable_interrupt
+  #define __disable_irq       __disable_interrupt
+  #define __enable_fault_irq    __enable_fiq
+  #define __disable_fault_irq   __disable_fiq
+  #define __NOP               __no_operation
+
+  #define __get_xPSR          __get_PSR
+
+  __IAR_FT void __set_mode(uint32_t mode)
+  {
+    __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
+  }
+
+  __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+  {
+    return __LDREX((unsigned long *)ptr);
+  }
+
+  __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+  {
+    return __STREX(value, (unsigned long *)ptr);
+  }
+
+
+  __IAR_FT uint32_t __RRX(uint32_t value)
+  {
+    uint32_t result;
+    __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+    return(result);
+  }
+
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  __IAR_FT uint32_t __get_FPEXC(void)
+  {
+  #if (__FPU_PRESENT == 1)
+    uint32_t result;
+    __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
+    return(result);
+  #else
+    return(0);
+  #endif
+  }
+
+  __IAR_FT void __set_FPEXC(uint32_t fpexc)
+  {
+  #if (__FPU_PRESENT == 1)
+    __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
+  #endif
+  }
+
+
+  #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
+  #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
+    __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
+  #define __get_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
+  #define __set_CP64(cp, op1, Rt, CRm) \
+    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
+
+  #include "cmsis_cp15.h"
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+
+__IAR_FT uint32_t __get_SP_usr(void)
+{
+  uint32_t cpsr;
+  uint32_t result;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     %1, sp     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
+   );
+  return result;
+}
+
+__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
+{
+  uint32_t cpsr;
+  __ASM volatile(
+    "MRS     %0, cpsr   \n"
+    "CPS     #0x1F      \n" // no effect in USR mode
+    "MOV     sp, %1     \n"
+    "MSR     cpsr_c, %2 \n" // no effect in USR mode
+    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
+   );
+}
+
+#define __get_mode()                (__get_CPSR() & 0x1FU)
+
+__STATIC_INLINE
+void __FPU_Enable(void)
+{
+  __ASM volatile(
+    //Permit access to VFP/NEON, registers by modifying CPACR
+    "        MRC     p15,0,R1,c1,c0,2  \n"
+    "        ORR     R1,R1,#0x00F00000 \n"
+    "        MCR     p15,0,R1,c1,c0,2  \n"
+
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    "        ISB                       \n"
+
+    //Enable VFP/NEON
+    "        VMRS    R1,FPEXC          \n"
+    "        ORR     R1,R1,#0x40000000 \n"
+    "        VMSR    FPEXC,R1          \n"
+
+    //Initialise VFP/NEON registers to 0
+    "        MOV     R2,#0             \n"
+
+    //Initialise D16 registers to 0
+    "        VMOV    D0, R2,R2         \n"
+    "        VMOV    D1, R2,R2         \n"
+    "        VMOV    D2, R2,R2         \n"
+    "        VMOV    D3, R2,R2         \n"
+    "        VMOV    D4, R2,R2         \n"
+    "        VMOV    D5, R2,R2         \n"
+    "        VMOV    D6, R2,R2         \n"
+    "        VMOV    D7, R2,R2         \n"
+    "        VMOV    D8, R2,R2         \n"
+    "        VMOV    D9, R2,R2         \n"
+    "        VMOV    D10,R2,R2         \n"
+    "        VMOV    D11,R2,R2         \n"
+    "        VMOV    D12,R2,R2         \n"
+    "        VMOV    D13,R2,R2         \n"
+    "        VMOV    D14,R2,R2         \n"
+    "        VMOV    D15,R2,R2         \n"
+
+#ifdef __ARM_ADVANCED_SIMD__
+    //Initialise D32 registers to 0
+    "        VMOV    D16,R2,R2         \n"
+    "        VMOV    D17,R2,R2         \n"
+    "        VMOV    D18,R2,R2         \n"
+    "        VMOV    D19,R2,R2         \n"
+    "        VMOV    D20,R2,R2         \n"
+    "        VMOV    D21,R2,R2         \n"
+    "        VMOV    D22,R2,R2         \n"
+    "        VMOV    D23,R2,R2         \n"
+    "        VMOV    D24,R2,R2         \n"
+    "        VMOV    D25,R2,R2         \n"
+    "        VMOV    D26,R2,R2         \n"
+    "        VMOV    D27,R2,R2         \n"
+    "        VMOV    D28,R2,R2         \n"
+    "        VMOV    D29,R2,R2         \n"
+    "        VMOV    D30,R2,R2         \n"
+    "        VMOV    D31,R2,R2         \n"
+#endif
+
+    //Initialise FPSCR to a known state
+    "        VMRS    R2,FPSCR          \n"
+    "        MOV32   R3,#0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+    "        AND     R2,R2,R3          \n"
+    "        VMSR    FPSCR,R2          \n");
+}
+
+
+
+#undef __IAR_FT
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

Drivers/CMSIS/Core_A/Include/irq_ctrl.h

@@ -0,0 +1,186 @@
+/**************************************************************************//**
+ * @file     irq_ctrl.h
+ * @brief    Interrupt Controller API header file
+ * @version  V1.0.0
+ * @date     23. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef IRQ_CTRL_H_
+#define IRQ_CTRL_H_
+
+#include <stdint.h>
+
+#ifndef IRQHANDLER_T
+#define IRQHANDLER_T
+/// Interrupt handler data type
+typedef void (*IRQHandler_t) (void);
+#endif
+
+#ifndef IRQN_ID_T
+#define IRQN_ID_T
+/// Interrupt ID number data type
+typedef int32_t IRQn_ID_t;
+#endif
+
+/* Interrupt mode bit-masks */
+#define IRQ_MODE_TRIG_Pos           (0U)
+#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
+#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
+#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
+#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
+
+#define IRQ_MODE_TYPE_Pos           (3U)
+#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)
+#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line
+#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line
+
+#define IRQ_MODE_DOMAIN_Pos         (4U)
+#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)
+#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain
+#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain
+
+#define IRQ_MODE_CPU_Pos            (5U)
+#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)
+#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs
+#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0
+#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1
+#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2
+#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3
+#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4
+#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5
+#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6
+#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7
+
+#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error
+
+/* Interrupt priority bit-masks */
+#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask
+#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error
+
+/// Initialize interrupt controller.
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Initialize (void);
+
+/// Register interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     handler       interrupt handler function address
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
+
+/// Get the registered interrupt handler.
+/// \param[in]     irqn          interrupt ID number
+/// \return registered interrupt handler function address.
+IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
+
+/// Enable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Enable (IRQn_ID_t irqn);
+
+/// Disable interrupt.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_Disable (IRQn_ID_t irqn);
+
+/// Get interrupt enable state.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
+uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
+
+/// Configure interrupt request mode.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     mode          mode configuration
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
+
+/// Get interrupt mode configuration.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+uint32_t IRQ_GetMode (IRQn_ID_t irqn);
+
+/// Get ID number of current interrupt request (IRQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveIRQ (void);
+
+/// Get ID number of current fast interrupt request (FIQ).
+/// \return interrupt ID number.
+IRQn_ID_t IRQ_GetActiveFIQ (void);
+
+/// Signal end of interrupt processing.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
+
+/// Set interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPending (IRQn_ID_t irqn);
+
+/// Get interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
+uint32_t IRQ_GetPending (IRQn_ID_t irqn);
+
+/// Clear interrupt pending flag.
+/// \param[in]     irqn          interrupt ID number
+/// \return 0 on success, -1 on error.
+int32_t IRQ_ClearPending (IRQn_ID_t irqn);
+
+/// Set interrupt priority value.
+/// \param[in]     irqn          interrupt ID number
+/// \param[in]     priority      interrupt priority value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
+
+/// Get interrupt priority.
+/// \param[in]     irqn          interrupt ID number
+/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
+
+/// Set priority masking threshold.
+/// \param[in]     priority      priority masking threshold value
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityMask (uint32_t priority);
+
+/// Get priority masking threshold
+/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityMask (void);
+
+/// Set priority grouping field split point
+/// \param[in]     bits          number of MSB bits included in the group priority field comparison
+/// \return 0 on success, -1 on error.
+int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
+
+/// Get priority grouping field split point
+/// \return current number of MSB bits included in the group priority field comparison with
+///         optional IRQ_PRIORITY_ERROR bit set.
+uint32_t IRQ_GetPriorityGroupBits (void);
+
+#endif  // IRQ_CTRL_H_

Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c

@@ -0,0 +1,410 @@
+/**************************************************************************//**
+ * @file     irq_ctrl_gic.c
+ * @brief    Interrupt controller handling implementation for GIC
+ * @version  V1.0.1
+ * @date     9. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#include "irq_ctrl.h"
+
+#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
+
+/// Number of implemented interrupt lines
+#ifndef IRQ_GIC_LINE_COUNT
+#define IRQ_GIC_LINE_COUNT      (1020U)
+#endif
+
+static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+static uint32_t     IRQ_ID0;
+
+/// Initialize interrupt controller.
+__WEAK int32_t IRQ_Initialize (void) {
+  uint32_t i;
+
+  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+    IRQTable[i] = (IRQHandler_t)NULL;
+  }
+  GIC_Enable();
+  return (0);
+}
+
+
+/// Register interrupt handler.
+__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    IRQTable[irqn] = handler;
+    status =  0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get the registered interrupt handler.
+__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+  IRQHandler_t h;
+
+  // Ignore CPUID field (software generated interrupts)
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    h = IRQTable[irqn];
+  } else {
+    h = (IRQHandler_t)0;
+  }
+
+  return (h);
+}
+
+
+/// Enable interrupt.
+__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EnableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Disable interrupt.
+__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_DisableIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt enable state.
+__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+  uint32_t enable;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+  } else {
+    enable = 0U;
+  }
+
+  return (enable);
+}
+
+
+/// Configure interrupt request mode.
+__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+  uint32_t val;
+  uint8_t cfg;
+  uint8_t secure;
+  uint8_t cpu;
+  int32_t status = 0;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    // Check triggering mode
+    val = (mode & IRQ_MODE_TRIG_Msk);
+
+    if (val == IRQ_MODE_TRIG_LEVEL) {
+      cfg = 0x00U;
+    } else if (val == IRQ_MODE_TRIG_EDGE) {
+      cfg = 0x02U;
+    } else {
+      cfg = 0x00U;
+      status = -1;
+    }
+
+    // Check interrupt type
+    val = mode & IRQ_MODE_TYPE_Msk;
+
+    if (val != IRQ_MODE_TYPE_IRQ) {
+      status = -1;
+    }
+
+    // Check interrupt domain
+    val = mode & IRQ_MODE_DOMAIN_Msk;
+
+    if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+      secure = 0U;
+    } else {
+      // Check security extensions support
+      val = GIC_DistributorInfo() & (1UL << 10U);
+
+      if (val != 0U) {
+        // Security extensions are supported
+        secure = 1U;
+      } else {
+        secure = 0U;
+        status = -1;
+      }
+    }
+
+    // Check interrupt CPU targets
+    val = mode & IRQ_MODE_CPU_Msk;
+
+    if (val == IRQ_MODE_CPU_ALL) {
+      cpu = 0xFFU;
+    } else {
+      cpu = val >> IRQ_MODE_CPU_Pos;
+    }
+
+    // Apply configuration if no mode error
+    if (status == 0) {
+      GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+      GIC_SetTarget       ((IRQn_Type)irqn, cpu);
+
+      if (secure != 0U) {
+        GIC_SetGroup ((IRQn_Type)irqn, secure);
+      }
+    }
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt mode configuration.
+__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+  uint32_t mode;
+  uint32_t val;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    mode = IRQ_MODE_TYPE_IRQ;
+
+    // Get trigger mode
+    val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+    if ((val & 2U) != 0U) {
+      // Corresponding interrupt is edge triggered
+      mode |= IRQ_MODE_TRIG_EDGE;
+    } else {
+      // Corresponding interrupt is level triggered
+      mode |= IRQ_MODE_TRIG_LEVEL;
+    }
+
+    // Get interrupt CPU targets
+    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+  } else {
+    mode = IRQ_MODE_ERROR;
+  }
+
+  return (mode);
+}
+
+
+/// Get ID number of current interrupt request (IRQ).
+__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
+  IRQn_ID_t irqn;
+  uint32_t prio;
+
+  /* Dummy read to avoid GIC 390 errata 801120 */
+  GIC_GetHighPendingIRQ();
+
+  irqn = GIC_AcknowledgePending();
+
+  __DSB();
+
+  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */
+  /* The following workaround code is for a single-core system.  It would be       */
+  /* different in a multi-core system.                                             */
+  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
+  /* so unlock it, otherwise service the interrupt as normal.                      */
+  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */
+  /* so will not occur here.                                                       */
+
+  if ((irqn == 0) || (irqn >= 0x3FE)) {
+    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
+    prio = GIC_GetPriority((IRQn_Type)0);
+    GIC_SetPriority ((IRQn_Type)0, prio);
+
+    __DSB();
+
+    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
+      /* If the ID is 0, is active and has not been seen before */
+      IRQ_ID0 = 1U;
+    }
+    /* End of Workaround GIC 390 errata 733075 */
+  }
+
+  return (irqn);
+}
+
+
+/// Get ID number of current fast interrupt request (FIQ).
+__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
+  return ((IRQn_ID_t)-1);
+}
+
+
+/// Signal end of interrupt processing.
+__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+  int32_t status;
+  IRQn_Type irq = (IRQn_Type)irqn;
+
+  irqn &= 0x3FFU;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_EndInterrupt (irq);
+
+    if (irqn == 0) {
+      IRQ_ID0 = 0U;
+    }
+
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt pending flag.
+__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+/// Get interrupt pending flag.
+__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+  uint32_t pending;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+  } else {
+    pending = 0U;
+  }
+
+  return (pending & 1U);
+}
+
+
+/// Clear interrupt pending flag.
+__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+  int32_t status;
+
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Set interrupt priority value.
+__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+  int32_t status;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    GIC_SetPriority ((IRQn_Type)irqn, priority);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get interrupt priority.
+__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+  uint32_t priority;
+
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
+    priority = GIC_GetPriority ((IRQn_Type)irqn);
+  } else {
+    priority = IRQ_PRIORITY_ERROR;
+  }
+
+  return (priority);
+}
+
+
+/// Set priority masking threshold.
+__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
+  GIC_SetInterfacePriorityMask (priority);
+  return (0);
+}
+
+
+/// Get priority masking threshold
+__WEAK uint32_t IRQ_GetPriorityMask (void) {
+  return GIC_GetInterfacePriorityMask();
+}
+
+
+/// Set priority grouping field split point
+__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+  int32_t status;
+
+  if (bits == IRQ_PRIORITY_Msk) {
+    bits = 7U;
+  }
+
+  if (bits < 8U) {
+    GIC_SetBinaryPoint (7U - bits);
+    status = 0;
+  } else {
+    status = -1;
+  }
+
+  return (status);
+}
+
+
+/// Get priority grouping field split point
+__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
+  uint32_t bp;
+
+  bp = GIC_GetBinaryPoint() & 0x07U;
+
+  return (7U - bp);
+}
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/arr_desc/arr_desc.h

@@ -0,0 +1,220 @@
+#ifndef _ARR_DESC_H_
+#define _ARR_DESC_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include <stdint.h>
+#include <string.h>             /* memset() */
+#include "../util/util.h"       /* CONCAT() */
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Array-descriptor struct.
+ */
+typedef struct ARR_DESC_struct
+{
+    void *  data_ptr;                /* Pointer to the array contents. */
+    int32_t element_count;           /* Number of current elements. */
+    int32_t element_size;            /* Size of current elements in bytes. */
+    int32_t underlying_size;         /* Size of underlying array in bytes. */
+} ARR_DESC_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix of the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_PREFIX ARR_DESC_ARR_
+
+/**
+ *  Evaluate to the array variable's name when creating an array and an array
+ *  descriptor at the same time.
+ */
+#define ARR_DESC_ARR_NAME(name)                 \
+    CONCAT(ARR_DESC_ARR_PREFIX, name)
+
+/**
+ *  Define an #ARR_DESC_t by itself.
+ *
+ *  @note The user must supply an array to store the data used by the
+ *  #ARR_DESC_t.
+ */
+#define ARR_DESC_INTERNAL_DEFINE(name, data_ptr,                \
+                                 element_count, element_size)   \
+    ARR_DESC_t name = {                                         \
+        data_ptr,                                               \
+        element_count,                                          \
+        element_size,                                           \
+        element_count * element_size                            \
+    }                                                           \
+
+/**
+ *  Define both an array and an #ARR_DESC_t that describes it.
+ *
+ *  @note Use the #CURLY() macro for the content field; it provides the curly
+ *  braces necessary for an array initialization.
+ */
+#define ARR_DESC_DEFINE(type, name, element_count, content)             \
+    type ARR_DESC_ARR_NAME(name)[element_count] = content;              \
+    ARR_DESC_INTERNAL_DEFINE(name,                                      \
+                             &ARR_DESC_ARR_NAME(name),                  \
+                             element_count,                             \
+                             sizeof(type)) /* Note the lacking semicolon */
+
+/**
+ *  Create a #ARR_DESC_t which refers to a subset of the data in another.
+ *
+ *  The new #ARR_DESC_t shares the same underlying array as the aliased
+ *  #ARR_DESC_t, but only describes a subset of the originals values.
+ */
+#define ARR_DESC_DEFINE_SUBSET(name, original, element_cnt)         \
+    ARR_DESC_INTERNAL_DEFINE(name,                                  \
+                             &ARR_DESC_ARR_NAME(original),          \
+                             element_cnt,                           \
+                             sizeof(ARR_DESC_ARR_NAME(original)[0]) \
+        ) /* Note the lacking semicolon */
+
+/**
+ *  Creat an #ARR_DESC_t which points to the data in an existing array.
+ *
+ *  @param start_idx Offset in array_ptr of first element.
+ *  @param element_cnt Number of elements to include in the #ARR_DESC_t.
+ *
+ *  @example
+ *
+ *  float my_floats[4] = {0.0f, 1.0f, 2.0f, 3.0f};
+ *
+ *  ARR_DESC_DEFINE_USING_ARR(my_arr_desc, my_floats, 1, 3);
+ *
+ *  printf("Element 0: %f\n", ARR_DESC_ELT(float, 0, &my_arr_desc));
+ *  printf("Element 1: %f\n", ARR_DESC_ELT(float, 1, &my_arr_desc));
+ *
+ *  Outputs:
+ *
+ *  Element 0: 1.000000
+ *  Element 1: 2.000000
+ *
+ *  @warning There are no checks in place to catch invalid start indices; This
+ *  is left to the user.
+ */
+#define ARR_DESC_DEFINE_USING_ARR(type, name, array_ptr, start_idx, element_cnt) \
+    ARR_DESC_INTERNAL_DEFINE(                                           \
+        name,                                                           \
+        (type *) (array_ptr + start_idx),                               \
+        element_cnt,                                                    \
+        sizeof(type)                                                    \
+        ) /* Note the lacking semicolon*/
+
+/**
+ *  Declare an #ARR_DESC_t object.
+ */
+#define ARR_DESC_DECLARE(name)                              \
+    extern ARR_DESC_t name /* Note the lacking semicolon */
+
+/**
+ *  Evaluate to the number of bytes stored in the #ARR_DESC_t.
+ */
+#define ARR_DESC_BYTES(arr_desc_ptr)                                \
+    ((arr_desc_ptr)->element_count * (arr_desc_ptr)->element_size)
+
+/**
+ *  Set the contents of #ARR_DESC_t to value.
+ */
+#define ARR_DESC_MEMSET(arr_desc_ptr, value, bytes)     \
+    do                                                  \
+    {                                                   \
+        memset((arr_desc_ptr)->data_ptr,                \
+               value,                                   \
+               BOUND(0,                                 \
+                     (arr_desc_ptr)->underlying_size,   \
+                     bytes)                             \
+            );                                          \
+    } while (0)
+
+/**
+ *  Perform a memcpy of 'bytes' bytes from the source #ARR_DESC_t to the
+ *  destination #ARR_DESC_t.
+ */
+#define ARR_DESC_MEMCPY(arr_desc_dest_ptr, arr_desc_src_ptr, bytes) \
+    do                                                              \
+    {                                                               \
+        memcpy((arr_desc_dest_ptr)->data_ptr,                       \
+               (arr_desc_src_ptr)->data_ptr,                        \
+               BOUND(0,                                             \
+                     (arr_desc_dest_ptr)->underlying_size,          \
+                     bytes));                                       \
+    } while (0)
+
+/**
+ *  Evaluate to true if the source #ARR_DESC_t contents will fit into the
+ *  destination #ARR_DESC_t and false otherwise.
+ */
+#define ARR_DESC_COPYABLE(arr_desc_dest_ptr, arr_desc_src_ptr)  \
+      (ARR_DESC_BYTES(arr_desc_src_ptr) <=                      \
+       (arr_desc_dest_ptr)->underlying_size)
+
+/**
+ *  Copy all the data from the source #ARR_DESC_t to the destination
+ *  #ARR_DESC_t.
+ *
+ *  @note If the destination #ARR_DESC_t is too small to fit the source data the
+ *  copy is aborted and nothing happens.
+ */
+#define ARR_DESC_COPY(arr_desc_dest_ptr, arr_desc_src_ptr)      \
+    do                                                          \
+    {                                                           \
+        if (ARR_DESC_COPYABLE(arr_desc_dest_ptr,                 \
+                             arr_desc_src_ptr))                 \
+        {                                                       \
+            ARR_DESC_MEMCPY(arr_desc_dest_ptr,                  \
+                            arr_desc_src_ptr,                   \
+                            ARR_DESC_BYTES(arr_desc_src_ptr));  \
+            /* Update the properties*/                          \
+            (arr_desc_dest_ptr)->element_count =                \
+                (arr_desc_src_ptr)->element_count;              \
+            (arr_desc_dest_ptr)->element_size =                 \
+                (arr_desc_src_ptr)->element_size;               \
+        }                                                       \
+    } while (0)
+
+/**
+ *  Compare the data in two #ARR_DESC_t structs for the specified number of
+ *  bytes.
+ */
+#define ARR_DESC_MEMCMP(arr_desc_ptr_a, arr_desc_ptr_b, bytes)  \
+        memcmp((arr_desc_ptr_a)->data_ptr,                      \
+            (arr_desc_ptr_b)->data_ptr,                         \
+               bytes) /* Note the lacking semicolon */          \
+
+/**
+ *  Zero out the contents of the #ARR_DESC_t.
+ */
+#define ARR_DESC_ZERO(arr_desc_ptr)             \
+        ARR_DESC_MEMSET(arr_desc_ptr,           \
+                        0,                      \
+                        (arr_desc_ptr)->underlying_size)
+
+/**
+ *  Evaluate to the data address in #ARR_DESC_t at offset.
+ */
+#define ARR_DESC_DATA_ADDR(type, arr_desc_ptr, offset)  \
+        ((void*)(((type *)                              \
+                  ((arr_desc_ptr)->data_ptr))           \
+                 + offset))
+
+/**
+ *  Evaluate to the element in #ARR_DESC_t with type at idx.
+ */
+#define ARR_DESC_ELT(type, idx, arr_desc_ptr)           \
+        (*((type *) ARR_DESC_DATA_ADDR(type,            \
+                                       arr_desc_ptr,    \
+                                       idx)))
+
+#endif /* _ARR_DESC_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest.h

@@ -0,0 +1,17 @@
+#ifndef _JTEST_H_
+#define _JTEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_test_call.h"
+#include "jtest_group.h"
+#include "jtest_group_define.h"
+#include "jtest_group_call.h"
+#include "jtest_cycle.h"
+
+#endif /* _JTEST_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_cycle.h

@@ -0,0 +1,65 @@
+#ifndef _JTEST_CYCLE_H_
+#define _JTEST_CYCLE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"           /* JTEST_DUMP_STRF() */
+#include "jtest_systick.h"
+#include "jtest_util.h"         /* STR() */
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Module Variables */
+/*--------------------------------------------------------------------------------*/
+extern const char * JTEST_CYCLE_STRF;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Wrap the function call, fn_call, to count execution cycles and display the
+ *  results.
+ */
+/* skipp function name + param
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        STR(fn_call),                   \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+*/
+#define JTEST_COUNT_CYCLES(fn_call)                     \
+    do                                                  \
+    {                                                   \
+        uint32_t __jtest_cycle_end_count;               \
+                                                        \
+        JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_SYSTICK_START(SysTick);                   \
+                                                        \
+        fn_call;                                        \
+                                                        \
+        __jtest_cycle_end_count =                       \
+            JTEST_SYSTICK_VALUE(SysTick);               \
+                                                        \
+		JTEST_SYSTICK_RESET(SysTick);                   \
+        JTEST_DUMP_STRF(JTEST_CYCLE_STRF,               \
+                        (JTEST_SYSTICK_INITIAL_VALUE -  \
+                         __jtest_cycle_end_count));     \
+    } while (0)
+
+#endif /* _JTEST_CYCLE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_define.h

@@ -0,0 +1,37 @@
+#ifndef _JTEST_DEFINE_H_
+#define _JTEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Makes a symbol for use as a struct name. Names made this way have two parts;
+ *  the first parts is a prefix common to all structs of that class. The second
+ *  is a specifier which differs for each instance of that struct type.
+ */
+#define JTEST_STRUCT_NAME(prefix, specifier)    \
+    CONCAT(prefix, specifier)
+
+/**
+ *  Define a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DEFINE_STRUCT(type, struct_name)    \
+    type struct_name
+
+/**
+ *  Declare a struct with type with a name generated by #JTEST_STRUCT_NAME().
+ */
+#define JTEST_DECLARE_STRUCT(struct_definition) \
+    extern struct_definition
+
+/**
+ *  Define and initialize a struct (created with JTEST_DEFINE_STRUCT()) and
+ *  initialize it with init_values.
+ */
+#define JTEST_INIT_STRUCT(struct_definition, init_values)       \
+    struct_definition = {                                       \
+        init_values                                             \
+    }
+
+#endif /* _JTEST_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_fw.h

@@ -0,0 +1,253 @@
+#ifndef _JTEST_FW_H_
+#define _JTEST_FW_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>             /* int32_t */
+#include <string.h>             /* strcpy() */
+#include <stdio.h>              /* sprintf() */
+#include "jtest_pf.h"           /* Extend JTEST_FW_t with Pass/Fail data */
+#include "jtest_group.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct used to interface with the Keil Debugger.
+ */
+typedef struct JTEST_FW_struct
+{
+    /* Action Triggers: The Keil debugger monitors these values for changes.  In
+     * response to a change, the debugger executes code on the host. */
+    volatile int32_t test_start;
+    volatile int32_t test_end;
+    volatile int32_t group_start;
+    volatile int32_t group_end;
+    volatile int32_t dump_str;
+    volatile int32_t dump_data;
+    volatile int32_t exit_fw;
+
+    JTEST_GROUP_t * current_group_ptr;
+
+    /* Buffers: The C-code cannot send strings and data directly to the
+     * debugging framework. Instead, the debugger can be told to read 128 byte
+     * (by default) chunks of memory.  Data received in this manner requires
+     * post-processing to be legible.*/
+    char * str_buffer;
+    char * data_buffer;
+
+    /* Pass/Fail Data */
+    JTEST_PF_MEMBERS;
+
+} JTEST_FW_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Default name for the JTEST_FW struct.
+ *
+ *  Define your own if you want the variable containing the #JTEST_FW_t to have
+ *  a different name.
+ */
+#ifndef JTEST_FW
+#define JTEST_FW JTEST_FW
+#endif
+
+/**
+ *  Default name for the JTEST_FW_STR_BUFFER.
+ *
+ *  Define your own if you want the variable containing the char buffer to have
+ *  a different name.
+ */
+#ifndef JTEST_FW_STR_BUFFER
+#define JTEST_FW_STR_BUFFER JTEST_FW_STR_BUFFER
+#endif
+
+/**
+ *  Size of the #JTEST_FW_t, output string-buffer.
+ *
+ *  If you change this value, make sure the "dump_str_fn" and "dump_data_fn"
+ *  functions in jtest_fns.ini uses the same size. If you aren't sure, read the
+ *  documentation Keil Debugger Command 'DISPLAY'.
+ */
+#define JTEST_BUF_SIZE 256
+
+
+/**
+ *  The maximum number of bytes output at once using #JTEST_DUMP_STRF().
+ */
+#define JTEST_STR_MAX_OUTPUT_SIZE 128
+
+/**
+ *  The maximum number of block transimissions needed to send a string from a
+ *  buffer with JTEST_BUF_SIZE.
+ */
+#define JTEST_STR_MAX_OUTPUT_SEGMENTS           \
+    (JTEST_BUF_SIZE / JTEST_STR_MAX_OUTPUT_SIZE)
+
+/**
+ *  Initialize the JTEST framework.
+ */
+#define JTEST_INIT()                                                    \
+    do                                                                  \
+    {                                                                   \
+        JTEST_FW.str_buffer = JTEST_FW_STR_BUFFER;                      \
+    } while (0)
+
+/* Debugger Action-triggering Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro to trigger various actions in the Keil Debugger.
+ */
+#define JTEST_TRIGGER_ACTION(action_name)       \
+    do                                          \
+    {                                           \
+        action_name();                          \
+    } while (0)
+
+/**
+ *  Trigger the "Test Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_START()                  \
+    JTEST_TRIGGER_ACTION(test_start)
+
+/**
+ *  Trigger the "Test End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_TEST_END()                    \
+    JTEST_TRIGGER_ACTION(test_end)
+
+
+/**
+ *  Trigger the "Group Start" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_START()                 \
+    JTEST_TRIGGER_ACTION(group_start)
+
+/**
+ *  Trigger the "Group End" action in the Keil Debugger.
+ */
+#define JTEST_ACT_GROUP_END()                   \
+    JTEST_TRIGGER_ACTION(group_end)
+
+
+/**
+ *  Fill the buffer named buf_name with value and dump it to the Keil debugger
+ *  using action.
+ */
+#define JTEST_ACT_DUMP(action, buf_name, value) \
+    do                                          \
+    {                                           \
+        JTEST_CLEAR_BUFFER(buf_name);           \
+        strcpy(JTEST_FW.buf_name, (value));     \
+        JTEST_TRIGGER_ACTION(action);           \
+    } while (0)
+
+/**
+ *  Trigger the "Exit Framework" action in the Keil Debugger.
+ */
+#define JTEST_ACT_EXIT_FW()                     \
+    do                                          \
+    {                                           \
+        JTEST_TRIGGER_ACTION(exit_fw);          \
+    } while (0)
+
+
+/* Buffer Manipulation Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Clear the JTEST_FW buffer with name buf_name.
+ */
+#define JTEST_CLEAR_BUFFER(buf_name)                    \
+    do                                                  \
+    {                                                   \
+        memset(JTEST_FW.buf_name, 0, JTEST_BUF_SIZE);   \
+    } while (0)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's string buffer.
+ */
+#define JTEST_CLEAR_STR_BUFFER()                \
+        JTEST_CLEAR_BUFFER(str_buffer)
+
+/**
+ *  Clear the memory needed for the JTEST_FW's data buffer.
+ */
+#define JTEST_CLEAR_DATA_BUFFER()               \
+        JTEST_CLEAR_BUFFER(data_buffer)
+
+/**
+ *  Dump the given string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STR(string)                          \
+        JTEST_ACT_DUMP(dump_str, str_buffer, string)
+
+/**
+ *  Dump a formatted string to the Keil Debugger.
+ */
+#define JTEST_DUMP_STRF(format_str, ... )                               \
+    do                                                                  \
+    {                                                                   \
+        JTEST_CLEAR_STR_BUFFER();                                       \
+        sprintf(JTEST_FW.str_buffer,format_str, __VA_ARGS__);           \
+        jtest_dump_str_segments();                                      \
+    } while (0)
+
+/* Pass/Fail Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_PASSED(amount)             \
+        JTEST_PF_INC_PASSED(&JTEST_FW, amount)
+
+/**
+ *  Increment the number of passed tests in #JTEST_FW.
+ */
+#define JTEST_FW_INC_FAILED(amount)             \
+        JTEST_PF_INC_FAILED(&JTEST_FW, amount)
+
+/* Manipulating the Current Group */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Evaluate to the current_group_ptr in #JTEST_FW.
+ */
+#define JTEST_CURRENT_GROUP_PTR()               \
+    (JTEST_FW.current_group_ptr)
+
+#define JTEST_SET_CURRENT_GROUP(group_ptr)      \
+    do                                          \
+    {                                           \
+        JTEST_CURRENT_GROUP_PTR() = group_ptr;  \
+    } while (0)
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Global Variables */
+/*--------------------------------------------------------------------------------*/
+extern char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE];
+extern volatile JTEST_FW_t JTEST_FW;
+
+/*--------------------------------------------------------------------------------*/
+/* Function Prototypes */
+/*--------------------------------------------------------------------------------*/
+void jtest_dump_str_segments(void);
+
+void test_start  (void);
+void test_end    (void);
+void group_start (void);
+void group_end   (void);
+void dump_str    (void);
+void dump_data   (void);
+void exit_fw     (void);
+
+
+#endif /* _JTEST_FW_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group.h

@@ -0,0 +1,66 @@
+#ifndef _JTEST_GROUP_H_
+#define _JTEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_pf.h"
+#include "jtest_util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a group of #JTEST_TEST_t structs. This struct is
+ *  used to run the group of tests, and report on their outcomes.
+ */
+typedef struct JTEST_GROUP_struct
+{
+    void (* group_fn_ptr) (void); /**< Pointer to the test group */
+    char * name_str;              /**< Name of the group */
+    
+    /* Extend the #JTEST_GROUP_t with Pass/Fail information.*/
+    JTEST_PF_MEMBERS;
+} JTEST_GROUP_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Set the name of JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_SET_NAME(group_ptr, name)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, name_str, name)
+
+#define JTEST_GROUP_SET_FN(group_ptr, fn_ptr)     \
+    JTEST_SET_STRUCT_ATTRIBUTE(group_ptr, group_fn_ptr, fn_ptr)
+
+/**
+ *  Increment the number of tests passed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_PASSED(group_ptr, amount) \
+    JTEST_PF_INC_PASSED(group_ptr, amount)
+
+/**
+ *  Increment the number of tests failed in the JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_INC_FAILED(group_ptr, amount) \
+    JTEST_PF_INC_FAILED(group_ptr, amount)
+
+/**
+ *  Reset the pass/fail information of the #JTEST_GROUP_t pointed to by
+ *  group_ptr.
+ */
+#define JTEST_GROUP_RESET_PF(group_ptr)         \
+    do                                          \
+    {                                           \
+        JTEST_PF_RESET_PASSED(group_ptr);       \
+        JTEST_PF_RESET_FAILED(group_ptr);       \
+    } while (0)
+
+#endif /* _JTEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_call.h

@@ -0,0 +1,126 @@
+#ifndef _JTEST_GROUP_CALL_H_
+#define _JTEST_GROUP_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_fw.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Execute the test in the #JTEST_GROUP_t struct associated witht he identifier
+ *  group_fn.
+ */
+#define JTEST_GROUP_RUN(group_fn)                                   \
+    do                                                              \
+    {                                                               \
+        JTEST_DUMP_STR("Group Name:\n");                            \
+        JTEST_DUMP_STR(JTEST_GROUP_STRUCT_NAME(group_fn).name_str); \
+        JTEST_GROUP_STRUCT_NAME(group_fn).group_fn_ptr();           \
+    } while (0)
+
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information using the
+ *  current #JTEST_GROUP_t's.
+ *
+ *  @param group_ptr Pointer to the current #JTEST_GROUP_t.
+ *  @param parent_ptr Pointer to the enclosing #JTEST_GROUP_t.
+ *
+ *  @warning Only run this if the current #JTEST_GROUP_t is being called within
+ *  the context of another #JTEST_GROUP_t.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_PF(group_ptr, parent_group_ptr) \
+    do                                                                  \
+    {                                                                   \
+        JTEST_GROUP_INC_PASSED(parent_group_ptr,                        \
+                               (group_ptr)->passed);                    \
+        JTEST_GROUP_INC_FAILED(parent_group_ptr,                        \
+                               (group_ptr)->failed);                    \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW's pass/fail information using the current
+ *  #JTEST_GROUP_t's.
+ */
+#define JTEST_GROUP_UPDATE_FW_PF(group_ptr)                     \
+    do                                                          \
+    {                                                           \
+        JTEST_FW_INC_PASSED((group_ptr)->passed);               \
+        JTEST_FW_INC_FAILED((group_ptr)->failed);               \
+    } while (0)
+
+/**
+ *  Update the enclosing context with the current #JTEST_GROUP_t's pass/fail
+ *  information. If this group isn't in an enclosing group, it updates the
+ *  #JTEST_FW's pass/fail info by default.
+ */
+#define JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(group_ptr,         \
+                                                 parent_group_ptr)  \
+    do                                                              \
+    {                                                               \
+        /* Update the pass fail counts in the parent group */       \
+        if (parent_group_ptr /* Null implies Top*/)                 \
+        {                                                           \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_PF(                     \
+                group_ptr,                                          \
+                parent_group_ptr);                                  \
+        } else {                                                    \
+            JTEST_GROUP_UPDATE_FW_PF(                               \
+                group_ptr);                                         \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Dump the results of running the #JTEST_GROUP_t to the Keil Debugger.
+ */
+#define JTEST_GROUP_DUMP_RESULTS(group_ptr)                             \
+        do                                                              \
+        {                                                               \
+            JTEST_DUMP_STRF(                                            \
+                "Tests Run: %" PRIu32 "\n"                              \
+                "----------\n"                                          \
+                "   Passed: %" PRIu32 "\n"                              \
+                "   Failed: %" PRIu32 "\n",                             \
+                (group_ptr)->passed + (group_ptr)->failed,              \
+                (group_ptr)->passed,                                    \
+                (group_ptr)->failed);                                   \
+        } while (0)
+
+/**
+ *  Call the #JTEST_GROUP_t associated with the identifier group_fn.
+ */
+#define JTEST_GROUP_CALL(group_fn)                                      \
+        do                                                              \
+        {   /* Save the current group from JTEST_FW_t before swapping */ \
+            /* it to this group (in order to restore it later )*/       \
+            JTEST_GROUP_t * __jtest_temp_group_ptr =                    \
+                JTEST_CURRENT_GROUP_PTR();                              \
+            JTEST_SET_CURRENT_GROUP(&JTEST_GROUP_STRUCT_NAME(group_fn)); \
+                                                                        \
+            /* Reset this group's pass/fail count. Each group */        \
+            /* should only remember counts for its last execution. */   \
+            JTEST_GROUP_RESET_PF(JTEST_CURRENT_GROUP_PTR());            \
+                                                                        \
+            /* Run the current group */                                 \
+            JTEST_ACT_GROUP_START();                                    \
+            JTEST_GROUP_RUN(group_fn);                                  \
+            JTEST_ACT_GROUP_END();                                      \
+                                                                        \
+            /* Update the pass fail counts in the parent group (or FW) */ \
+            JTEST_GROUP_UPDATE_PARENT_GROUP_OR_FW_PF(                   \
+                JTEST_CURRENT_GROUP_PTR(),                              \
+                __jtest_temp_group_ptr);                                \
+                                                                        \
+            JTEST_GROUP_DUMP_RESULTS(JTEST_CURRENT_GROUP_PTR());        \
+                                                                        \
+            /* Restore the previously current group */                  \
+            JTEST_SET_CURRENT_GROUP(__jtest_temp_group_ptr);            \
+        } while (0)
+
+#endif /* _JTEST_GROUP_CALL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_group_define.h

@@ -0,0 +1,87 @@
+#ifndef _JTEST_GROUP_DEFINE_H_
+#define _JTEST_GROUP_DEFINE_H_
+
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_group.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_GROUP_t structs.
+ */
+#define JTEST_GROUP_STRUCT_NAME_PREFIX G_JTEST_GROUP_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_GROUP_t tests.
+ */
+#define JTEST_GROUP_FN_TEMPLATE(group_fn)    \
+    void group_fn(void)
+
+#define JTEST_GROUP_FN_PROTOTYPE JTEST_GROUP_FN_TEMPLATE /**< Alias for
+                                                            #JTEST_GROUP_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_GROUP_t struct associated with group_fn.
+ */
+#define JTEST_GROUP_STRUCT_NAME(group_fn)    \
+    JTEST_STRUCT_NAME(JTEST_GROUP_STRUCT_NAME_PREFIX, group_fn)
+
+/**
+ *  Define a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DEFINE_STRUCT(group_fn)  \
+    JTEST_DEFINE_STRUCT(JTEST_GROUP_t,       \
+                        JTEST_GROUP_STRUCT_NAME(group_fn))
+
+/**
+ *  Declare a #JTEST_GROUP_t struct based on the given group_fn.
+ */
+#define JTEST_GROUP_DECLARE_STRUCT(group_fn) \
+    JTEST_DECLARE_STRUCT(JTEST_GROUP_DEFINE_STRUCT(group_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    group_fn,                                \
+        STR_NL(group_fn),                       \
+        JTEST_PF_MEMBER_INIT
+
+/**
+ *  Initialize the contents of a #JTEST_GROUP_t struct.
+ */
+#define JTEST_GROUP_INIT(group_fn)           \
+    JTEST_GROUP_DEFINE_STRUCT(group_fn) = {  \
+        JTEST_GROUP_STRUCT_INIT(group_fn)    \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_GROUP_t object and a test function.
+ */
+#define JTEST_DEFINE_GROUP(group_fn)         \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_INIT(group_fn);              \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_GROUP_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_GROUP(group_fn)        \
+    JTEST_GROUP_FN_PROTOTYPE(group_fn);      \
+    JTEST_GROUP_DECLARE_STRUCT(group_fn) /* Note the lacking semicolon */
+
+#endif /* _JTEST_GROUP_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_pf.h

@@ -0,0 +1,85 @@
+#ifndef _JTEST_PF_H_
+#define _JTEST_PF_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Purpose */
+/*--------------------------------------------------------------------------------*/
+/* jtest_pf.h Contains macros useful for capturing pass/fail data. */
+
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Members that can be added to other structs to extend them pass/fail data and
+ * corresponding functionality.
+ */
+#define JTEST_PF_MEMBERS                            \
+    uint32_t passed;                                \
+    uint32_t failed /* Note the lacking semicolon*/ \
+
+/**
+ *  Used for initializing JTEST_PF_MEMBERS in a struct declaration.
+ */
+#define JTEST_PF_MEMBER_INIT                    \
+    0,                                          \
+    0
+
+/* Member-Incrementing Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for incrementing #JTEST_PF_MEMBERS.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_INC_XXX(xxx, struct_pf_ptr, amount)    \
+    do                                                  \
+    {                                                   \
+        ((struct_pf_ptr)->xxx) += (amount);             \
+    } while (0)
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the passed
+ *  member.
+ */
+#define JTEST_PF_INC_PASSED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(passed, struct_pf_ptr, amount)
+
+
+/**
+ *  Specialization of the #JTEST_PF_INC_XXX macro to increment the failed
+ *  member.
+ */
+#define JTEST_PF_INC_FAILED(struct_pf_ptr, amount)  \
+    JTEST_PF_INC_XXX(failed, struct_pf_ptr, amount)
+
+
+/* Member-Resetting Macros */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Dispatch macro for setting #JTEST_PF_MEMBERS to zero.
+ *
+ *  @param xxx Values: 'passed', 'failed'
+ */
+#define JTEST_PF_RESET_XXX(xxx, struct_pf_ptr)  \
+    do                                          \
+    {                                           \
+        ((struct_pf_ptr)->xxx) = UINT32_C(0);   \
+    } while (0)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'passed' member.
+ */
+#define JTEST_PF_RESET_PASSED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(passed, struct_pf_ptr)
+
+/**
+ *  Specialization of #JTEST_PF_RESET_XXX for the 'failed' member.
+ */
+#define JTEST_PF_RESET_FAILED(struct_pf_ptr)    \
+    JTEST_PF_RESET_XXX(failed, struct_pf_ptr)
+
+#endif /* _JTEST_PF_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_systick.h

@@ -0,0 +1,93 @@
+#ifndef _JTEST_SYSTICK_H_
+#define _JTEST_SYSTICK_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+/* Get access to the SysTick structure. */
+#if   defined ARMCM0
+  #include "ARMCM0.h"
+#elif defined ARMCM0P
+  #include "ARMCM0plus.h"
+#elif defined ARMCM3
+  #include "ARMCM3.h"
+#elif defined ARMCM4
+  #include "ARMCM4.h"
+#elif defined ARMCM4_FP
+  #include "ARMCM4_FP.h"
+#elif defined ARMCM7
+  #include "ARMCM7.h" 
+#elif defined ARMCM7_SP
+  #include "ARMCM7_SP.h"
+#elif defined ARMCM7_DP
+  #include "ARMCM7_DP.h"
+#elif defined ARMSC000
+  #include "ARMSC000.h"
+#elif defined ARMSC300
+  #include "ARMSC300.h"
+#elif defined ARMv8MBL
+  #include "ARMv8MBL.h"
+#elif defined ARMv8MML
+  #include "ARMv8MML.h"
+#elif defined ARMv8MML_DSP
+  #include "ARMv8MML_DSP.h"
+#elif defined ARMv8MML_SP
+  #include "ARMv8MML_SP.h"
+#elif defined ARMv8MML_DSP_SP
+  #include "ARMv8MML_DSP_SP.h"
+#elif defined ARMv8MML_DP
+  #include "ARMv8MML_DP.h"
+#elif defined ARMv8MML_DSP_DP
+  #include "ARMv8MML_DSP_DP.h"
+
+#else
+  #warning "no appropriate header file found!"
+#endif
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Initial value for the SysTick module.
+ *
+ *  @note This is also the maximum value, important as SysTick is a decrementing
+ *  counter.
+ */
+#define JTEST_SYSTICK_INITIAL_VALUE 0xFFFFFF
+
+/**
+ *  Reset the SysTick, decrementing timer to it's maximum value and disable it.
+ *
+ *  This macro should leave the SysTick timer in a state that's ready for cycle
+ *  counting.
+ */
+#define JTEST_SYSTICK_RESET(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->LOAD = JTEST_SYSTICK_INITIAL_VALUE;  \
+        (systick_ptr)->VAL = 1;                             \
+                                                            \
+        /* Disable the SysTick module. */                   \
+        (systick_ptr)->CTRL = UINT32_C(0x000000);           \
+    } while (0)
+
+/**
+ *  Start the SysTick timer, sourced by the processor clock.
+ */
+#define JTEST_SYSTICK_START(systick_ptr)                    \
+    do                                                      \
+    {                                                       \
+        (systick_ptr)->CTRL =                               \
+            SysTick_CTRL_ENABLE_Msk |                       \
+            SysTick_CTRL_CLKSOURCE_Msk; /* Internal clk*/   \
+    } while (0)
+
+/**
+ *  Evaluate to the current value of the SysTick timer.
+ */
+#define JTEST_SYSTICK_VALUE(systick_ptr)        \
+    ((systick_ptr)->VAL)
+           
+#endif /* _JTEST_SYSTICK_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test.h

@@ -0,0 +1,100 @@
+#ifndef _JTEST_TEST_H_
+#define _JTEST_TEST_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include <stdint.h>
+#include "jtest_util.h"
+#include "jtest_test_ret.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  A struct which represents a Test in the JTEST framework.  This struct is
+ *  used to enable, run, and describe the test it represents.
+ */
+typedef struct JTEST_TEST_struct
+{
+    JTEST_TEST_RET_t ( * test_fn_ptr)(void); /**< Pointer to the test function. */
+    char   * test_fn_str;                    /**< Name of the test function */
+    char   * fut_str;           /**< Name of the function under test. */
+
+    /**
+     *  Flags that govern how the #JTEST_TEST_t behaves.
+     */
+    union {
+        struct {
+            unsigned enabled : 1;
+            unsigned unused  : 7;
+        } bits;
+        uint8_t byte;           /* Access all flags at once. */
+    } flags;
+    
+} JTEST_TEST_t;
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Assign a test function to the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FN(jtest_test_ptr, fn_ptr)                   \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, test_fn_ptr, fn_ptr)
+
+/**
+ *  Specify a function under test (FUT) for the #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_SET_FUT(jtest_test_ptr, str)                 \
+    JTEST_SET_STRUCT_ATTRIBUTE(jtest_test_ptr, fut_str, str)
+
+/* Macros concerning JTEST_TEST_t flags */
+/*--------------------------------------------------------------------------------*/
+
+#define JTEST_TEST_FLAG_SET 1 /**< Value of a set #JTEST_TEST_t flag. */
+#define JTEST_TEST_FLAG_CLR 0 /**< Value of a cleared #JTEST_TEST_t flag. */
+
+/**
+ *  Evaluate to the flag in #JTEST_TEST_t having flag_name.
+ */
+#define JTEST_TEST_FLAG(jtest_test_ptr, flag_name)  \
+    ((jtest_test_ptr)->flags.bits.flag_name)
+
+/**
+ *  Dispatch macro for setting and clearing #JTEST_TEST_t flags.
+ *
+ *  @param jtest_test_ptr Pointer to a #JTEST_TEST_t struct.
+ *  @param flag_name      Name of the flag to set in #JTEST_TEST_t.flags.bits
+ *  @param xxx            Vaid values: "SET" or "CLR"
+ *
+ *  @note This function depends on JTEST_TEST_FLAG_SET and JTEST_TEST_FLAG_CLR.
+ */
+#define JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, xxx)                  \
+    do                                                                       \
+    {                                                                        \
+        JTEST_TEST_FLAG(jtest_test_ptr, flag_name) = JTEST_TEST_FLAG_##xxx ; \
+    } while (0)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to set #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_SET_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, SET)
+
+/**
+ *  Specification of #JTEST_TEST_XXX_FLAG to clear #JTEST_TEST_t flags.
+ */
+#define JTEST_TEST_CLR_FLAG(jtest_test_ptr, flag_name)                       \
+    JTEST_TEST_XXX_FLAG(jtest_test_ptr, flag_name, CLR)
+
+/**
+ *  Evaluate to true if the #JTEST_TEST_t is enabled.
+ */
+#define JTEST_TEST_IS_ENABLED(jtest_test_ptr)                           \
+    (JTEST_TEST_FLAG(jtest_test_ptr, enabled) == JTEST_TEST_FLAG_SET)
+
+#endif /* _JTEST_TEST_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_call.h

@@ -0,0 +1,121 @@
+#ifndef _JTEST_TEST_CALL_H_
+#define _JTEST_TEST_CALL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "jtest_test.h"
+#include "jtest_test_define.h"
+#include "jtest_fw.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Exectute the test in the #JTEST_TEST_t struct associated with the identifier
+ *  test_fn and store the result in retval.
+ */
+#define JTEST_TEST_RUN(retval, test_fn)                                 \
+    do                                                                  \
+    {                                                                   \
+        JTEST_DUMP_STR("Test Name:\n");                                 \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).test_fn_str);    \
+        JTEST_DUMP_STR("Function Under Test:\n");                       \
+        JTEST_DUMP_STR(JTEST_TEST_STRUCT_NAME(test_fn).fut_str);        \
+        retval = JTEST_TEST_STRUCT_NAME(test_fn).test_fn_ptr();         \
+    } while (0)
+
+/**
+ *  Update the enclosing #JTEST_GROUP_t's pass/fail information based on
+ *  test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ *
+ *  @warning Only use if #JTEST_TEST_t is called in the context of a
+ *  #JTEST_GROUP_t.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval)              \
+    do                                                              \
+    {                                                               \
+        /* Update enclosing JTEST_GROUP_t with pass/fail info */    \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_GROUP_INC_PASSED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        } else {                                                    \
+            JTEST_GROUP_INC_FAILED(JTEST_CURRENT_GROUP_PTR(), 1);   \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the #JTEST_FW with pass/fail information based on test_retval.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_FW_PF(test_retval)                        \
+    do                                                              \
+    {                                                               \
+        /* Update the JTEST_FW with pass/fail info */                \
+        if (test_retval == JTEST_TEST_PASSED)                       \
+        {                                                           \
+            JTEST_FW_INC_PASSED( 1);                                \
+        } else {                                                    \
+            JTEST_FW_INC_FAILED(1);                                 \
+        }                                                           \
+    } while (0)
+
+/**
+ *  Update the enclosing JTEST_GROUP_t's pass/fail information, or the
+ *  #JTEST_FW's if this test has no enclosing #JTEST_GROUP_t.
+ *
+ *  @param test_retval A #JTEST_TEST_RET_enum for the current test.
+ */
+#define JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(test_retval)            \
+    do                                                                  \
+    {                                                                   \
+        /* Update pass-fail information */                              \
+        if (JTEST_CURRENT_GROUP_PTR() /* Non-null */)                    \
+        {                                                               \
+            JTEST_TEST_UPDATE_PARENT_GROUP_PF(test_retval);             \
+        } else {                                                        \
+            JTEST_TEST_UPDATE_FW_PF(test_retval);                       \
+        }                                                               \
+    } while (0)
+
+/**
+ *  Dump the results of the test to the Keil Debugger.
+ */
+#define JTEST_TEST_DUMP_RESULTS(test_retval)        \
+        do                                          \
+        {                                           \
+            if (test_retval == JTEST_TEST_PASSED)   \
+            {                                       \
+                JTEST_DUMP_STR("Test Passed\n");      \
+            } else {                                \
+                JTEST_DUMP_STR("Test Failed\n");      \
+            }                                       \
+        } while (0)
+
+/**
+ *  Call the #JTEST_TEST_t assocaited with the identifier test_fn.
+ */
+#define JTEST_TEST_CALL(test_fn)                                        \
+    do                                                                  \
+    {                                                                   \
+        if (JTEST_TEST_IS_ENABLED(&JTEST_TEST_STRUCT_NAME(test_fn)))    \
+        {                                                               \
+            /* Default to failure */                                    \
+            JTEST_TEST_RET_t __jtest_test_ret = JTEST_TEST_FAILED;      \
+                                                                        \
+            JTEST_ACT_TEST_START();                                     \
+            JTEST_TEST_RUN(__jtest_test_ret, test_fn);                  \
+                                                                        \
+            /* Update pass-fail information */                          \
+            JTEST_TEST_UPDATE_PARENT_GROUP_OR_FW_PF(__jtest_test_ret);  \
+                                                                        \
+            JTEST_TEST_DUMP_RESULTS(__jtest_test_ret);                  \
+            JTEST_ACT_TEST_END();                                       \
+        }                                                               \
+    } while (0)
+
+#endif /* _JTEST_TEST_CALL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_define.h

@@ -0,0 +1,133 @@
+#ifndef _JTEST_TEST_DEFINE_H_
+#define _JTEST_TEST_DEFINE_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "jtest_util.h"
+#include "jtest_define.h"
+#include "jtest_test.h"
+
+/* For defining macros with optional arguments */
+#include "opt_arg/opt_arg.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Prefix for all #JTEST_TEST_t structs.
+ */
+#define JTEST_TEST_STRUCT_NAME_PREFIX G_JTEST_TEST_STRUCT_
+
+/**
+ *  Define test template used by #JTEST_TEST_t tests.
+ */
+#define JTEST_TEST_FN_TEMPLATE(test_fn)                         \
+    JTEST_TEST_RET_t test_fn(void)
+
+#define JTEST_TEST_FN_PROTOTYPE JTEST_TEST_FN_TEMPLATE /**< Alias for
+                                                        * #JTEST_TEST_FN_TEMPLATE. */
+
+/**
+ *  Evaluate to the name of the #JTEST_TEST_t struct associated with test_fn.
+ */
+#define JTEST_TEST_STRUCT_NAME(test_fn)                         \
+    JTEST_STRUCT_NAME(JTEST_TEST_STRUCT_NAME_PREFIX, test_fn)
+
+/**
+ *  Define a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DEFINE_STRUCT(test_fn)                   \
+    JTEST_DEFINE_STRUCT(JTEST_TEST_t,                       \
+                        JTEST_TEST_STRUCT_NAME(test_fn))
+
+/**
+ *  Declare a #JTEST_TEST_t struct based on the given test_fn.
+ */
+#define JTEST_TEST_DECLARE_STRUCT(test_fn)      \
+    JTEST_DECLARE_STRUCT(JTEST_TEST_DEFINE_STRUCT(test_fn))
+
+/**
+ *  Contents needed to initialize a JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)    \
+    test_fn,                                            \
+        STR_NL(test_fn),                                   \
+        STR_NL(fut),                                       \
+    {                                                   \
+        {                                               \
+            enable,                                     \
+                0                                       \
+        }                                               \
+    }                                                   \
+        
+
+/**
+ *  Initialize the contents of a #JTEST_TEST_t struct.
+ */
+#define JTEST_TEST_INIT(test_fn, fut, enable)              \
+    JTEST_TEST_DEFINE_STRUCT(test_fn) = {                  \
+        JTEST_TEST_STRUCT_INIT(test_fn, fut, enable)       \
+    }
+
+/* Test Definition Macro */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Define a #JTEST_TEST_t object and a test function.
+ */
+#define _JTEST_DEFINE_TEST(test_fn, fut, enable)           \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                      \
+    JTEST_TEST_INIT(test_fn, fut, enable);                 \
+    JTEST_TEST_FN_PROTOTYPE(test_fn) /* Notice the lacking semicolon */
+
+/**
+ *  Declare a #JTEST_TEST_t object and a test function prototype.
+ */
+#define JTEST_DECLARE_TEST(test_fn)                                     \
+    JTEST_TEST_FN_PROTOTYPE(test_fn);                                   \
+    JTEST_TEST_DECLARE_STRUCT(test_fn) /* Note the lacking semicolon */
+
+/*--------------------------------------------------------------------------------*/
+/* Macros with optional arguments */
+/*--------------------------------------------------------------------------------*/
+
+/* Top-level Interface */
+#define JTEST_DEFINE_TEST(...)                             \
+    JTEST_DEFINE_TEST_(PP_NARG(__VA_ARGS__), ##__VA_ARGS__)
+
+/* Dispatch Macro*/
+#define JTEST_DEFINE_TEST_(N, ...)                         \
+    SPLICE(JTEST_DEFINE_TEST_, N)(__VA_ARGS__)
+
+/* Default Arguments */
+#define JTEST_DEFINE_TEST_DEFAULT_FUT /* Blank */
+#define JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+    JTEST_TRUE                                 /* Tests enabled by
+                                                * default. */ 
+
+/* Dispatch Cases*/
+#define JTEST_DEFINE_TEST_1(_1)                            \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_FUT,                     \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_2(_1, _2)                        \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        JTEST_DEFINE_TEST_DEFAULT_ENABLE                   \
+        )
+
+#define JTEST_DEFINE_TEST_3(_1, _2, _3)                    \
+    _JTEST_DEFINE_TEST(                                    \
+        _1,                                                \
+        _2,                                                \
+        _3                                                 \
+        )
+
+#endif /* _JTEST_TEST_DEFINE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_test_ret.h

@@ -0,0 +1,17 @@
+#ifndef _JTEST_TEST_RET_H_
+#define _JTEST_TEST_RET_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Type Definitions */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Values a #JTEST_TEST_t can return.
+ */
+typedef enum JTEST_TEST_RET_enum
+{
+    JTEST_TEST_PASSED,
+    JTEST_TEST_FAILED
+} JTEST_TEST_RET_t;
+
+#endif /* _JTEST_TEST_RET_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/jtest_util.h

@@ -0,0 +1,27 @@
+#ifndef _JTEST_UTIL_H_
+#define _JTEST_UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "util/util.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/* Define boolean values for the framework. */
+#define JTEST_TRUE  1           /**< Value used for TRUE in JTEST. */
+#define JTEST_FALSE 0           /**< Value used for FALSE in JTEST. */
+
+/**
+ *  Set the value of the attribute in the struct to by struct_ptr to value.
+ */
+#define JTEST_SET_STRUCT_ATTRIBUTE(struct_ptr, attribute, value)    \
+    do                                                              \
+    {                                                               \
+        (struct_ptr)->attribute = (value);                          \
+    } while (0)
+
+#endif /* _JTEST_UTIL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/opt_arg.h

@@ -0,0 +1,15 @@
+#ifndef _OPT_ARG_H_
+#define _OPT_ARG_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "pp_narg.h"
+#include "splice.h"
+
+/* If you are Joseph Jaoudi, you have a snippet which expands into an
+   example. If you are not Joseph, but possess his code, study the examples. If
+   you have no examples, turn back contact Joseph. */
+
+#endif /* _OPT_ARG_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/pp_narg.h

@@ -0,0 +1,25 @@
+#ifndef _PP_NARG_H_
+#define _PP_NARG_H_
+
+#define PP_NARG(...)                                      \
+    PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
+#define PP_NARG_(...)                                     \
+    PP_ARG_N(__VA_ARGS__)
+#define PP_ARG_N(                                         \
+                 _1, _2, _3, _4, _5, _6, _7, _8, _9,_10,  \
+                 _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+                 _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+                 _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+                 _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+                 _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+                 _61,_62,_63,N,...) N
+#define PP_RSEQ_N()                                       \
+    63,62,61,60,                                          \
+        59,58,57,56,55,54,53,52,51,50,                    \
+        49,48,47,46,45,44,43,42,41,40,                    \
+        39,38,37,36,35,34,33,32,31,30,                    \
+        29,28,27,26,25,24,23,22,21,20,                    \
+        19,18,17,16,15,14,13,12,11,10,                    \
+        9,8,7,6,5,4,3,2,1,0
+
+#endif /* _PP_NARG_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/opt_arg/splice.h

@@ -0,0 +1,8 @@
+#ifndef _SPLICE_H_
+#define _SPLICE_H_
+
+#define SPLICE(a,b) SPLICE_1(a,b)
+#define SPLICE_1(a,b) SPLICE_2(a,b)
+#define SPLICE_2(a,b) a##b
+
+#endif /* _SPLICE_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/inc/util/util.h

@@ -0,0 +1,52 @@
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Convert a symbol to a string and add a 'NewLine'.
+ */
+#define STR_NL(x)  STR1_NL(x)
+#define STR1_NL(x) (STR2_NL(x)"\n")
+#define STR2_NL(x) #x
+
+/**
+ *  Convert a symbol to a string.
+ */
+#define STR(x)  STR1(x)
+#define STR1(x) STR2(x)
+#define STR2(x) #x
+
+/**
+ *  Concatenate two symbols.
+ */
+#define CONCAT(a, b)  CONCAT1(a, b)
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define CONCAT2(a, b) a##b
+
+
+/**
+ *  Place curly braces around a varaible number of macro arguments.
+ */
+#define CURLY(...) {__VA_ARGS__}
+
+/**
+ *  Place parenthesis around a variable number of macro arguments.
+ */
+#define PAREN(...) (__VA_ARGS__)
+
+/* Standard min/max macros. */
+#define MIN(x,y) (((x) < (y)) ? (x) : (y) )
+#define MAX(x,y) (((x) > (y)) ? (x) : (y) )
+
+/**
+ *  Bound value using low and high limits.
+ *
+ *  Evaluate to a number in the range, endpoint inclusive.
+ */
+#define BOUND(low, high, value)                 \
+    MAX(MIN(high, value), low)
+
+#endif /* _UTIL_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c

@@ -0,0 +1,9 @@
+#include "../inc/jtest_cycle.h"
+#include <inttypes.h>
+
+/*--------------------------------------------------------------------------------*/
+/* Define Module Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* const char * JTEST_CYCLE_STRF = "Running: %s\nCycles: %" PRIu32 "\n"; */
+const char * JTEST_CYCLE_STRF = "Cycles: %" PRIu32 "\n"; /* function name + parameter string skipped */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c

@@ -0,0 +1,36 @@
+#include "jtest_fw.h"
+
+/**
+ *  Dump the JTEST_FW.str_buffer the Keil framework in pieces.
+ *
+ *  The JTEST_FW.str_buffer contains more characters than the Keil framework can
+ *  dump at once. This function dumps them in blocks.
+ */
+void jtest_dump_str_segments(void)
+{
+    uint32_t seg_idx      = 0;
+    uint32_t memmove_idx = 0;
+    uint32_t seg_cnt  =
+        (strlen(JTEST_FW.str_buffer) / JTEST_STR_MAX_OUTPUT_SIZE) + 1;
+
+    for( seg_idx = 0; seg_idx < seg_cnt; ++seg_idx)
+    {
+        JTEST_TRIGGER_ACTION(dump_str);
+
+        if (seg_idx < JTEST_STR_MAX_OUTPUT_SEGMENTS)
+        {
+            memmove_idx = 0;
+            while (memmove_idx < (seg_cnt - seg_idx -1) )
+            {
+                memmove(
+                    JTEST_FW.str_buffer+
+                    (memmove_idx* JTEST_STR_MAX_OUTPUT_SIZE),
+                    JTEST_FW.str_buffer+
+                    ((memmove_idx+1)*JTEST_STR_MAX_OUTPUT_SIZE),
+                    JTEST_BUF_SIZE);
+                ++memmove_idx;
+            }
+        }
+    }
+    return;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c

@@ -0,0 +1,9 @@
+#include "../inc/jtest.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Define Global Variables */
+/*--------------------------------------------------------------------------------*/
+
+char JTEST_FW_STR_BUFFER[JTEST_BUF_SIZE] = {0};
+
+volatile JTEST_FW_t JTEST_FW = {0};

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c

@@ -0,0 +1,37 @@
+
+#include "jtest_fw.h"
+
+void test_start    (void) {
+//  ;
+  JTEST_FW.test_start++;
+}
+
+void test_end      (void) {
+//  ;
+  JTEST_FW.test_end++;
+}
+
+void group_start   (void) {
+//  ;
+  JTEST_FW.group_start++;
+}
+
+void group_end     (void) {
+//  ;
+  JTEST_FW.group_end++;
+}
+
+void dump_str      (void) {
+//  ;
+  JTEST_FW.dump_str++;
+}
+
+void dump_data     (void) {
+//  ;
+  JTEST_FW.dump_data++;
+}
+
+void exit_fw       (void) {
+//  ;
+  JTEST_FW.exit_fw++;
+}

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/all_tests.h

@@ -0,0 +1,9 @@
+#ifndef _ALL_TESTS_H_
+#define _ALL_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(all_tests);
+
+#endif /* _ALL_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_templates.h

@@ -0,0 +1,267 @@
+#ifndef _BASIC_MATH_TEMPLATES_H_
+#define _BASIC_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the outputs used by basic math tests for the function under test and
+ *  the reference function.
+ */
+#define BASIC_MATH_COMPARE_INTERFACE(block_size, output_type)   \
+    TEST_ASSERT_BUFFERS_EQUAL(                                  \
+        basic_math_output_ref.data_ptr,                         \
+        basic_math_output_fut.data_ptr,                         \
+        block_size * sizeof(output_type))
+
+/*
+ * Comparison SNR thresholds for the data types used in basic_math_tests.
+ */
+#define BASIC_MATH_SNR_THRESHOLD_float32_t 120
+#define BASIC_MATH_SNR_THRESHOLD_q31_t 100
+#define BASIC_MATH_SNR_THRESHOLD_q15_t 75
+#define BASIC_MATH_SNR_THRESHOLD_q7_t 25
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_COMPARE_INTERFACE(block_size, output_type)   \
+    do                                                              \
+    {                                                               \
+        TEST_CONVERT_AND_ASSERT_SNR(                                \
+            basic_math_output_f32_ref,                              \
+            basic_math_output_ref.data_ptr,                         \
+            basic_math_output_f32_fut,                              \
+            basic_math_output_fut.data_ptr,                         \
+            block_size,                                             \
+            output_type,                                            \
+            BASIC_MATH_SNR_THRESHOLD_##output_type                  \
+            );                                                      \
+    } while (0)
+
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define BASIC_MATH_SNR_ELT1_COMPARE_INTERFACE(block_size, output_type)  \
+    do                                                                  \
+    {                                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                                    \
+            basic_math_output_f32_ref,                                  \
+            basic_math_output_ref.data_ptr,                             \
+            basic_math_output_f32_fut,                                  \
+            basic_math_output_fut.data_ptr,                             \
+            1,                                                          \
+            output_type,                                                \
+            BASIC_MATH_SNR_THRESHOLD_##output_type                      \
+            );                                                          \
+    } while (0)
+
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_abs_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_abs_INPUT_INTERFACE(input, block_size)              \
+    PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_add_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_add_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size)      \
+    PAREN(input_a, input_b, block_size, basic_math_output_fut.data_ptr) \
+
+#define REF_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size)      \
+    PAREN(input_a, input_b, block_size, basic_math_output_ref.data_ptr) \
+
+#define ARM_mult_INPUT_INTERFACE(input_a, input_b, block_size)          \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_mult_INPUT_INTERFACE(input_a, input_b, block_size)          \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_negate_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, basic_math_output_fut.data_ptr, block_size)
+
+#define REF_negate_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, basic_math_output_ref.data_ptr, block_size)
+
+#define ARM_offset_INPUT_INTERFACE(input, elt, block_size)          \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_offset_INPUT_INTERFACE(input, elt, block_size)          \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+#define ARM_shift_INPUT_INTERFACE(input, elt, block_size)           \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_shift_INPUT_INTERFACE(input, elt, block_size)           \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+#define ARM_scale_float_INPUT_INTERFACE(input, elt, block_size)     \
+    PAREN(input, elt, basic_math_output_fut.data_ptr, block_size)   \
+
+#define REF_scale_float_INPUT_INTERFACE(input, elt, block_size)     \
+    PAREN(input, elt, basic_math_output_ref.data_ptr, block_size)   \
+
+/* These two are for the fixed point functions */
+#define ARM_scale_INPUT_INTERFACE(input, elt1, elt2, block_size)        \
+    PAREN(input, elt1, elt2, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_scale_INPUT_INTERFACE(input, elt1, elt2, block_size)        \
+    PAREN(input, elt1, elt2, basic_math_output_ref.data_ptr, block_size) \
+
+#define ARM_sub_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_fut.data_ptr, block_size) \
+
+#define REF_sub_INPUT_INTERFACE(input_a, input_b, block_size)           \
+    PAREN(input_a, input_b, basic_math_output_ref.data_ptr, block_size) \
+
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,       \
+                                                 suffix,        \
+                                                 input_type,    \
+                                                 output_type)   \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,          \
+                      arm_##fn_name##_##suffix)                 \
+    {                                                           \
+        TEST_TEMPLATE_BUF1_BLK(                                 \
+            basic_math_f_all,                                   \
+            basic_math_block_sizes,                             \
+            input_type,                                         \
+            output_type,                                        \
+            arm_##fn_name##_##suffix,                           \
+            ARM_##fn_name##_INPUT_INTERFACE,                    \
+            ref_##fn_name##_##suffix,                           \
+            REF_##fn_name##_INPUT_INTERFACE,                    \
+            BASIC_MATH_COMPARE_INTERFACE);                      \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF2_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name,               \
+                                                 suffix,                \
+                                                 input_type,            \
+                                                 output_type,           \
+                                                 comparison_interface)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,                  \
+                      arm_##fn_name##_##suffix)                         \
+    {                                                                   \
+        TEST_TEMPLATE_BUF2_BLK(                                         \
+            basic_math_f_all,                                           \
+            basic_math_f_all,                                           \
+            basic_math_block_sizes,                                     \
+            input_type,                                                 \
+            output_type,                                                \
+            arm_##fn_name##_##suffix,                                   \
+            ARM_##fn_name##_INPUT_INTERFACE,                            \
+            ref_##fn_name##_##suffix,                                   \
+            REF_##fn_name##_INPUT_INTERFACE,                            \
+            comparison_interface);                                      \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_ELT1_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT1_BLK(fn_name,      \
+                                                      suffix,       \
+                                                      input_type,   \
+                                                      elt_type,     \
+                                                      output_type)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_ELT1_BLK(                                \
+            basic_math_f_all,                                       \
+            basic_math_elts,                                        \
+            basic_math_block_sizes,                                 \
+            input_type,                                             \
+            elt_type,                                               \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            BASIC_MATH_COMPARE_INTERFACE);                          \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_ELT2_BLK() for basic math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define BASIC_MATH_DEFINE_TEST_TEMPLATE_BUF1_ELT2_BLK(fn_name,      \
+                                                      suffix,       \
+                                                      input_type,   \
+                                                      elt1_type,    \
+                                                      elt2_type,    \
+                                                      output_type)  \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_ELT2_BLK(                                \
+            basic_math_f_all,                                       \
+            basic_math_elts,                                        \
+            basic_math_elts2,                                       \
+            basic_math_block_sizes,                                 \
+            input_type,                                             \
+            elt1_type,                                              \
+            elt2_type,                                              \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            BASIC_MATH_COMPARE_INTERFACE);                          \
+    }
+
+#endif /* _BASIC_MATH_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_data.h

@@ -0,0 +1,46 @@
+#ifndef ARM_BASIC_MATH_TEST_DATA_H
+#define ARM_BASIC_MATH_TEST_DATA_H
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define BASIC_MATH_MAX_INPUT_ELEMENTS 32
+#define BASIC_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(basic_math_output_fut);
+ARR_DESC_DECLARE(basic_math_output_ref);
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_ref[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+extern BASIC_MATH_BIGGEST_INPUT_TYPE
+basic_math_output_f32_fut[BASIC_MATH_MAX_INPUT_ELEMENTS];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(basic_math_block_sizes);
+
+/* Numbers */
+ARR_DESC_DECLARE(basic_math_elts);
+ARR_DESC_DECLARE(basic_math_elts2);
+ARR_DESC_DECLARE(basic_math_eltsf);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(basic_math_zeros);
+ARR_DESC_DECLARE(basic_math_f_2);
+ARR_DESC_DECLARE(basic_math_f_15);
+ARR_DESC_DECLARE(basic_math_f_32);
+ARR_DESC_DECLARE(basic_math_f_all);
+
+#endif

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_test_group.h

@@ -0,0 +1,9 @@
+#ifndef _BASIC_MATH_TEST_GROUP_H_
+#define _BASIC_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(basic_math_tests);
+
+#endif /* _BASIC_MATH_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/basic_math_tests/basic_math_tests.h

@@ -0,0 +1,17 @@
+#ifndef _BASIC_MATH_TESTS_H_
+#define _BASIC_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(abs_tests);
+JTEST_DECLARE_GROUP(add_tests);
+JTEST_DECLARE_GROUP(dot_prod_tests);
+JTEST_DECLARE_GROUP(mult_tests);
+JTEST_DECLARE_GROUP(negate_tests);
+JTEST_DECLARE_GROUP(offset_tests);
+JTEST_DECLARE_GROUP(scale_tests);
+JTEST_DECLARE_GROUP(shift_tests);
+JTEST_DECLARE_GROUP(sub_tests);
+
+#endif /* _BASIC_MATH_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_templates.h

@@ -0,0 +1,222 @@
+#ifndef _COMPLEX_MATH_TEMPLATES_H_
+#define _COMPLEX_MATH_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+#include "test_templates.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Compare the real outputs from the function under test and the reference
+ *  function.
+ */
+#define COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size, output_type)  \
+    TEST_ASSERT_BUFFERS_EQUAL(                                      \
+        complex_math_output_ref_a.data_ptr,                         \
+        complex_math_output_fut_a.data_ptr,                         \
+        block_size * sizeof(output_type))
+
+/**
+ *  Compare the real and imaginary outputs from the function under test and the
+ *  reference function.
+ */
+#define COMPLEX_MATH_COMPARE_CMPLX_INTERFACE(block_size, output_type)   \
+    do                                                                  \
+    {                                                                   \
+        COMPLEX_MATH_COMPARE_RE_INTERFACE(block_size * 2, output_type); \
+    } while (0)
+
+
+/*
+ * Comparison SNR thresholds for the data types used in complex_math_tests.
+ */
+#define COMPLEX_MATH_SNR_THRESHOLD_float32_t 120
+#define COMPLEX_MATH_SNR_THRESHOLD_q31_t 100
+#define COMPLEX_MATH_SNR_THRESHOLD_q15_t 75
+
+/**
+ *  Compare reference and fut outputs using SNR.
+ *
+ *  The output_suffix specifies which output buffers to use for the
+ *  comparison. An output_suffix of 'a' expands to the following buffers:
+ *
+ *  - complex_math_output_f32_ref_a
+ *  - complex_math_output_f32_fut_a
+ *  - complex_math_output_ref_a
+ *  - complex_math_output_fut_a
+ *
+ *  @note The outputs are converted to float32_t before comparison.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,      \
+                                               output_type,     \
+                                               output_suffix)   \
+    do                                                          \
+    {                                                           \
+        TEST_CONVERT_AND_ASSERT_SNR(                            \
+            complex_math_output_f32_ref_##output_suffix,        \
+            complex_math_output_ref_##output_suffix.data_ptr,   \
+            complex_math_output_f32_fut_##output_suffix,        \
+            complex_math_output_fut_##output_suffix.data_ptr,   \
+            block_size,                                         \
+            output_type,                                        \
+            COMPLEX_MATH_SNR_THRESHOLD_##output_type            \
+            );                                                  \
+    } while (0)
+
+/**
+ *  Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for real outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_RE_INTERFACE(block_size,       \
+                                                   output_type) \
+    COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,          \
+                                           output_type,         \
+                                           a)
+
+/**
+ *  Specification of #COMPLEX_MATH_SNR_COMPARE_INTERFACE() for complex outputs.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_CMPLX_INTERFACE(block_size,    \
+                                                 output_type)   \
+        COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size * 2,  \
+                                               output_type,     \
+                                               a)
+
+/**
+ *  Compare reference and fut split outputs using SNR.
+ *
+ *  'Split' refers to two separate output buffers; one for real and one for
+ *  complex.
+ */
+#define COMPLEX_MATH_SNR_COMPARE_SPLIT_INTERFACE(block_size,    \
+                                                 output_type)   \
+        do                                                      \
+        {                                                       \
+            COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,  \
+                                                   output_type, \
+                                                   a);          \
+            COMPLEX_MATH_SNR_COMPARE_OUT_INTERFACE(block_size,  \
+                                                   output_type, \
+                                                   b);          \
+        } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* Input Interfaces */
+/*--------------------------------------------------------------------------------*/
+/*
+ *  General:
+ *  Input interfaces provide inputs to functions inside test templates.  They
+ *  ONLY provide the inputs.  The output variables should be hard coded.
+ *
+ *  The input interfaces must have the following format:
+ *
+ *  ARM_xxx_INPUT_INTERFACE() or
+ *  REF_xxx_INPUT_INTERFACE()
+ *
+ *  The xxx must be lowercase, and is intended to be the indentifying substring
+ *  in the function's name.  Acceptable values are 'sub' or 'add' from the
+ *  functions arm_add_q31.
+ */
+
+#define ARM_cmplx_conj_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_conj_INPUT_INTERFACE(input, block_size)           \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, block_size,                                 \
+          complex_math_output_fut_a.data_ptr,                          \
+          complex_math_output_fut_b.data_ptr)
+
+#define REF_cmplx_dot_prod_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, block_size,                                 \
+          complex_math_output_ref_a.data_ptr,                          \
+          complex_math_output_ref_b.data_ptr)
+
+#define ARM_cmplx_mag_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_INPUT_INTERFACE(input, block_size)            \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mag_squared_INPUT_INTERFACE(input, block_size)    \
+    PAREN(input, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mag_squared_INPUT_INTERFACE(input, block_size)    \
+    PAREN(input, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_cmplx_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+#define ARM_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_fut_a.data_ptr, block_size)
+
+#define REF_cmplx_mult_real_INPUT_INTERFACE(input_a, input_b, block_size) \
+    PAREN(input_a, input_b, complex_math_output_ref_a.data_ptr, block_size)
+
+/*--------------------------------------------------------------------------------*/
+/* Test Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF1_BLK() for complex math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF1_BLK(fn_name,         \
+                                                   suffix,          \
+                                                   input_type,      \
+                                                   output_type,     \
+                                                   comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF1_BLK(                                     \
+            complex_math_f_all,                                     \
+            complex_math_block_sizes,                               \
+            input_type,                                             \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+/**
+ *  Specialization of #TEST_TEMPLATE_BUF2_BLK1() for complex math tests.
+ *
+ *  @note This macro relies on the existance of ARM_xxx_INPUT_INTERFACE and
+ *  REF_xxx_INPUT_INTERFACEs.
+ */
+#define COMPLEX_MATH_DEFINE_TEST_TEMPLATE_BUF2_BLK(fn_name,         \
+                                                   suffix,          \
+                                                   input_type,      \
+                                                   output_type,     \
+                                                   comparison_interface) \
+    JTEST_DEFINE_TEST(arm_##fn_name##_##suffix##_test,              \
+                      arm_##fn_name##_##suffix)                     \
+    {                                                               \
+        TEST_TEMPLATE_BUF2_BLK(                                     \
+            complex_math_f_all,                                     \
+            complex_math_f_all,                                     \
+            complex_math_block_sizes,                               \
+            input_type,                                             \
+            output_type,                                            \
+            arm_##fn_name##_##suffix,                               \
+            ARM_##fn_name##_INPUT_INTERFACE,                        \
+            ref_##fn_name##_##suffix,                               \
+            REF_##fn_name##_INPUT_INTERFACE,                        \
+            comparison_interface);                                  \
+    }
+
+#endif /* _COMPLEX_MATH_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_data.h

@@ -0,0 +1,50 @@
+#ifndef _COMPLEX_MATH_TEST_DATA_H_
+#define _COMPLEX_MATH_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arr_desc.h"
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+#define COMPLEX_MATH_MAX_INPUT_ELEMENTS 32
+#define COMPLEX_MATH_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Decalare Variables */
+/*--------------------------------------------------------------------------------*/
+
+/* Input/Output Buffers */
+ARR_DESC_DECLARE(complex_math_output_fut_a);
+ARR_DESC_DECLARE(complex_math_output_fut_b);
+ARR_DESC_DECLARE(complex_math_output_ref_a);
+ARR_DESC_DECLARE(complex_math_output_ref_b);
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_ref_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_a[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+extern COMPLEX_MATH_BIGGEST_INPUT_TYPE
+complex_math_output_f32_fut_b[COMPLEX_MATH_MAX_INPUT_ELEMENTS * 2];
+
+/* Block Sizes*/
+ARR_DESC_DECLARE(complex_math_block_sizes);
+
+/* Float Inputs */
+ARR_DESC_DECLARE(complex_math_zeros);
+ARR_DESC_DECLARE(complex_math_f_2);
+ARR_DESC_DECLARE(complex_math_f_15);
+ARR_DESC_DECLARE(complex_math_f_32);
+ARR_DESC_DECLARE(complex_math_f_all);
+
+
+#endif /* _COMPLEX_MATH_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_test_group.h

@@ -0,0 +1,9 @@
+#ifndef _COMPLEX_MATH_TEST_GROUP_H_
+#define _COMPLEX_MATH_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Groups */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(complex_math_tests);
+
+#endif /* _COMPLEX_MATH_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/complex_math_tests/complex_math_tests.h

@@ -0,0 +1,14 @@
+#ifndef _COMPLEX_MATH_TESTS_H_
+#define _COMPLEX_MATH_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(cmplx_conj_tests);
+JTEST_DECLARE_GROUP(cmplx_dot_prod_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_tests);
+JTEST_DECLARE_GROUP(cmplx_mag_squared_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_cmplx_tests);
+JTEST_DECLARE_GROUP(cmplx_mult_real_tests);
+
+#endif /* _COMPLEX_MATH_TESTS_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_templates.h

@@ -0,0 +1,46 @@
+#ifndef _CONTROLLER_TEMPLATES_H_
+#define _CONTROLLER_TEMPLATES_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "test_templates.h"
+#include <string.h>             /* memcpy() */
+
+/*--------------------------------------------------------------------------------*/
+/* Group Specific Templates */
+/*--------------------------------------------------------------------------------*/
+
+/**
+ * Comparison SNR thresholds for the data types used in transform_tests.
+ */
+#define CONTROLLER_SNR_THRESHOLD_float32_t 110
+#define CONTROLLER_SNR_THRESHOLD_q31_t     100
+#define CONTROLLER_SNR_THRESHOLD_q15_t     45
+
+/**
+ *  Compare the outputs from the function under test and the reference
+ *  function using SNR.
+ */
+#define CONTROLLER_SNR_COMPARE_INTERFACE(block_size,    \
+                                         output_type)   \
+    do                                                  \
+    {                                                   \
+        TEST_CONVERT_AND_ASSERT_SNR(                    \
+            controller_output_f32_ref,                  \
+            (output_type *) controller_output_ref,      \
+            controller_output_f32_fut,                  \
+            (output_type *) controller_output_fut,      \
+            block_size,                                 \
+            output_type,                                \
+            CONTROLLER_SNR_THRESHOLD_##output_type      \
+            );                                          \
+    } while (0)
+
+
+/*--------------------------------------------------------------------------------*/
+/* TEST Templates */
+/*--------------------------------------------------------------------------------*/
+
+#endif /* _CONTROLLER_TEMPLATES_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_data.h

@@ -0,0 +1,33 @@
+#ifndef _CONTROLLER_TEST_DATA_H_
+#define _CONTROLLER_TEST_DATA_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Includes */
+/*--------------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------------------*/
+/* Macros and Defines */
+/*--------------------------------------------------------------------------------*/
+
+#define CONTROLLER_MAX_LEN 1024
+#define CONTROLLER_MAX_COEFFS_LEN (12 * 3)
+#define TRANFORM_BIGGEST_INPUT_TYPE float32_t
+
+/*--------------------------------------------------------------------------------*/
+/* Variable Declarations */
+/*--------------------------------------------------------------------------------*/
+
+extern float32_t controller_output_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_ref[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_fut[CONTROLLER_MAX_LEN];
+extern float32_t controller_output_f32_ref[CONTROLLER_MAX_LEN];
+extern const float32_t controller_f32_inputs[CONTROLLER_MAX_LEN];
+extern const q31_t controller_q31_inputs[CONTROLLER_MAX_LEN];
+extern const q15_t * controller_q15_inputs;
+extern const float32_t controller_f32_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q31_t controller_q31_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+extern const q15_t controller_q15_coeffs[CONTROLLER_MAX_COEFFS_LEN];
+
+#endif /* _CONTROLLER_TEST_DATA_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_test_group.h

@@ -0,0 +1,9 @@
+#ifndef _CONTROLLER_TEST_GROUP_H_
+#define _CONTROLLER_TEST_GROUP_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Declare Test Group */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(controller_tests);
+
+#endif /* _CONTROLLER_TEST_GROUP_H_ */

Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/controller_tests/controller_tests.h

@@ -0,0 +1,11 @@
+#ifndef _CONTROLLER_TESTS_H_
+#define _CONTROLLER_TESTS_H_
+
+/*--------------------------------------------------------------------------------*/
+/* Test/Group Declarations */
+/*--------------------------------------------------------------------------------*/
+JTEST_DECLARE_GROUP(pid_reset_tests);
+JTEST_DECLARE_GROUP(sin_cos_tests);
+JTEST_DECLARE_GROUP(pid_tests);
+
+#endif /* _CONTROLLER_TESTS_H_ */