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Modbus-rtu/PLSR/Src/plsr_platform_f407.c

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  1. #include "plsr_platform.h"

  2. #include "plsr.h"

  3. 

  4. #ifdef PLSR_HOST_TEST

  5. 

  6. #include <string.h>

  7. 

  8. static uint8_t PlsrHostPulseActive[4];

  9. static uint32_t PlsrHostFrequency[4];

  10. static uint32_t PlsrHostQueuedFrequency[4];

  11. static uint8_t PlsrHostUpdatePending[4];

  12. static uint8_t PlsrHostInputs[2];

  13. static uint8_t PlsrHostSelectedPulse;

  14. static uint8_t PlsrHostDirectionLevel;

  15. static uint8_t PlsrHostEmitPulseOnCriticalEntry;

  16. static uint8_t PlsrHostEmitPulseOnCriticalExit;

  17. static uint8_t PlsrHostLatchPulseOnCriticalEntry;

  18. static uint8_t PlsrHostCriticalEntriesToSkip;

  19. static uint8_t PlsrHostFailNextStart;

  20. static uint8_t PlsrHostFailNextFrequencyAtUpdate;

  21. static PLSR_PERSIST_PAYLOAD PlsrHostPersistentPayload;

  22. static uint8_t PlsrHostPersistentValid;

  23. static uint32_t PlsrHostSaveCount;

  24. 

  25. static void PlsrHostLatchPulse(uint8_t pulseOutput)

  26. {

  27.     if ((pulseOutput <= 3U)

  28.         && (PlsrHostPulseActive[pulseOutput] != 0U))

  29.     {

  30.         PlsrHostFrequency[pulseOutput] =

  31.             PlsrHostQueuedFrequency[pulseOutput];

  32.         PlsrHostUpdatePending[pulseOutput] = 1U;

  33.     }

  34. }

  35. 

  36. static void PlsrHostServicePendingPulse(uint8_t pulseOutput)

  37. {

  38.     if ((pulseOutput <= 3U)

  39.         && (PlsrHostUpdatePending[pulseOutput] != 0U))

  40.     {

  41.         PlsrHostUpdatePending[pulseOutput] = 0U;

  42.         PlsrPulseTimerIrq(pulseOutput);

  43.     }

  44. }

  45. 

  46. uint8_t PlsrPlatformInit(void)

  47. {

  48.     (void)memset(PlsrHostPulseActive, 0, sizeof(PlsrHostPulseActive));

  49.     (void)memset(PlsrHostFrequency, 0, sizeof(PlsrHostFrequency));

  50.     (void)memset(PlsrHostQueuedFrequency, 0,

  51.                  sizeof(PlsrHostQueuedFrequency));

  52.     (void)memset(PlsrHostUpdatePending, 0,

  53.                  sizeof(PlsrHostUpdatePending));

  54.     PlsrHostSelectedPulse = 0U;

  55.     PlsrHostDirectionLevel = 0U;

  56.     PlsrHostEmitPulseOnCriticalEntry = 0U;

  57.     PlsrHostEmitPulseOnCriticalExit = 0U;

  58.     PlsrHostLatchPulseOnCriticalEntry = 0U;

  59.     PlsrHostCriticalEntriesToSkip = 0U;

  60.     PlsrHostFailNextStart = 0U;

  61.     PlsrHostFailNextFrequencyAtUpdate = 0U;

  62.     return 1U;

  63. }

  64. 

  65. uint8_t PlsrPlatformPrepare(uint8_t pulseOutput,

  66.                             uint8_t directionOutput,

  67.                             uint8_t directionLevel)

  68. {

  69.     uint8_t index;

  70.     (void)directionOutput;

  71. 

  72.     if (PlsrHostFailNextStart != 0U)

  73.     {

  74.         PlsrHostFailNextStart = 0U;

  75.         return 0U;

  76.     }

  77.     if ((pulseOutput > 3U) || (directionOutput > 3U))

  78.     {

  79.         return 0U;

  80.     }

  81.     for (index = 0U; index < 4U; index++)

  82.     {

  83.         PlsrHostPulseActive[index] = 0U;

  84.         PlsrHostFrequency[index] = 0UL;

  85.         PlsrHostQueuedFrequency[index] = 0UL;

  86.         PlsrHostUpdatePending[index] = 0U;

  87.     }

  88.     PlsrHostSelectedPulse = pulseOutput;

  89.     PlsrHostDirectionLevel = (directionLevel != 0U) ? 1U : 0U;

  90.     return 1U;

  91. }

  92. 

  93. uint8_t PlsrPlatformStartPulse(uint8_t pulseOutput,

  94.                                uint32_t firstFrequencyHz,

  95.                                uint32_t queuedFrequencyHz,

  96.                                uint32_t *actualFirstFrequencyHz,

  97.                                uint32_t *actualQueuedFrequencyHz)

  98. {

  99.     if ((pulseOutput > 3U) || (firstFrequencyHz == 0UL)

  100.         || (firstFrequencyHz > PLSR_FREQUENCY_MAX_HZ)

  101.         || (queuedFrequencyHz == 0UL)

  102.         || (queuedFrequencyHz > PLSR_FREQUENCY_MAX_HZ)

  103.         || (actualFirstFrequencyHz == NULL)

  104.         || (actualQueuedFrequencyHz == NULL))

  105.     {

  106.         return 0U;

  107.     }

  108.     PlsrHostPulseActive[pulseOutput] = 1U;

  109.     PlsrHostFrequency[pulseOutput] = firstFrequencyHz;

  110.     PlsrHostQueuedFrequency[pulseOutput] = queuedFrequencyHz;

  111.     PlsrHostUpdatePending[pulseOutput] = 0U;

  112.     PlsrHostSelectedPulse = pulseOutput;

  113.     *actualFirstFrequencyHz = firstFrequencyHz;

  114.     *actualQueuedFrequencyHz = queuedFrequencyHz;

  115.     return 1U;

  116. }

  117. 

  118. uint8_t PlsrPlatformQueueFrequency(uint8_t pulseOutput,

  119.                                    uint32_t frequencyHz,

  120.                                    uint32_t *actualFrequencyHz)

  121. {

  122.     if (PlsrHostFailNextFrequencyAtUpdate != 0U)

  123.     {

  124.         PlsrHostFailNextFrequencyAtUpdate = 0U;

  125.         return 0U;

  126.     }

  127.     if ((pulseOutput > 3U) || (frequencyHz == 0UL)

  128.         || (frequencyHz > PLSR_FREQUENCY_MAX_HZ)

  129.         || (actualFrequencyHz == NULL)

  130.         || (PlsrHostPulseActive[pulseOutput] == 0U))

  131.     {

  132.         return 0U;

  133.     }

  134.     PlsrHostQueuedFrequency[pulseOutput] = frequencyHz;

  135.     *actualFrequencyHz = frequencyHz;

  136.     return 1U;

  137. }

  138. 

  139. void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput)

  140. {

  141.     PlsrHostServicePendingPulse(pulseOutput);

  142. }

  143. 

  144. uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput)

  145. {

  146.     return (pulseOutput <= 3U) ? PlsrHostFrequency[pulseOutput] : 0UL;

  147. }

  148. 

  149. void PlsrPlatformStopPulse(uint8_t pulseOutput)

  150. {

  151.     if (pulseOutput <= 3U)

  152.     {

  153.         PlsrHostPulseActive[pulseOutput] = 0U;

  154.         PlsrHostFrequency[pulseOutput] = 0UL;

  155.         PlsrHostQueuedFrequency[pulseOutput] = 0UL;

  156.         PlsrHostUpdatePending[pulseOutput] = 0U;

  157.     }

  158. }

  159. 

  160. uint8_t PlsrPlatformReadInput(uint8_t inputSelection)

  161. {

  162.     return (inputSelection <= 1U) ? PlsrHostInputs[inputSelection] : 0U;

  163. }

  164. 

  165. uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload)

  166. {

  167.     if ((payload == NULL) || (PlsrHostPersistentValid == 0U))

  168.     {

  169.         return 0U;

  170.     }

  171.     *payload = PlsrHostPersistentPayload;

  172.     return 1U;

  173. }

  174. 

  175. uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload)

  176. {

  177.     if (payload == NULL)

  178.     {

  179.         return 0U;

  180.     }

  181.     PlsrHostPersistentPayload = *payload;

  182.     PlsrHostPersistentValid = 1U;

  183.     PlsrHostSaveCount++;

  184.     return 1U;

  185. }

  186. 

  187. void PlsrPlatformCheckpointConfig(const PLSR_CONFIG *config)

  188. {

  189.     if (config != NULL)

  190.     {

  191.         PlsrHostPersistentPayload.config = *config;

  192.         PlsrHostPersistentValid = 1U;

  193.     }

  194. }

  195. 

  196. void PlsrPlatformCheckpointPosition(int32_t position,

  197.                                     uint8_t positionValid,

  198.                                     uint8_t wasBusy)

  199. {

  200.     PlsrHostPersistentPayload.position = position;

  201.     PlsrHostPersistentPayload.positionValid = positionValid;

  202.     PlsrHostPersistentPayload.wasBusy = wasBusy;

  203.     PlsrHostPersistentPayload.reserved = 0U;

  204. }

  205. 

  206. uint32_t PlsrPlatformEnterCritical(void)

  207. {

  208.     if (PlsrHostEmitPulseOnCriticalEntry != 0U)

  209.     {

  210.         if (PlsrHostCriticalEntriesToSkip != 0U)

  211.         {

  212.             PlsrHostCriticalEntriesToSkip--;

  213.         }

  214.         else

  215.         {

  216.             PlsrHostEmitPulseOnCriticalEntry = 0U;

  217.             PlsrHostLatchPulse(PlsrHostSelectedPulse);

  218.             PlsrHostServicePendingPulse(PlsrHostSelectedPulse);

  219.         }

  220.     }

  221.     if (PlsrHostLatchPulseOnCriticalEntry != 0U)

  222.     {

  223.         PlsrHostLatchPulseOnCriticalEntry = 0U;

  224.         PlsrHostLatchPulse(PlsrHostSelectedPulse);

  225.     }

  226.     return 0UL;

  227. }

  228. 

  229. void PlsrPlatformExitCritical(uint32_t state)

  230. {

  231.     (void)state;

  232.     if (PlsrHostEmitPulseOnCriticalExit != 0U)

  233.     {

  234.         PlsrHostEmitPulseOnCriticalExit = 0U;

  235.         PlsrHostLatchPulse(PlsrHostSelectedPulse);

  236.     }

  237.     PlsrHostServicePendingPulse(PlsrHostSelectedPulse);

  238. }

  239. 

  240. void PlsrTestSetInput(uint8_t inputSelection, uint8_t level)

  241. {

  242.     if (inputSelection <= 1U)

  243.     {

  244.         PlsrHostInputs[inputSelection] = (level != 0U) ? 1U : 0U;

  245.     }

  246. }

  247. 

  248. void PlsrTestEmitPulses(uint32_t pulseCount)

  249. {

  250.     while ((pulseCount != 0UL)

  251.            && (PlsrHostPulseActive[PlsrHostSelectedPulse] != 0U))

  252.     {

  253.         PlsrHostLatchPulse(PlsrHostSelectedPulse);

  254.         PlsrHostServicePendingPulse(PlsrHostSelectedPulse);

  255.         pulseCount--;

  256.     }

  257. }

  258. 

  259. void PlsrTestEmitPulseOnCriticalEntry(void)

  260. {

  261.     PlsrHostCriticalEntriesToSkip = 0U;

  262.     PlsrHostEmitPulseOnCriticalEntry = 1U;

  263. }

  264. 

  265. void PlsrTestEmitPulseAfterCriticalEntries(uint8_t entriesToSkip)

  266. {

  267.     PlsrHostCriticalEntriesToSkip = entriesToSkip;

  268.     PlsrHostEmitPulseOnCriticalEntry = 1U;

  269. }

  270. 

  271. void PlsrTestEmitPulseOnCriticalExit(void)

  272. {

  273.     PlsrHostEmitPulseOnCriticalExit = 1U;

  274. }

  275. 

  276. void PlsrTestLatchPulseOnCriticalEntry(void)

  277. {

  278.     PlsrHostLatchPulseOnCriticalEntry = 1U;

  279. }

  280. 

  281. void PlsrTestServicePendingPulse(void)

  282. {

  283.     PlsrHostServicePendingPulse(PlsrHostSelectedPulse);

  284. }

  285. 

  286. void PlsrTestFailNextStart(void)

  287. {

  288.     PlsrHostFailNextStart = 1U;

  289. }

  290. 

  291. void PlsrTestFailNextFrequencyAtUpdate(void)

  292. {

  293.     PlsrHostFailNextFrequencyAtUpdate = 1U;

  294. }

  295. 

  296. uint8_t PlsrTestPulseIsActive(void)

  297. {

  298.     return PlsrHostPulseActive[PlsrHostSelectedPulse];

  299. }

  300. 

  301. uint32_t PlsrTestOutputFrequency(void)

  302. {

  303.     return PlsrHostFrequency[PlsrHostSelectedPulse];

  304. }

  305. 

  306. uint32_t PlsrTestQueuedFrequency(void)

  307. {

  308.     return PlsrHostQueuedFrequency[PlsrHostSelectedPulse];

  309. }

  310. 

  311. uint8_t PlsrTestDirectionLevel(void)

  312. {

  313.     return PlsrHostDirectionLevel;

  314. }

  315. 

  316. void PlsrTestClearPersistentStorage(void)

  317. {

  318.     (void)memset(&PlsrHostPersistentPayload, 0,

  319.                  sizeof(PlsrHostPersistentPayload));

  320.     (void)memset(PlsrHostInputs, 0, sizeof(PlsrHostInputs));

  321.     PlsrHostPersistentValid = 0U;

  322.     PlsrHostSaveCount = 0UL;

  323. }

  324. 

  325. void PlsrTestResetSaveCount(void)

  326. {

  327.     PlsrHostSaveCount = 0UL;

  328. }

  329. 

  330. uint32_t PlsrTestSaveCount(void)

  331. {

  332.     return PlsrHostSaveCount;

  333. }

  334. 

  335. #else

  336. 

  337. #include "stm32f4xx_hal.h"

  338. #include <stddef.h>

  339. #include <string.h>

  340. 

  341. #define PLSR_ENABLE_IRQ_CYCLE_DIAG (0U)

  342. 

  343. #define PLSR_FLASH_SLOT_A_ADDRESS      (0x080C0000UL)

  344. #define PLSR_FLASH_SLOT_B_ADDRESS      (0x080E0000UL)

  345. #define PLSR_FLASH_MAGIC               (0x50534C52UL)

  346. #define PLSR_FLASH_VERSION             (2U)

  347. #define PLSR_BACKUP_CONFIG_ADDRESS     (BKPSRAM_BASE + 0x0100UL)

  348. #define PLSR_BACKUP_POSITION_ADDRESS   (BKPSRAM_BASE + 0x0200UL)

  349. #define PLSR_BACKUP_CONFIG_MAGIC       (0x50434647UL)

  350. #define PLSR_BACKUP_POSITION_MAGIC     (0x50504F53UL)

  351. 

  352. typedef struct

  353. {

  354.     TIM_TypeDef *timer;

  355.     GPIO_TypeDef *port;

  356.     uint16_t pin;

  357.     uint8_t pinIndex;

  358.     uint8_t alternate;

  359.     IRQn_Type irq;

  360.     uint32_t timerClockHz;

  361. } PLSR_TIMER_MAP;

  362. 

  363. typedef struct

  364. {

  365.     GPIO_TypeDef *port;

  366.     uint16_t pin;

  367. } PLSR_GPIO_MAP;

  368. 

  369. typedef struct

  370. {

  371.     uint32_t prescaler;

  372.     uint32_t period;

  373.     uint32_t compare;

  374.     uint32_t actualFrequencyHz;

  375. } PLSR_TIMER_SETTING;

  376. 

  377. typedef struct

  378. {

  379.     uint32_t magic;

  380.     uint16_t version;

  381.     uint16_t payloadSize;

  382.     uint32_t generation;

  383.     PLSR_PERSIST_PAYLOAD payload;

  384.     uint32_t crc32;

  385. } PLSR_FLASH_RECORD;

  386. 

  387. typedef struct

  388. {

  389.     uint32_t magic;

  390.     PLSR_CONFIG config;

  391.     uint32_t crc32;

  392. } PLSR_BACKUP_CONFIG_RECORD;

  393. 

  394. typedef struct

  395. {

  396.     uint32_t magic;

  397.     uint32_t generation;

  398.     int32_t position;

  399.     uint8_t positionValid;

  400.     uint8_t wasBusy;

  401.     uint16_t reserved;

  402.     uint32_t crc32;

  403. } PLSR_BACKUP_POSITION_RECORD;

  404. 

  405. static const PLSR_TIMER_MAP PlsrTimerMap[4] =

  406. {

  407.     {TIM10, GPIOF, GPIO_PIN_6, 6U, GPIO_AF3_TIM10,

  408.      TIM1_UP_TIM10_IRQn, 168000000UL},

  409.     {TIM13, GPIOF, GPIO_PIN_8, 8U, GPIO_AF9_TIM13,

  410.      TIM8_UP_TIM13_IRQn, 84000000UL},

  411.     {TIM11, GPIOF, GPIO_PIN_7, 7U, GPIO_AF3_TIM11,

  412.      TIM1_TRG_COM_TIM11_IRQn, 168000000UL},

  413.     {TIM14, GPIOF, GPIO_PIN_9, 9U, GPIO_AF9_TIM14,

  414.      TIM8_TRG_COM_TIM14_IRQn, 84000000UL}

  415. };

  416. 

  417. static const PLSR_GPIO_MAP PlsrDirectionMap[4] =

  418. {

  419.     {GPIOH, GPIO_PIN_9},

  420.     {GPIOH, GPIO_PIN_8},

  421.     {GPIOH, GPIO_PIN_7},

  422.     {GPIOH, GPIO_PIN_6}

  423. };

  424. 

  425. static PLSR_FLASH_RECORD PlsrFlashRecordBuffer;

  426. static uint32_t PlsrBackupPositionGeneration;

  427. static uint32_t PlsrTimerActiveFrequencyHz[4];

  428. static uint32_t PlsrTimerQueuedFrequencyHz[4];

  429. static uint32_t PlsrTimerQueueGeneration[4];

  430. 

  431. static void PlsrHandleTimerIrq(uint8_t pulseOutput);

  432. 

  433. #if PLSR_ENABLE_IRQ_CYCLE_DIAG

  434. volatile uint32_t PlsrIrqCount[4];

  435. volatile uint32_t PlsrIrqLastCycles[4];

  436. volatile uint32_t PlsrIrqMaxCycles[4];

  437. #endif

  438. 

  439. static uint32_t PlsrCrc32(const void *data, uint32_t length)

  440. {

  441.     const uint8_t *bytes = (const uint8_t *)data;

  442.     uint32_t crc = 0xFFFFFFFFUL;

  443.     uint32_t index;

  444.     uint8_t bit;

  445. 

  446.     for (index = 0UL; index < length; index++)

  447.     {

  448.         crc ^= bytes[index];

  449.         for (bit = 0U; bit < 8U; bit++)

  450.         {

  451.             crc = ((crc & 1UL) != 0UL) ? ((crc >> 1U) ^ 0xEDB88320UL)

  452.                                            : (crc >> 1U);

  453.         }

  454.     }

  455.     return ~crc;

  456. }

  457. 

  458. static uint8_t PlsrGenerationIsNewer(uint32_t first, uint32_t second)

  459. {

  460.     return ((int32_t)(first - second) > 0) ? 1U : 0U;

  461. }

  462. 

  463. static uint32_t PlsrFlashRecordCrc(const PLSR_FLASH_RECORD *record)

  464. {

  465.     const uint8_t *start = (const uint8_t *)&record->version;

  466.     uint32_t length = (uint32_t)(offsetof(PLSR_FLASH_RECORD, crc32)

  467.                                  - offsetof(PLSR_FLASH_RECORD, version));

  468.     return PlsrCrc32(start, length);

  469. }

  470. 

  471. static uint8_t PlsrFlashRecordIsValid(const PLSR_FLASH_RECORD *record)

  472. {

  473.     return ((record->magic == PLSR_FLASH_MAGIC)

  474.             && (record->version == PLSR_FLASH_VERSION)

  475.             && (record->payloadSize == sizeof(PLSR_PERSIST_PAYLOAD))

  476.             && (record->crc32 == PlsrFlashRecordCrc(record))) ? 1U : 0U;

  477. }

  478. 

  479. static uint8_t PlsrBackupConfigIsValid(

  480.     const PLSR_BACKUP_CONFIG_RECORD *record)

  481. {

  482.     return ((record->magic == PLSR_BACKUP_CONFIG_MAGIC)

  483.             && (record->crc32

  484.                 == PlsrCrc32(&record->config, sizeof(record->config)))) ? 1U : 0U;

  485. }

  486. 

  487. static uint8_t PlsrBackupPositionIsValid(

  488.     const PLSR_BACKUP_POSITION_RECORD *record)

  489. {

  490.     uint32_t crc = PlsrCrc32(&record->generation,

  491.                              sizeof(record->generation)

  492.                              + sizeof(record->position)

  493.                              + sizeof(record->positionValid)

  494.                              + sizeof(record->wasBusy)

  495.                              + sizeof(record->reserved));

  496.     return ((record->magic == PLSR_BACKUP_POSITION_MAGIC)

  497.             && (record->crc32 == crc)) ? 1U : 0U;

  498. }

  499. 

  500. static const PLSR_BACKUP_POSITION_RECORD *PlsrNewestBackupPosition(void)

  501. {

  502.     const PLSR_BACKUP_POSITION_RECORD *slots =

  503.         (const PLSR_BACKUP_POSITION_RECORD *)PLSR_BACKUP_POSITION_ADDRESS;

  504.     uint8_t validA = PlsrBackupPositionIsValid(&slots[0]);

  505.     uint8_t validB = PlsrBackupPositionIsValid(&slots[1]);

  506. 

  507.     if ((validA == 0U) && (validB == 0U))

  508.     {

  509.         return NULL;

  510.     }

  511.     if (validA == 0U)

  512.     {

  513.         return &slots[1];

  514.     }

  515.     if (validB == 0U)

  516.     {

  517.         return &slots[0];

  518.     }

  519.     return (PlsrGenerationIsNewer(slots[1].generation,

  520.                                   slots[0].generation) != 0U)

  521.                ? &slots[1] : &slots[0];

  522. }

  523. 

  524. static void PlsrTimerStop(TIM_TypeDef *timer)

  525. {

  526.     timer->DIER &= ~TIM_DIER_UIE;

  527.     timer->CR1 &= ~TIM_CR1_CEN;

  528.     timer->CCER &= ~TIM_CCER_CC1E;

  529.     timer->SR = ~TIM_SR_UIF;

  530. }

  531. 

  532. static void PlsrTimerInitialize(TIM_TypeDef *timer)

  533. {

  534.     timer->CR1 = TIM_CR1_ARPE | TIM_CR1_URS;

  535.     timer->CR2 = 0UL;

  536.     timer->SMCR = 0UL;

  537.     timer->DIER = 0UL;

  538.     timer->CCMR1 = TIM_CCMR1_OC1PE | (6UL << TIM_CCMR1_OC1M_Pos);

  539.     timer->CCER = 0UL;

  540.     timer->PSC = 0UL;

  541.     timer->ARR = 999UL;

  542.     timer->CCR1 = 500UL;

  543.     timer->CNT = 0UL;

  544.     timer->EGR = TIM_EGR_UG;

  545.     timer->SR = 0UL;

  546. }

  547. 

  548. static void PlsrPulsePinHoldIdle(uint8_t pulseOutput)

  549. {

  550.     const PLSR_TIMER_MAP *map = &PlsrTimerMap[pulseOutput];

  551.     GPIO_InitTypeDef gpio;

  552. 

  553.     HAL_GPIO_WritePin(map->port, map->pin, GPIO_PIN_SET);

  554.     gpio.Pin = map->pin;

  555.     gpio.Mode = GPIO_MODE_OUTPUT_PP;

  556.     gpio.Pull = GPIO_NOPULL;

  557.     gpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH;

  558.     gpio.Alternate = 0U;

  559.     HAL_GPIO_Init(map->port, &gpio);

  560. }

  561. 

  562. static void PlsrPulsePinCaptureIdle(uint8_t pulseOutput)

  563. {

  564.     const PLSR_TIMER_MAP *map = &PlsrTimerMap[pulseOutput];

  565.     uint32_t shift = (uint32_t)map->pinIndex * 2UL;

  566.     uint32_t mode = map->port->MODER;

  567. 

  568.     /* The update IRQ occurs while PWM is high; switch to GPIO high first. */

  569.     map->port->BSRR = map->pin;

  570.     mode &= ~(3UL << shift);

  571.     mode |= 1UL << shift;

  572.     map->port->MODER = mode;

  573.     __DSB();

  574. }

  575. 

  576. static void PlsrPulsePinRelease(uint8_t pulseOutput)

  577. {

  578.     const PLSR_TIMER_MAP *map = &PlsrTimerMap[pulseOutput];

  579.     GPIO_InitTypeDef gpio;

  580. 

  581.     gpio.Pin = map->pin;

  582.     gpio.Mode = GPIO_MODE_AF_PP;

  583.     gpio.Pull = GPIO_NOPULL;

  584.     gpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH;

  585.     gpio.Alternate = map->alternate;

  586.     HAL_GPIO_Init(map->port, &gpio);

  587.     __DSB();

  588. }

  589. 

  590. static uint8_t PlsrTimerCalculate(uint8_t pulseOutput,

  591.                                   uint32_t frequencyHz,

  592.                                   PLSR_TIMER_SETTING *setting)

  593. {

  594.     const PLSR_TIMER_MAP *map;

  595.     uint32_t prescalerDivider;

  596.     uint32_t denominator;

  597.     uint32_t periodCounts;

  598. 

  599.     if ((pulseOutput > 3U) || (frequencyHz == 0UL)

  600.         || (frequencyHz > PLSR_FREQUENCY_MAX_HZ)

  601.         || (setting == NULL))

  602.     {

  603.         return 0U;

  604.     }

  605. 

  606.     map = &PlsrTimerMap[pulseOutput];

  607.     prescalerDivider = (((map->timerClockHz - 1UL) / frequencyHz) >> 16U)

  608.                        + 1UL;

  609.     if (prescalerDivider > 65536UL)

  610.     {

  611.         return 0U;

  612.     }

  613.     denominator = prescalerDivider * frequencyHz;

  614.     periodCounts = (map->timerClockHz + denominator / 2UL) / denominator;

  615.     if (periodCounts < 2UL)

  616.     {

  617.         periodCounts = 2UL;

  618.     }

  619.     if (periodCounts > 65536UL)

  620.     {

  621.         periodCounts = 65536UL;

  622.     }

  623. 

  624.     setting->prescaler = prescalerDivider - 1UL;

  625.     setting->period = periodCounts - 1UL;

  626.     setting->compare = periodCounts / 2UL;

  627.     setting->actualFrequencyHz =

  628.         map->timerClockHz / (prescalerDivider * periodCounts);

  629.     return 1U;

  630. }

  631. 

  632. static void PlsrTimerWriteSetting(TIM_TypeDef *timer,

  633.                                   const PLSR_TIMER_SETTING *setting)

  634. {

  635.     timer->PSC = setting->prescaler;

  636.     timer->ARR = setting->period;

  637.     timer->CCR1 = setting->compare;

  638. }

  639. 

  640. uint8_t PlsrPlatformInit(void)

  641. {

  642.     GPIO_InitTypeDef gpio;

  643.     uint8_t index;

  644.     const PLSR_BACKUP_POSITION_RECORD *positionRecord;

  645. 

  646.     __HAL_RCC_GPIOB_CLK_ENABLE();

  647.     __HAL_RCC_GPIOF_CLK_ENABLE();

  648.     __HAL_RCC_GPIOG_CLK_ENABLE();

  649.     __HAL_RCC_GPIOH_CLK_ENABLE();

  650.     __HAL_RCC_TIM10_CLK_ENABLE();

  651.     __HAL_RCC_TIM11_CLK_ENABLE();

  652.     __HAL_RCC_TIM13_CLK_ENABLE();

  653.     __HAL_RCC_TIM14_CLK_ENABLE();

  654.     __HAL_RCC_PWR_CLK_ENABLE();

  655.     HAL_PWR_EnableBkUpAccess();

  656.     __HAL_RCC_BKPSRAM_CLK_ENABLE();

  657.     if (HAL_PWREx_EnableBkUpReg() != HAL_OK)

  658.     {

  659.         return 0U;

  660.     }

  661. 

  662. #if PLSR_ENABLE_IRQ_CYCLE_DIAG

  663.     CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;

  664.     DWT->CYCCNT = 0UL;

  665.     DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;

  666.     (void)memset((void *)PlsrIrqCount, 0, sizeof(PlsrIrqCount));

  667.     (void)memset((void *)PlsrIrqLastCycles, 0, sizeof(PlsrIrqLastCycles));

  668.     (void)memset((void *)PlsrIrqMaxCycles, 0, sizeof(PlsrIrqMaxCycles));

  669. #endif

  670. 

  671.     HAL_GPIO_WritePin(GPIOH, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8

  672.                               | GPIO_PIN_9, GPIO_PIN_SET);

  673.     gpio.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9;

  674.     gpio.Mode = GPIO_MODE_OUTPUT_PP;

  675.     gpio.Pull = GPIO_NOPULL;

  676.     gpio.Speed = GPIO_SPEED_FREQ_HIGH;

  677.     gpio.Alternate = 0U;

  678.     HAL_GPIO_Init(GPIOH, &gpio);

  679. 

  680.     gpio.Mode = GPIO_MODE_INPUT;

  681.     gpio.Pull = GPIO_NOPULL;

  682.     gpio.Speed = GPIO_SPEED_FREQ_LOW;

  683.     gpio.Alternate = 0U;

  684.     gpio.Pin = GPIO_PIN_5;

  685.     HAL_GPIO_Init(GPIOB, &gpio);

  686.     gpio.Pin = GPIO_PIN_12;

  687.     HAL_GPIO_Init(GPIOG, &gpio);

  688. 

  689.     for (index = 0U; index < 4U; index++)

  690.     {

  691.         PlsrTimerActiveFrequencyHz[index] = 0UL;

  692.         PlsrTimerQueuedFrequencyHz[index] = 0UL;

  693.         PlsrTimerQueueGeneration[index] = 0UL;

  694.         PlsrTimerInitialize(PlsrTimerMap[index].timer);

  695.         PlsrPulsePinHoldIdle(index);

  696.         HAL_NVIC_SetPriority(PlsrTimerMap[index].irq, 1U, 0U);

  697.         HAL_NVIC_EnableIRQ(PlsrTimerMap[index].irq);

  698.     }

  699. 

  700.     positionRecord = PlsrNewestBackupPosition();

  701.     PlsrBackupPositionGeneration =

  702.         (positionRecord == NULL) ? 0UL : positionRecord->generation;

  703.     return 1U;

  704. }

  705. 

  706. uint8_t PlsrPlatformPrepare(uint8_t pulseOutput,

  707.                             uint8_t directionOutput,

  708.                             uint8_t directionLevel)

  709. {

  710.     uint8_t index;

  711. 

  712.     if ((pulseOutput > 3U) || (directionOutput > 3U))

  713.     {

  714.         return 0U;

  715.     }

  716.     for (index = 0U; index < 4U; index++)

  717.     {

  718.         PlsrPulsePinHoldIdle(index);

  719.         PlsrTimerStop(PlsrTimerMap[index].timer);

  720.         HAL_GPIO_WritePin(PlsrDirectionMap[index].port,

  721.                           PlsrDirectionMap[index].pin,

  722.                           GPIO_PIN_SET);

  723.     }

  724.     if (directionLevel != 0U)

  725.     {

  726.         HAL_GPIO_WritePin(PlsrDirectionMap[directionOutput].port,

  727.                           PlsrDirectionMap[directionOutput].pin,

  728.                           GPIO_PIN_RESET);

  729.     }

  730.     return 1U;

  731. }

  732. 

  733. uint8_t PlsrPlatformStartPulse(uint8_t pulseOutput,

  734.                                uint32_t firstFrequencyHz,

  735.                                uint32_t queuedFrequencyHz,

  736.                                uint32_t *actualFirstFrequencyHz,

  737.                                uint32_t *actualQueuedFrequencyHz)

  738. {

  739.     TIM_TypeDef *timer;

  740.     PLSR_TIMER_SETTING firstSetting;

  741.     PLSR_TIMER_SETTING queuedSetting;

  742. 

  743.     if ((actualFirstFrequencyHz == NULL)

  744.         || (actualQueuedFrequencyHz == NULL)

  745.         || (PlsrTimerCalculate(pulseOutput, firstFrequencyHz,

  746.                                &firstSetting) == 0U)

  747.         || (PlsrTimerCalculate(pulseOutput, queuedFrequencyHz,

  748.                                &queuedSetting) == 0U))

  749.     {

  750.         return 0U;

  751.     }

  752.     timer = PlsrTimerMap[pulseOutput].timer;

  753.     timer->DIER &= ~TIM_DIER_UIE;

  754.     timer->CR1 &= ~TIM_CR1_CEN;

  755.     timer->CCER &= ~TIM_CCER_CC1E;

  756.     timer->CNT = 0UL;

  757.     PlsrTimerWriteSetting(timer, &firstSetting);

  758.     timer->EGR = TIM_EGR_UG;

  759.     PlsrTimerWriteSetting(timer, &queuedSetting);

  760.     timer->SR = 0UL;

  761.     timer->CCER |= TIM_CCER_CC1E;

  762.     __DSB();

  763.     timer->DIER |= TIM_DIER_UIE;

  764.     PlsrPulsePinRelease(pulseOutput);

  765.     timer->CR1 |= TIM_CR1_CEN;

  766.     PlsrTimerActiveFrequencyHz[pulseOutput] =

  767.         firstSetting.actualFrequencyHz;

  768.     PlsrTimerQueuedFrequencyHz[pulseOutput] =

  769.         queuedSetting.actualFrequencyHz;

  770.     PlsrTimerQueueGeneration[pulseOutput]++;

  771.     *actualFirstFrequencyHz = firstSetting.actualFrequencyHz;

  772.     *actualQueuedFrequencyHz = queuedSetting.actualFrequencyHz;

  773.     return 1U;

  774. }

  775. 

  776. uint8_t PlsrPlatformQueueFrequency(uint8_t pulseOutput,

  777.                                    uint32_t frequencyHz,

  778.                                    uint32_t *actualFrequencyHz)

  779. {

  780.     TIM_TypeDef *timer;

  781.     PLSR_TIMER_SETTING setting;

  782.     uint32_t counterBefore;

  783.     uint32_t counterAfter;

  784.     uint32_t counterFinal;

  785.     uint32_t criticalState;

  786.     uint32_t generationBefore;

  787.     uint32_t ownGeneration;

  788.     uint8_t wrappedWhileUpdatesDisabled;

  789. 

  790.     if ((pulseOutput > 3U) || (actualFrequencyHz == NULL)

  791.         || (PlsrTimerCalculate(pulseOutput, frequencyHz, &setting) == 0U))

  792.     {

  793.         return 0U;

  794.     }

  795.     timer = PlsrTimerMap[pulseOutput].timer;

  796.     if ((timer->CR1 & TIM_CR1_CEN) == 0UL)

  797.     {

  798.         return 0U;

  799.     }

  800. 

  801.     criticalState = PlsrPlatformEnterCritical();

  802.     generationBefore = PlsrTimerQueueGeneration[pulseOutput];

  803.     if ((timer->SR & TIM_SR_UIF) != 0UL)

  804.     {

  805.         PlsrHandleTimerIrq(pulseOutput);

  806.         if (PlsrTimerQueueGeneration[pulseOutput] != generationBefore)

  807.         {

  808.             *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput];

  809.             PlsrPlatformExitCritical(criticalState);

  810.             return 1U;

  811.         }

  812.         if ((timer->CR1 & TIM_CR1_CEN) == 0UL)

  813.         {

  814.             PlsrPlatformExitCritical(criticalState);

  815.             return 0U;

  816.         }

  817.     }

  818. 

  819.     /* UDIS blocks shadow transfers while the three preload registers are

  820.        replaced. The counter and PWM output continue without interruption. */

  821.     counterBefore = timer->CNT;

  822.     timer->CR1 |= TIM_CR1_UDIS;

  823.     __DMB();

  824.     if ((timer->SR & TIM_SR_UIF) != 0UL)

  825.     {

  826.         timer->CR1 &= ~TIM_CR1_UDIS;

  827.         PlsrHandleTimerIrq(pulseOutput);

  828.         if ((PlsrTimerQueueGeneration[pulseOutput] != generationBefore)

  829.             || ((timer->CR1 & TIM_CR1_CEN) == 0UL))

  830.         {

  831.             uint8_t stillRunning =

  832.                 ((timer->CR1 & TIM_CR1_CEN) != 0UL) ? 1U : 0U;

  833. 

  834.             *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput];

  835.             PlsrPlatformExitCritical(criticalState);

  836.             return stillRunning;

  837.         }

  838.         counterBefore = timer->CNT;

  839.         timer->CR1 |= TIM_CR1_UDIS;

  840.         __DMB();

  841.     }

  842.     PlsrTimerWriteSetting(timer, &setting);

  843.     __DMB();

  844.     PlsrTimerQueuedFrequencyHz[pulseOutput] = setting.actualFrequencyHz;

  845.     PlsrTimerQueueGeneration[pulseOutput]++;

  846.     ownGeneration = PlsrTimerQueueGeneration[pulseOutput];

  847.     counterAfter = timer->CNT;

  848.     timer->CR1 &= ~TIM_CR1_UDIS;

  849.     __DMB();

  850.     counterFinal = timer->CNT;

  851. 

  852.     /* With UDIS set an overflow does not set UIF. A wrapped counter proves

  853.        that its real output edge occurred, so account for that edge once. */

  854.     wrappedWhileUpdatesDisabled =

  855.         ((counterAfter < counterBefore)

  856.          || ((counterFinal < counterAfter)

  857.              && ((timer->SR & TIM_SR_UIF) == 0UL))) ? 1U : 0U;

  858.     if (wrappedWhileUpdatesDisabled != 0U)

  859.     {

  860.         PlsrPulseTimerIrq(pulseOutput);

  861.     }

  862.     else if ((timer->SR & TIM_SR_UIF) != 0UL)

  863.     {

  864.         PlsrHandleTimerIrq(pulseOutput);

  865.     }

  866.     *actualFrequencyHz =

  867.         (PlsrTimerQueueGeneration[pulseOutput] == ownGeneration)

  868.             ? setting.actualFrequencyHz

  869.             : PlsrTimerQueuedFrequencyHz[pulseOutput];

  870.     PlsrPlatformExitCritical(criticalState);

  871.     return 1U;

  872. }

  873. 

  874. void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput)

  875. {

  876.     if (pulseOutput <= 3U)

  877.     {

  878.         PlsrHandleTimerIrq(pulseOutput);

  879.     }

  880. }

  881. 

  882. uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput)

  883. {

  884.     return (pulseOutput <= 3U)

  885.                ? PlsrTimerActiveFrequencyHz[pulseOutput] : 0UL;

  886. }

  887. 

  888. void PlsrPlatformStopPulse(uint8_t pulseOutput)

  889. {

  890.     if (pulseOutput <= 3U)

  891.     {

  892.         PlsrPulsePinCaptureIdle(pulseOutput);

  893.         PlsrTimerStop(PlsrTimerMap[pulseOutput].timer);

  894.         PlsrTimerActiveFrequencyHz[pulseOutput] = 0UL;

  895.         PlsrTimerQueuedFrequencyHz[pulseOutput] = 0UL;

  896.         PlsrTimerQueueGeneration[pulseOutput]++;

  897.     }

  898. }

  899. 

  900. uint8_t PlsrPlatformReadInput(uint8_t inputSelection)

  901. {

  902.     if (inputSelection == 0U)

  903.     {

  904.         return (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_5) == GPIO_PIN_SET) ? 1U : 0U;

  905.     }

  906.     if (inputSelection == 1U)

  907.     {

  908.         return (HAL_GPIO_ReadPin(GPIOG, GPIO_PIN_12) == GPIO_PIN_SET) ? 1U : 0U;

  909.     }

  910.     return 0U;

  911. }

  912. 

  913. uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload)

  914. {

  915.     const PLSR_FLASH_RECORD *slotA =

  916.         (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_A_ADDRESS;

  917.     const PLSR_FLASH_RECORD *slotB =

  918.         (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_B_ADDRESS;

  919.     const PLSR_FLASH_RECORD *selected = NULL;

  920.     const PLSR_BACKUP_CONFIG_RECORD *backupConfig =

  921.         (const PLSR_BACKUP_CONFIG_RECORD *)PLSR_BACKUP_CONFIG_ADDRESS;

  922.     const PLSR_BACKUP_POSITION_RECORD *backupPosition;

  923.     uint8_t validA;

  924.     uint8_t validB;

  925.     uint8_t haveConfig = 0U;

  926. 

  927.     if (payload == NULL)

  928.     {

  929.         return 0U;

  930.     }

  931. 

  932.     validA = PlsrFlashRecordIsValid(slotA);

  933.     validB = PlsrFlashRecordIsValid(slotB);

  934.     if ((validA != 0U) && (validB != 0U))

  935.     {

  936.         selected = (PlsrGenerationIsNewer(slotB->generation,

  937.                                           slotA->generation) != 0U)

  938.                        ? slotB : slotA;

  939.     }

  940.     else if (validA != 0U)

  941.     {

  942.         selected = slotA;

  943.     }

  944.     else if (validB != 0U)

  945.     {

  946.         selected = slotB;

  947.     }

  948. 

  949.     if (selected != NULL)

  950.     {

  951.         *payload = selected->payload;

  952.         haveConfig = 1U;

  953.     }

  954.     else

  955.     {

  956.         (void)memset(payload, 0, sizeof(*payload));

  957.     }

  958. 

  959.     if (PlsrBackupConfigIsValid(backupConfig) != 0U)

  960.     {

  961.         payload->config = backupConfig->config;

  962.         haveConfig = 1U;

  963.     }

  964.     backupPosition = PlsrNewestBackupPosition();

  965.     if (backupPosition != NULL)

  966.     {

  967.         payload->position = backupPosition->position;

  968.         payload->positionValid = backupPosition->positionValid;

  969.         payload->wasBusy = backupPosition->wasBusy;

  970.     }

  971.     return haveConfig;

  972. }

  973. 

  974. uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload)

  975. {

  976.     const PLSR_FLASH_RECORD *slotA =

  977.         (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_A_ADDRESS;

  978.     const PLSR_FLASH_RECORD *slotB =

  979.         (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_B_ADDRESS;

  980.     uint8_t validA;

  981.     uint8_t validB;

  982.     uint32_t newestGeneration = 0UL;

  983.     uint32_t targetAddress;

  984.     uint32_t targetSector;

  985.     uint32_t sectorError;

  986.     uint32_t index;

  987.     uint32_t wordCount;

  988.     const uint32_t *words;

  989.     FLASH_EraseInitTypeDef erase;

  990.     HAL_StatusTypeDef status = HAL_OK;

  991. 

  992.     if (payload == NULL)

  993.     {

  994.         return 0U;

  995.     }

  996. 

  997.     validA = PlsrFlashRecordIsValid(slotA);

  998.     validB = PlsrFlashRecordIsValid(slotB);

  999.     if ((validA != 0U) && (validB != 0U))

  1000.     {

  1001.         if (PlsrGenerationIsNewer(slotB->generation, slotA->generation) != 0U)

  1002.         {

  1003.             newestGeneration = slotB->generation;

  1004.             targetAddress = PLSR_FLASH_SLOT_A_ADDRESS;

  1005.             targetSector = FLASH_SECTOR_10;

  1006.         }

  1007.         else

  1008.         {

  1009.             newestGeneration = slotA->generation;

  1010.             targetAddress = PLSR_FLASH_SLOT_B_ADDRESS;

  1011.             targetSector = FLASH_SECTOR_11;

  1012.         }

  1013.     }

  1014.     else if (validA != 0U)

  1015.     {

  1016.         newestGeneration = slotA->generation;

  1017.         targetAddress = PLSR_FLASH_SLOT_B_ADDRESS;

  1018.         targetSector = FLASH_SECTOR_11;

  1019.     }

  1020.     else if (validB != 0U)

  1021.     {

  1022.         newestGeneration = slotB->generation;

  1023.         targetAddress = PLSR_FLASH_SLOT_A_ADDRESS;

  1024.         targetSector = FLASH_SECTOR_10;

  1025.     }

  1026.     else

  1027.     {

  1028.         targetAddress = PLSR_FLASH_SLOT_A_ADDRESS;

  1029.         targetSector = FLASH_SECTOR_10;

  1030.     }

  1031. 

  1032.     (void)memset(&PlsrFlashRecordBuffer, 0, sizeof(PlsrFlashRecordBuffer));

  1033.     PlsrFlashRecordBuffer.magic = PLSR_FLASH_MAGIC;

  1034.     PlsrFlashRecordBuffer.version = PLSR_FLASH_VERSION;

  1035.     PlsrFlashRecordBuffer.payloadSize = sizeof(PLSR_PERSIST_PAYLOAD);

  1036.     PlsrFlashRecordBuffer.generation = newestGeneration + 1UL;

  1037.     PlsrFlashRecordBuffer.payload = *payload;

  1038.     PlsrFlashRecordBuffer.crc32 = PlsrFlashRecordCrc(&PlsrFlashRecordBuffer);

  1039. 

  1040.     if (HAL_FLASH_Unlock() != HAL_OK)

  1041.     {

  1042.         return 0U;

  1043.     }

  1044.     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR

  1045.                            | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR

  1046.                            | FLASH_FLAG_PGSERR);

  1047.     erase.TypeErase = FLASH_TYPEERASE_SECTORS;

  1048.     erase.VoltageRange = FLASH_VOLTAGE_RANGE_3;

  1049.     erase.Sector = targetSector;

  1050.     erase.NbSectors = 1U;

  1051.     if (HAL_FLASHEx_Erase(&erase, &sectorError) != HAL_OK)

  1052.     {

  1053.         status = HAL_ERROR;

  1054.     }

  1055. 

  1056.     words = (const uint32_t *)&PlsrFlashRecordBuffer;

  1057.     wordCount = sizeof(PlsrFlashRecordBuffer) / sizeof(uint32_t);

  1058.     if (status == HAL_OK)

  1059.     {

  1060.         for (index = 1UL; index < wordCount; index++)

  1061.         {

  1062.             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD,

  1063.                                   targetAddress + index * 4UL,

  1064.                                   words[index]) != HAL_OK)

  1065.             {

  1066.                 status = HAL_ERROR;

  1067.                 break;

  1068.             }

  1069.         }

  1070.     }

  1071.     if ((status == HAL_OK)

  1072.         && (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, targetAddress,

  1073.                               PLSR_FLASH_MAGIC) != HAL_OK))

  1074.     {

  1075.         status = HAL_ERROR;

  1076.     }

  1077.     if (HAL_FLASH_Lock() != HAL_OK)

  1078.     {

  1079.         status = HAL_ERROR;

  1080.     }

  1081. 

  1082.     if ((status == HAL_OK)

  1083.         && (PlsrFlashRecordIsValid(

  1084.                 (const PLSR_FLASH_RECORD *)targetAddress) != 0U))

  1085.     {

  1086.         return 1U;

  1087.     }

  1088.     return 0U;

  1089. }

  1090. 

  1091. void PlsrPlatformCheckpointConfig(const PLSR_CONFIG *config)

  1092. {

  1093.     PLSR_BACKUP_CONFIG_RECORD *record =

  1094.         (PLSR_BACKUP_CONFIG_RECORD *)PLSR_BACKUP_CONFIG_ADDRESS;

  1095. 

  1096.     if (config == NULL)

  1097.     {

  1098.         return;

  1099.     }

  1100.     record->magic = 0UL;

  1101.     record->config = *config;

  1102.     record->crc32 = PlsrCrc32(&record->config, sizeof(record->config));

  1103.     __DMB();

  1104.     record->magic = PLSR_BACKUP_CONFIG_MAGIC;

  1105.     __DMB();

  1106. }

  1107. 

  1108. void PlsrPlatformCheckpointPosition(int32_t position,

  1109.                                     uint8_t positionValid,

  1110.                                     uint8_t wasBusy)

  1111. {

  1112.     PLSR_BACKUP_POSITION_RECORD *slots =

  1113.         (PLSR_BACKUP_POSITION_RECORD *)PLSR_BACKUP_POSITION_ADDRESS;

  1114.     PLSR_BACKUP_POSITION_RECORD *record;

  1115. 

  1116.     PlsrBackupPositionGeneration++;

  1117.     record = &slots[PlsrBackupPositionGeneration & 1UL];

  1118.     record->magic = 0UL;

  1119.     record->generation = PlsrBackupPositionGeneration;

  1120.     record->position = position;

  1121.     record->positionValid = (positionValid != 0U) ? 1U : 0U;

  1122.     record->wasBusy = (wasBusy != 0U) ? 1U : 0U;

  1123.     record->reserved = 0U;

  1124.     record->crc32 = PlsrCrc32(&record->generation,

  1125.                               sizeof(record->generation)

  1126.                               + sizeof(record->position)

  1127.                               + sizeof(record->positionValid)

  1128.                               + sizeof(record->wasBusy)

  1129.                               + sizeof(record->reserved));

  1130.     __DMB();

  1131.     record->magic = PLSR_BACKUP_POSITION_MAGIC;

  1132.     __DMB();

  1133. }

  1134. 

  1135. uint32_t PlsrPlatformEnterCritical(void)

  1136. {

  1137.     uint32_t state = __get_PRIMASK();

  1138.     __disable_irq();

  1139.     __DMB();

  1140.     return state;

  1141. }

  1142. 

  1143. void PlsrPlatformExitCritical(uint32_t state)

  1144. {

  1145.     __DMB();

  1146.     if (state == 0UL)

  1147.     {

  1148.         __enable_irq();

  1149.     }

  1150. }

  1151. 

  1152. static void PlsrHandleTimerIrq(uint8_t pulseOutput)

  1153. {

  1154.     TIM_TypeDef *timer = PlsrTimerMap[pulseOutput].timer;

  1155. #if PLSR_ENABLE_IRQ_CYCLE_DIAG

  1156.     uint32_t startedAt;

  1157.     uint32_t elapsedCycles;

  1158. #endif

  1159. 

  1160.     if (((timer->SR & TIM_SR_UIF) != 0UL)

  1161.         && ((timer->DIER & TIM_DIER_UIE) != 0UL))

  1162.     {

  1163. #if PLSR_ENABLE_IRQ_CYCLE_DIAG

  1164.         startedAt = DWT->CYCCNT;

  1165. #endif

  1166.         timer->SR = ~TIM_SR_UIF;

  1167.         PlsrTimerActiveFrequencyHz[pulseOutput] =

  1168.             PlsrTimerQueuedFrequencyHz[pulseOutput];

  1169.         PlsrPulseTimerIrq(pulseOutput);

  1170. #if PLSR_ENABLE_IRQ_CYCLE_DIAG

  1171.         elapsedCycles = DWT->CYCCNT - startedAt;

  1172.         PlsrIrqCount[pulseOutput]++;

  1173.         PlsrIrqLastCycles[pulseOutput] = elapsedCycles;

  1174.         if (elapsedCycles > PlsrIrqMaxCycles[pulseOutput])

  1175.         {

  1176.             PlsrIrqMaxCycles[pulseOutput] = elapsedCycles;

  1177.         }

  1178. #endif

  1179.     }

  1180. }

  1181. 

  1182. void TIM1_UP_TIM10_IRQHandler(void)

  1183. {

  1184.     PlsrHandleTimerIrq(0U);

  1185. }

  1186. 

  1187. void TIM8_UP_TIM13_IRQHandler(void)

  1188. {

  1189.     PlsrHandleTimerIrq(1U);

  1190. }

  1191. 

  1192. void TIM1_TRG_COM_TIM11_IRQHandler(void)

  1193. {

  1194.     PlsrHandleTimerIrq(2U);

  1195. }

  1196. 

  1197. void TIM8_TRG_COM_TIM14_IRQHandler(void)

  1198. {

  1199.     PlsrHandleTimerIrq(3U);

  1200. }

  1201. 

  1202. #endif /* PLSR_HOST_TEST */