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Modbus-rtu/PLSR/Test/test_plsr_hal.c

1319 wiersze
44 KiB
Czysty Wina Historia 

  1. #include "plc_device.h"

  2. #include "plsr_core.h"

  3. #include "plsr_hal_f407.h"

  4. #include "plsr_job.h"

  5. #include "plsr_persistence.h"

  6. #include "plsr_self_test.h"

  7. #include <stdio.h>

  8. #include <string.h>

  9. 

  10. #define TEST_WORD_CAPACITY  (3000U)

  11. #define TEST_BIT_CAPACITY   (128U)

  12. #define TEST_S0_BASE        (100U)

  13. #define TEST_S1_BASE        (200U)

  14. 

  15. typedef struct

  16. {

  17.     uint16_t words[3][TEST_WORD_CAPACITY];

  18.     uint8_t bits[3][TEST_BIT_CAPACITY];

  19. } TEST_MEMORY;

  20. 

  21. static int TestFailures;

  22. static int TestChecks;

  23. 

  24. #define CHECK(condition)                                                     \

  25.     do                                                                       \

  26.     {                                                                        \

  27.         TestChecks++;                                                        \

  28.         if (!(condition))                                                    \

  29.         {                                                                    \

  30.             TestFailures++;                                                  \

  31.             (void)printf("FAIL line %d: %s\n", __LINE__, #condition);       \

  32.         }                                                                    \

  33.     } while (0)

  34. 

  35. static uint8_t TestValidateWords(void *context,

  36.                                  PLSR_DEVICE_TYPE device,

  37.                                  uint32_t firstAddress,

  38.                                  uint32_t wordCount)

  39. {

  40.     (void)context;

  41.     (void)device;

  42.     return (((uint64_t)firstAddress + wordCount) <= TEST_WORD_CAPACITY)

  43.                ? 1U

  44.                : 0U;

  45. }

  46. 

  47. static uint8_t TestReadWord(void *context,

  48.                             PLSR_DEVICE_TYPE device,

  49.                             uint32_t address,

  50.                             uint16_t *value)

  51. {

  52.     TEST_MEMORY *memory = (TEST_MEMORY *)context;

  53. 

  54.     if ((memory == NULL) || (value == NULL) || (device > PLSR_DEVICE_FD)

  55.         || (address >= TEST_WORD_CAPACITY))

  56.     {

  57.         return 0U;

  58.     }

  59.     *value = memory->words[device][address];

  60.     return 1U;

  61. }

  62. 

  63. static uint8_t TestReadBit(void *context,

  64.                            PLSR_DEVICE_TYPE device,

  65.                            uint32_t address,

  66.                            uint8_t *value)

  67. {

  68.     TEST_MEMORY *memory = (TEST_MEMORY *)context;

  69.     uint8_t index;

  70. 

  71.     if ((memory == NULL) || (value == NULL) || (device < PLSR_DEVICE_X)

  72.         || (device > PLSR_DEVICE_HM) || (address >= TEST_BIT_CAPACITY))

  73.     {

  74.         return 0U;

  75.     }

  76.     index = (uint8_t)(device - PLSR_DEVICE_X);

  77.     *value = memory->bits[index][address];

  78.     return 1U;

  79. }

  80. 

  81. static void TestWriteDword(TEST_MEMORY *memory,

  82.                            PLSR_DEVICE_TYPE device,

  83.                            uint32_t address,

  84.                            int32_t value)

  85. {

  86.     uint32_t raw = (uint32_t)value;

  87. 

  88.     memory->words[device][address] = (uint16_t)(raw & 0xFFFFUL);

  89.     memory->words[device][address + 1UL] = (uint16_t)(raw >> 16U);

  90. }

  91. 

  92. static void TestWriteSfdDword(uint16_t address, uint32_t value)

  93. {

  94.     CHECK(PlcDeviceWriteSfd(address, (uint16_t)(value & 0xFFFFUL))

  95.           == PLC_DEVICE_OK);

  96.     CHECK(PlcDeviceWriteSfd((uint16_t)(address + 1U),

  97.                             (uint16_t)(value >> 16U)) == PLC_DEVICE_OK);

  98. }

  99. 

  100. static void TestSetSegment(TEST_MEMORY *memory,

  101.                            uint16_t number,

  102.                            uint32_t frequency,

  103.                            int32_t pulses)

  104. {

  105.     uint32_t base = TEST_S0_BASE + (uint32_t)number * 10UL;

  106. 

  107.     TestWriteDword(memory, PLSR_DEVICE_D, base, (int32_t)frequency);

  108.     TestWriteDword(memory, PLSR_DEVICE_D, base + 2UL, pulses);

  109.     memory->words[PLSR_DEVICE_D][base + 4UL] = 0U;

  110.     TestWriteDword(memory, PLSR_DEVICE_D, base + 5UL, 0);

  111.     memory->words[PLSR_DEVICE_D][base + 7UL] = 0U;

  112.     TestWriteDword(memory, PLSR_DEVICE_D, base + 8UL, 0);

  113. }

  114. 

  115. static void TestResetEnvironment(void)

  116. {

  117.     PlsrPersistenceTestResetStorage();

  118.     CHECK(PlcDeviceInit() == PLC_DEVICE_OK);

  119.     CHECK(PlcDeviceWriteSfd(906U, 4) == PLC_DEVICE_OK);

  120.     CHECK(PlsrInit() == PLSR_RESULT_OK);

  121. }

  122. 

  123. static void TestCompleteFirstAbPrime(uint8_t axis)

  124. {

  125.     int quarter;

  126. 

  127.     CHECK(PlsrHwIsAbStartupPriming(axis) != 0U);

  128.     for (quarter = 0; quarter < 4; quarter++)

  129.     {

  130.         PlsrHwTestAdvanceAbQuarter(axis);

  131.     }

  132.     CHECK(PlsrHwIsAbStartupPriming(axis) == 0U);

  133.     CHECK(PlsrHwGetEmittedPulses(axis) == 0);

  134.     CHECK(PlsrHwTestGetAbQuarter(axis) == 0U);

  135. }

  136. 

  137. static PLSR_CALL TestMakeCall(TEST_MEMORY *memory)

  138. {

  139.     PLSR_CALL call;

  140. 

  141.     (void)memset(&call, 0, sizeof(call));

  142.     call.sequence = 10UL;

  143.     call.source.context = memory;

  144.     call.source.validateWords = TestValidateWords;

  145.     call.source.readWord = TestReadWord;

  146.     call.source.readBit = TestReadBit;

  147.     call.s0.device = PLSR_DEVICE_D;

  148.     call.s0.address = TEST_S0_BASE;

  149.     call.s1.device = PLSR_DEVICE_D;

  150.     call.s1.address = TEST_S1_BASE;

  151.     call.s2.type = PLSR_OPERAND_CONSTANT;

  152.     call.s2.constant = 1;

  153.     call.dAxis = 0U;

  154.     call.outputModeOverride = PLSR_OUTPUT_MODE_FROM_SFD;

  155.     return call;

  156. }

  157. 

  158. static PLSR_STATUS TestGetStatus(void)

  159. {

  160.     PLSR_STATUS status;

  161. 

  162.     (void)memset(&status, 0, sizeof(status));

  163.     CHECK(PlsrGetStatus(0U, &status) == PLSR_RESULT_OK);

  164.     return status;

  165. }

  166. 

  167. static int32_t TestReadSdDword(uint16_t lowAddress)

  168. {

  169.     int32_t lowWord = 0;

  170.     int32_t highWord = 0;

  171.     uint32_t rawValue;

  172. 

  173.     CHECK(PlcDeviceReadSd(lowAddress, &lowWord) == PLC_DEVICE_OK);

  174.     CHECK(PlcDeviceReadSd((uint16_t)(lowAddress + 1U), &highWord)

  175.           == PLC_DEVICE_OK);

  176.     rawValue = ((uint32_t)lowWord & 0xFFFFUL)

  177.                | (((uint32_t)highWord & 0xFFFFUL) << 16U);

  178.     return (int32_t)rawValue;

  179. }

  180. 

  181. /* ---- HAL 单测 ---- */

  182. 

  183. static void TestMapping(void)

  184. {

  185.     (void)PlsrHwInit();

  186.     CHECK(PlsrHwGetTimerClockHz(0U) == 168000000UL);

  187.     CHECK(PlsrHwGetTimerClockHz(1U) == 84000000UL);

  188.     CHECK(PlsrHwGetTimerClockHz(2U) == 168000000UL);

  189.     CHECK(PlsrHwGetTimerClockHz(3U) == 84000000UL);

  190.     CHECK(PlsrHwGetTimerClockHz(4U) == 0UL);

  191.     CHECK(PlsrHwResolveDirectionPoint(4U) != 0U);

  192.     CHECK(PlsrHwResolveDirectionPoint(8U) == 0U);

  193.     CHECK(PlsrHwResolveDirectionPoint(20U) != 0U);

  194.     CHECK(PlsrHwResolveDirectionPoint(21U) == 0U);

  195. }

  196. 

  197. static void TestDirDelaySequence(void)

  198. {

  199.     (void)PlsrHwInit();

  200.     PLSR_HW_START_PARAMS params;

  201.     uint16_t psc;

  202.     uint16_t arr;

  203.     int ticks;

  204. 

  205.     (void)memset(&params, 0, sizeof(params));

  206.     params.frequencyHz = 1000UL;

  207.     params.targetPulses = 100;

  208.     params.directionPoint = 4U;

  209.     params.directionPositive = 1U;

  210.     params.directionDelayMs = 10U;

  211. 

  212.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  213.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  214.     CHECK(PlsrHwTestGetDirLevel(0U) == 1U);

  215.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  216.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  217. 

  218.     for (ticks = 0; ticks < 9; ticks++)

  219.     {

  220.         PlsrHwTick(0U);

  221.     }

  222.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  223. 

  224.     PlsrHwTick(0U);

  225.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  226. 

  227.     /* 首个非零频率启动 PWM，ARR/CCR 与分频计算一致。 */

  228.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  229.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  230.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  231.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  232.     CHECK(PlsrCalculateTimerDivider(168000000UL, 1000UL, &psc, &arr)

  233.           == PLSR_RESULT_OK);

  234.     CHECK(PlsrHwTestGetArr(0U) == arr);

  235.     CHECK(PlsrHwTestGetPsc(0U) == psc);

  236.     CHECK(PlsrHwTestGetCcr(0U) == arr / 2UL);

  237.     /* PWM 模式 1（OC1M=110）：复位后 CCMR1=0 冻结，无此配置输出恒定电平。 */

  238.     CHECK((PlsrHwTestGetCcmr1(0U) & 0x70UL) == 0x60UL);

  239.     /* ARR/CCR 预装载（ARPE=CR1 bit7，OC1PE=CCMR1 bit3）：

  240.      * 运行中调频不产生提前回绕，否则加速段多出 ~ln(f1/f0) 个假脉冲。 */

  241.     CHECK((PlsrHwTestGetCr1(0U) & 0x80UL) == 0x80UL);

  242.     CHECK((PlsrHwTestGetCcmr1(0U) & 0x08UL) == 0x08UL);

  243. 

  244.     /* 段间同向衔接：方向不变时跳过方向延时，直接进入 PWM 待启动。 */

  245.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  246.     params.targetPulses = 50;

  247.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  248.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  249.     CHECK(PlsrHwTestGetDirLevel(0U) == 1U);

  250. 

  251.     /* 反向时方向延时仍生效。 */

  252.     params.directionPositive = 0U;

  253.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  254.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  255.     CHECK(PlsrHwTestGetDirLevel(0U) == 0U);

  256. }

  257. 

  258. static void TestZeroFrequencyWaits(void)

  259. {

  260.     (void)PlsrHwInit();

  261.     PLSR_HW_START_PARAMS params;

  262. 

  263.     (void)memset(&params, 0, sizeof(params));

  264.     params.frequencyHz = 0UL;

  265.     params.targetPulses = 50;

  266.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  267.     params.directionPositive = 1U;

  268.     params.directionDelayMs = 0U;

  269. 

  270.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  271.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  272.     PlsrHwTick(0U);

  273.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  274.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  275. 

  276.     /* 起始速度为 0：profile 升频后首个非零频率才启动 PWM。 */

  277.     CHECK(PlsrHwSetFrequency(0U, 10UL) == PLSR_RESULT_OK);

  278.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  279.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  280. }

  281. 

  282. static void TestPulseCounting(void)

  283. {

  284.     (void)PlsrHwInit();

  285.     PLSR_HW_START_PARAMS params;

  286.     int pulse;

  287. 

  288.     (void)memset(&params, 0, sizeof(params));

  289.     params.frequencyHz = 1000UL;

  290.     params.targetPulses = 5;

  291.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  292.     params.directionPositive = 1U;

  293.     params.directionDelayMs = 0U;

  294. 

  295.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  296.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  297.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  298.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  299. 

  300.     /* EGR.UG 只加载预装载寄存器，不能被当作物理脉冲。

  301.      * 共享 IRQ 入口在对应定时器没有 UIF 时也必须无动作。 */

  302.     PlsrHwOnTimerUpdate(0U);

  303.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  304. 

  305.     for (pulse = 0; pulse < 4; pulse++)

  306.     {

  307.         PlsrHwTestTriggerUpdate(0U);

  308.         CHECK(PlsrHwGetEmittedPulses(0U) == pulse + 1);

  309.         CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  310.     }

  311.     /* 第 5 个脉冲：到目标，停止 + 段完成事件。 */

  312.     PlsrHwTestTriggerUpdate(0U);

  313.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  314.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  315.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  316. 

  317.     /* 停止后再触发更新中断无动作。 */

  318.     PlsrHwTestTriggerUpdate(0U);

  319.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  320. }

  321. 

  322. static void TestAbPhaseAndCounting(void)

  323. {

  324.     PLSR_HW_START_PARAMS params;

  325.     static const uint8_t positiveA[4] = {1U, 1U, 0U, 0U};

  326.     static const uint8_t positiveB[4] = {0U, 1U, 1U, 0U};

  327.     static const uint8_t negativeA[4] = {0U, 1U, 1U, 0U};

  328.     static const uint8_t negativeB[4] = {1U, 1U, 0U, 0U};

  329.     uint32_t oldArr;

  330.     uint32_t oldBasePsc;

  331.     uint32_t oldPairPsc;

  332.     uint32_t newPeriod;

  333.     int quarter;

  334. 

  335.     (void)PlsrHwInit();

  336.     (void)memset(&params, 0, sizeof(params));

  337.     params.frequencyHz = 1000UL;

  338.     params.targetPulses = 4;

  339.     params.outputMode = PLSR_OUTPUT_AB;

  340.     params.directionPoint = 4U;       /* AB 模式必须忽略独立 DIR 点。 */

  341.     params.directionPositive = 1U;

  342.     params.directionDelayMs = 10U;    /* AB 模式不得执行方向延时。 */

  343. 

  344.     CHECK(PlsrHwStartPulse(1U, &params) == PLSR_RESULT_INVALID_AXIS);

  345.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  346.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  347.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  348.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  349.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  350.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  351.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  352.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  353.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  354.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  355.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  356.     CHECK(PlsrHwTestGetCcr(0U) == PlsrHwTestGetCcr(1U));

  357.     CHECK(PlsrHwTestGetCcr(0U)

  358.           == (PlsrHwTestGetArr(0U) + 1UL) / 2UL);

  359.     /* 两相从精确 00 边界起步；CC1IF 会在开中断前再次清除。 */

  360.     CHECK(PlsrHwTestGetCnt(0U)

  361.           == ((PlsrHwTestGetArr(0U) + 1UL) * 3UL) / 4UL);

  362.     CHECK(PlsrHwTestGetCnt(1U) == PlsrHwTestGetCcr(1U));

  363.     TestCompleteFirstAbPrime(0U);

  364. 

  365.     /* 任一物理 timer update 不能直接计作完整 AB 周期。 */

  366.     PlsrHwTestTriggerUpdate(0U);

  367.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  368. 

  369.     /* 正向：00→10→11→01→00；四次相位跳变只计一个脉冲。 */

  370.     for (quarter = 0; quarter < 4; quarter++)

  371.     {

  372.         PlsrHwTestAdvanceAbQuarter(0U);

  373.         CHECK(PlsrHwTestGetAbPhaseA(0U) == positiveA[quarter]);

  374.         CHECK(PlsrHwTestGetAbPhaseB(0U) == positiveB[quarter]);

  375.     }

  376.     CHECK(PlsrHwGetEmittedPulses(0U) == 1);

  377.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  378. 

  379.     /* 运行中调频先排队，不能让相差 1/4 周期的两路各自加载 ARR。 */

  380.     oldArr = PlsrHwTestGetArr(0U);

  381.     oldBasePsc = PlsrHwTestGetPsc(0U);

  382.     oldPairPsc = PlsrHwTestGetPsc(1U);

  383.     CHECK(PlsrHwSetFrequency(0U, 2000UL) == PLSR_RESULT_OK);

  384.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  385.     for (quarter = 0; quarter < 4; quarter++)

  386.     {

  387.         PlsrHwTestAdvanceAbQuarter(0U);

  388.     }

  389.     CHECK(PlsrHwGetEmittedPulses(0U) == 2);

  390.     CHECK(PlsrHwTestGetArr(0U) == oldArr);

  391.     CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  392.     CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  393. 

  394.     CHECK(PlsrHwSetFrequency(0U, 2000UL) == PLSR_RESULT_OK);

  395.     CHECK(PlsrHwTestGetAbQuarter(0U) == 0U);

  396.     CHECK(PlsrHwTestGetArr(0U) == oldArr);

  397.     CHECK(PlsrHwTestGetArr(1U) == oldArr);

  398.     CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  399.     CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  400. 

  401.     for (quarter = 0; quarter < 3; quarter++)

  402.     {

  403.         PlsrHwTestAdvanceAbQuarter(0U);

  404.         CHECK(PlsrHwTestGetArr(0U) == oldArr);

  405.         CHECK(PlsrHwTestGetArr(1U) == oldArr);

  406.         CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  407.         CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  408.     }

  409.     /* 回到 00 后，两路同时装载新频率并从精确 90° 位置重启。 */

  410.     PlsrHwTestAdvanceAbQuarter(0U);

  411.     CHECK(PlsrHwGetEmittedPulses(0U) == 3);

  412.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  413.     CHECK((PlsrHwTestGetArr(0U) != oldArr)

  414.           || (PlsrHwTestGetPsc(0U) != oldBasePsc));

  415.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  416.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  417.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  418.     newPeriod = PlsrHwTestGetArr(0U) + 1UL;

  419.     CHECK(PlsrHwTestGetCnt(0U) == (newPeriod * 3UL) / 4UL);

  420.     CHECK(PlsrHwTestGetCnt(1U) == newPeriod / 2UL);

  421. 

  422.     for (quarter = 0; quarter < 4; quarter++)

  423.     {

  424.         PlsrHwTestAdvanceAbQuarter(0U);

  425.     }

  426.     CHECK(PlsrHwGetEmittedPulses(0U) == 4);

  427.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  428.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  429.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  430.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  431.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  432. 

  433.     /* 反向：00→01→11→10→00。 */

  434.     params.targetPulses = 1;

  435.     params.directionPositive = 0U;

  436.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  437.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  438.     for (quarter = 0; quarter < 4; quarter++)

  439.     {

  440.         PlsrHwTestAdvanceAbQuarter(0U);

  441.         CHECK(PlsrHwTestGetAbPhaseA(0U) == negativeA[quarter]);

  442.         CHECK(PlsrHwTestGetAbPhaseB(0U) == negativeB[quarter]);

  443.     }

  444.     CHECK(PlsrHwGetEmittedPulses(0U) == 1);

  445.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  446. 

  447.     /* 紧急停止即使发生在周期中间，也必须回到安全 00。 */

  448.     params.targetPulses = 10;

  449.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  450.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  451.     PlsrHwTestAdvanceAbQuarter(0U);

  452.     CHECK(PlsrHwTestGetAbQuarter(0U) == 1U);

  453.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  454.     CHECK(PlsrHwTestGetAbQuarter(0U) == 0U);

  455.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  456.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  457. }

  458. 

  459. static void TestTwoAbAxesIndependent(void)

  460. {

  461.     PLSR_HW_START_PARAMS params;

  462.     int quarter;

  463. 

  464.     (void)PlsrHwInit();

  465.     (void)memset(&params, 0, sizeof(params));

  466.     params.frequencyHz = 1000UL;

  467.     params.targetPulses = 1;

  468.     params.outputMode = PLSR_OUTPUT_AB;

  469.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  470.     params.directionPositive = 1U;

  471. 

  472.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  473.     CHECK(PlsrHwStartPulse(2U, &params) == PLSR_RESULT_OK);

  474.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  475.     CHECK(PlsrHwSetFrequency(2U, 2000UL) == PLSR_RESULT_OK);

  476.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  477.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  478.     CHECK(PlsrHwTestGetPwmEnabled(2U) != 0U);

  479.     CHECK(PlsrHwTestGetPwmEnabled(3U) != 0U);

  480. 

  481.     TestCompleteFirstAbPrime(0U);

  482.     TestCompleteFirstAbPrime(2U);

  483. 

  484.     for (quarter = 0; quarter < 4; quarter++)

  485.     {

  486.         PlsrHwTestAdvanceAbQuarter(0U);

  487.     }

  488.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  489.     CHECK(PlsrHwGetState(2U) == PLSR_HW_STATE_RUNNING);

  490.     CHECK(PlsrHwGetEmittedPulses(2U) == 0);

  491.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  492.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  493.     CHECK(PlsrHwTestGetPwmEnabled(2U) != 0U);

  494.     CHECK(PlsrHwTestGetPwmEnabled(3U) != 0U);

  495. 

  496.     for (quarter = 0; quarter < 4; quarter++)

  497.     {

  498.         PlsrHwTestAdvanceAbQuarter(2U);

  499.     }

  500.     CHECK(PlsrHwGetState(2U) == PLSR_HW_STATE_DONE);

  501.     CHECK(PlsrHwGetEmittedPulses(2U) == 1);

  502. }

  503. 

  504. static void TestAbFrequencyLimits(void)

  505. {

  506.     PLSR_HW_START_PARAMS params;

  507.     int quarter;

  508. 

  509.     (void)PlsrHwInit();

  510.     (void)memset(&params, 0, sizeof(params));

  511.     params.frequencyHz = 1UL;

  512.     params.targetPulses = 100;

  513.     params.outputMode = PLSR_OUTPUT_AB;

  514.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  515.     params.directionPositive = 1U;

  516. 

  517.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  518.     CHECK(PlsrHwSetFrequency(0U, 1UL) == PLSR_RESULT_OK);

  519.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  520.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  521.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  522.     CHECK(PlsrHwTestGetArr(0U) <= 65535UL);

  523. 

  524.     TestCompleteFirstAbPrime(0U);

  525. 

  526.     CHECK(PlsrHwSetFrequency(0U, 100000UL) == PLSR_RESULT_OK);

  527.     for (quarter = 0; quarter < 4; quarter++)

  528.     {

  529.         PlsrHwTestAdvanceAbQuarter(0U);

  530.     }

  531.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  532.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  533.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  534.     CHECK(PlsrHwTestGetArr(0U) >= 3UL);

  535.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  536. }

  537. 

  538. static void TestStopAndInvalidArgs(void)

  539. {

  540.     (void)PlsrHwInit();

  541.     PLSR_HW_START_PARAMS params;

  542. 

  543.     (void)memset(&params, 0, sizeof(params));

  544.     params.frequencyHz = 1000UL;

  545.     params.targetPulses = 100;

  546.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  547.     params.directionPositive = 1U;

  548.     params.directionDelayMs = 0U;

  549. 

  550.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  551.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  552.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  553.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  554.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  555.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  556.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  557. 

  558.     CHECK(PlsrHwStartPulse(4U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  559.     CHECK(PlsrHwStartPulse(0U, NULL) == PLSR_RESULT_INVALID_ARGUMENT);

  560.     params.targetPulses = 0;

  561.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  562.     params.targetPulses = 1;

  563.     params.outputMode = PLSR_OUTPUT_CW_CCW;

  564.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_NOT_SUPPORTED);

  565.     params.outputMode = (PLSR_OUTPUT_MODE)99;

  566.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  567.     CHECK(PlsrHwSetFrequency(4U, 1000UL) == PLSR_RESULT_INVALID_ARGUMENT);

  568.     CHECK(PlsrHwStopPulse(4U) == PLSR_RESULT_INVALID_ARGUMENT);

  569. }

  570. 

  571. /* ---- 端到端集成：START → 硬件 → 计数 → 事件 → 段间 → 完成 ---- */

  572. 

  573. static void TestEndToEndTwoSegments(void)

  574. {

  575.     TEST_MEMORY memory;

  576.     PLSR_CALL call;

  577.     PLSR_STATUS status;

  578.     uint16_t initialPsc;

  579.     uint16_t initialArr;

  580.     int ticks;

  581.     int pulse;

  582. 

  583.     TestResetEnvironment();

  584.     (void)memset(&memory, 0, sizeof(memory));

  585.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 2);

  586.     TestSetSegment(&memory, 1U, 1000U, 100);

  587.     TestSetSegment(&memory, 2U, 2000U, 200);

  588. 

  589.     call = TestMakeCall(&memory);

  590.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  591.     PlsrProcess();

  592.     status = TestGetStatus();

  593.     CHECK(status.state == PLSR_STATE_ACCEL);

  594.     CHECK(status.currentSegment == 1U);

  595.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  596. 

  597.     /* DIR 延时 10ms → PWM 启动（段1 起始速度 0，profile 升频后启动）。 */

  598.     for (ticks = 0; ticks < 9; ticks++)

  599.     {

  600.         PlsrProcess();

  601.     }

  602.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  603.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  604.     CHECK(PlsrCalculateTimerDivider(168000000UL, 75UL,

  605.                                     &initialPsc, &initialArr)

  606.           == PLSR_RESULT_OK);

  607.     CHECK(PlsrHwTestGetPsc(0U) == initialPsc);

  608.     CHECK(PlsrHwTestGetArr(0U) == initialArr);

  609. 

  610.     /* 加速完成 → 状态机进入 RUN。 */

  611.     for (ticks = 0; ticks < 500; ticks++)

  612.     {

  613.         PlsrProcess();

  614.         if (TestGetStatus().state == PLSR_STATE_RUN)

  615.         {

  616.             break;

  617.         }

  618.     }

  619.     status = TestGetStatus();

  620.     CHECK(status.state == PLSR_STATE_RUN);

  621.     CHECK(status.currentSegment == 1U);

  622. 

  623.     /* 段1 脉冲完成：100 次更新中断 → SEGMENT_COMPLETE → 段2 启动。 */

  624.     for (pulse = 0; pulse < 100; pulse++)

  625.     {

  626.         PlsrHwTestTriggerUpdate(0U);

  627.     }

  628.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  629.     PlsrProcess();

  630.     status = TestGetStatus();

  631.     CHECK(status.state == PLSR_STATE_ACCEL);

  632.     CHECK(status.currentSegment == 2U);

  633.     CHECK(status.logicalPosition == 100);

  634.     CHECK(status.taskPulses == 100);

  635.     CHECK(status.totalPulses == 100);

  636.     CHECK(TestReadSdDword(1000U) == 2);

  637.     CHECK(TestReadSdDword(1002U) == 0);

  638. 

  639.     /* 段2：DIR 延时 → PWM → 加速 → RUN。 */

  640.     for (ticks = 0; ticks < 600; ticks++)

  641.     {

  642.         PlsrProcess();

  643.         if (TestGetStatus().state == PLSR_STATE_RUN)

  644.         {

  645.             break;

  646.         }

  647.     }

  648.     status = TestGetStatus();

  649.     CHECK(status.state == PLSR_STATE_RUN);

  650.     CHECK(status.currentSegment == 2U);

  651. 

  652.     /* 段2 脉冲完成 → 任务结束。 */

  653.     for (pulse = 0; pulse < 200; pulse++)

  654.     {

  655.         PlsrHwTestTriggerUpdate(0U);

  656.     }

  657.     PlsrProcess();

  658.     status = TestGetStatus();

  659.     CHECK(status.state == PLSR_STATE_COMPLETED);

  660.     CHECK(status.done != 0U);

  661.     CHECK(status.logicalPosition == 300);

  662.     CHECK(status.taskPulses == 300);

  663.     CHECK(status.totalPulses == 300);

  664.     CHECK(TestReadSdDword(1000U) == 2);

  665.     CHECK(TestReadSdDword(1002U) == 200);

  666.     CHECK(TestReadSdDword(1004U) == 200);

  667.     CHECK(TestReadSdDword(1006U) == 0);

  668.     {

  669.         int32_t hsdPulses;

  670.         int32_t hsdEquivalent;

  671. 

  672.         CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  673.         CHECK(hsdPulses == 300);

  674.         CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent)

  675.               == PLC_DEVICE_OK);

  676.         CHECK(hsdEquivalent == 300);

  677.     }

  678.     /* 终态转换后 HAL 回 IDLE（允许重新启动），脉冲已停止。 */

  679.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  680.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  681. }

  682. 

  683. static void TestEndToEndAbSegment(void)

  684. {

  685.     TEST_MEMORY memory;

  686.     PLSR_CALL call;

  687.     PLSR_STATUS status;

  688.     int quarter;

  689. 

  690.     TestResetEnvironment();

  691.     (void)memset(&memory, 0, sizeof(memory));

  692.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  693.     TestSetSegment(&memory, 1U, 1000U, -2);

  694. 

  695.     call = TestMakeCall(&memory);

  696.     call.sequence = 15UL;

  697.     call.outputModeOverride = PLSR_OUTPUT_AB;

  698.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  699.     PlsrProcess();

  700.     status = TestGetStatus();

  701.     CHECK(status.state == PLSR_STATE_ACCEL);

  702.     CHECK(status.outputMode == PLSR_OUTPUT_AB);

  703.     CHECK(status.directionPoint == PLSR_DIRECTION_POINT_NONE);

  704.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  705.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  706.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  707. 

  708.     TestCompleteFirstAbPrime(0U);

  709. 

  710.     /* 负脉冲选择反向相序，完整两个周期后由同一事件链结束任务。 */

  711.     PlsrHwTestAdvanceAbQuarter(0U);

  712.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  713.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 1U);

  714.     for (quarter = 1; quarter < 8; quarter++)

  715.     {

  716.         PlsrHwTestAdvanceAbQuarter(0U);

  717.     }

  718.     CHECK(PlsrHwGetEmittedPulses(0U) == 2);

  719.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  720.     PlsrProcess();

  721.     status = TestGetStatus();

  722.     CHECK(status.state == PLSR_STATE_COMPLETED);

  723.     CHECK(status.done != 0U);

  724.     CHECK(status.directionPositive == 0U);

  725.     CHECK(status.logicalPosition == -2);

  726.     CHECK(status.taskPulses == -2);

  727.     CHECK(status.totalPulses == 2);

  728.     CHECK(TestReadSdDword(1002U) == -2);

  729.     CHECK(TestReadSdDword(1004U) == -2);

  730.     CHECK(status.highResourceMask == 0U);

  731.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  732.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  733. }

  734. 

  735. static void TestPositionOnImmediateStop(void)

  736. {

  737.     TEST_MEMORY memory;

  738.     PLSR_CALL call;

  739.     PLSR_COMMAND command;

  740.     PLSR_STATUS status;

  741.     int pulse;

  742.     int tick;

  743. 

  744.     TestResetEnvironment();

  745.     (void)memset(&memory, 0, sizeof(memory));

  746.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  747.     TestSetSegment(&memory, 1U, 1000U, 100);

  748.     call = TestMakeCall(&memory);

  749.     call.sequence = 30UL;

  750.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  751.     PlsrProcess();

  752.     for (tick = 0; tick < 10; tick++)

  753.     {

  754.         PlsrProcess();

  755.     }

  756.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  757. 

  758.     for (pulse = 0; pulse < 37; pulse++)

  759.     {

  760.         PlsrHwTestTriggerUpdate(0U);

  761.     }

  762.     PlsrProcess();

  763.     status = TestGetStatus();

  764.     CHECK(status.logicalPosition == 37);

  765.     CHECK(status.taskPulses == 37);

  766.     CHECK(status.totalPulses == 37);

  767. 

  768.     command.sequence = 31UL;

  769.     command.axis = 0U;

  770.     command.opcode = PLSR_CMD_STOP_IMMEDIATE;

  771.     command.argument = 0;

  772.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  773.     PlsrProcess();

  774.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  775.     CHECK(PlsrPostEvent(0U, PLSR_EVENT_STOP_IMMEDIATE_DONE)

  776.           == PLSR_RESULT_OK);

  777.     PlsrProcess();

  778.     status = TestGetStatus();

  779.     CHECK(status.state == PLSR_STATE_STOPPED);

  780.     CHECK(status.logicalPosition == 37);

  781.     CHECK(status.taskPulses == 37);

  782.     CHECK(status.totalPulses == 37);

  783.     CHECK(TestReadSdDword(1002U) == 37);

  784. 

  785.     command.sequence = 32UL;

  786.     command.opcode = PLSR_CMD_CLEAR_TOTAL;

  787.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  788.     PlsrProcess();

  789.     status = TestGetStatus();

  790.     CHECK(status.logicalPosition == 37);

  791.     CHECK(status.totalPulses == 0);

  792. }

  793. 

  794. static void TestAbsolutePositionAccounting(void)

  795. {

  796.     TEST_MEMORY memory;

  797.     PLSR_CALL call;

  798.     PLSR_COMMAND command;

  799.     PLSR_STATUS status;

  800.     int32_t hsdPosition;

  801.     int pulse;

  802.     int tick;

  803. 

  804.     TestResetEnvironment();

  805.     command.sequence = 40UL;

  806.     command.axis = 0U;

  807.     command.opcode = PLSR_CMD_SET_POSITION;

  808.     command.argument = 100;

  809.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  810.     PlsrProcess();

  811. 

  812.     (void)memset(&memory, 0, sizeof(memory));

  813.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  814.     TestSetSegment(&memory, 1U, 1000U, 130);

  815.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S1_BASE, 1);

  816.     call = TestMakeCall(&memory);

  817.     call.sequence = 41UL;

  818.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  819.     PlsrProcess();

  820.     for (tick = 0; tick < 10; tick++)

  821.     {

  822.         PlsrProcess();

  823.     }

  824.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  825.     for (pulse = 0; pulse < 30; pulse++)

  826.     {

  827.         PlsrHwTestTriggerUpdate(0U);

  828.     }

  829.     PlsrProcess();

  830.     status = TestGetStatus();

  831.     CHECK(status.state == PLSR_STATE_COMPLETED);

  832.     CHECK(status.logicalPosition == 130);

  833.     CHECK(status.taskPulses == 30);

  834.     CHECK(status.totalPulses == 30);

  835.     CHECK(status.positionValid != 0U);

  836.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPosition) == PLC_DEVICE_OK);

  837.     CHECK(hsdPosition == 130);

  838. }

  839. 

  840. static void TestEquivalentRemainderAccounting(void)

  841. {

  842.     TEST_MEMORY memory;

  843.     PLSR_CALL call;

  844.     PLSR_STATUS status;

  845.     int32_t hsdPulses;

  846.     int32_t hsdEquivalent;

  847. 

  848.     TestResetEnvironment();

  849.     CHECK(PlcDeviceWriteSfd(900U, (1U << 8U)) == PLC_DEVICE_OK);

  850.     TestWriteSfdDword(902U, 3UL);

  851.     TestWriteSfdDword(904U, 2UL);

  852.     TestWriteSfdDword(956U, 60000UL);

  853.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  854. 

  855.     (void)memset(&memory, 0, sizeof(memory));

  856.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  857.     TestSetSegment(&memory, 1U, 1000U, 1);

  858.     call = TestMakeCall(&memory);

  859.     call.sequence = 30UL;

  860.     call.outputModeOverride = PLSR_OUTPUT_PULSE_DIR;

  861. 

  862.     /* 3脉冲/2单位：第一次1单位只输出1脉冲并保存1/2余数。 */

  863.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  864.     PlsrProcess();

  865.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  866.     PlsrHwTestTriggerUpdate(0U);

  867.     PlsrProcess();

  868.     status = TestGetStatus();

  869.     CHECK(status.state == PLSR_STATE_COMPLETED);

  870.     CHECK(status.logicalPosition == 1);

  871.     CHECK(status.taskPulses == 1);

  872.     CHECK(status.totalPulses == 1);

  873.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  874.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  875.     CHECK(hsdPulses == 1);

  876.     CHECK(hsdEquivalent == 0);

  877. 

  878.     /* 第二次1单位合并余数后输出2脉冲；两次合计精确为3脉冲/2单位。 */

  879.     call.sequence = 31UL;

  880.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  881.     PlsrProcess();

  882.     PlsrHwTestTriggerUpdate(0U);

  883.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  884.     PlsrHwTestTriggerUpdate(0U);

  885.     PlsrProcess();

  886.     status = TestGetStatus();

  887.     CHECK(status.state == PLSR_STATE_COMPLETED);

  888.     CHECK(status.logicalPosition == 3);

  889.     CHECK(status.taskPulses == 2);

  890.     CHECK(status.totalPulses == 3);

  891.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  892.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  893.     CHECK(hsdPulses == 3);

  894.     CHECK(hsdEquivalent == 2);

  895.     CHECK(TestReadSdDword(1002U) == 2);

  896.     CHECK(TestReadSdDword(1004U) == 1);

  897. }

  898. 

  899. static void TestEquivalentCompatibleError(void)

  900. {

  901.     TEST_MEMORY memory;

  902.     PLSR_CALL call;

  903.     PLSR_STATUS status;

  904.     int32_t errorCode = -1;

  905.     int32_t errorBlock = -1;

  906. 

  907.     TestResetEnvironment();

  908.     CHECK(PlcDeviceWriteSfd(900U, (1U << 8U)) == PLC_DEVICE_OK);

  909.     TestWriteSfdDword(902U, 0UL);

  910.     TestWriteSfdDword(904U, 2UL);

  911.     TestWriteSfdDword(956U, 60000UL);

  912. 

  913.     (void)memset(&memory, 0, sizeof(memory));

  914.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  915.     TestSetSegment(&memory, 1U, 1000U, 1);

  916.     call = TestMakeCall(&memory);

  917.     call.sequence = 32UL;

  918.     call.outputModeOverride = PLSR_OUTPUT_PULSE_DIR;

  919. 

  920.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  921.     PlsrProcess();

  922.     status = TestGetStatus();

  923.     CHECK(status.lastCommandResult == PLSR_RESULT_INVALID_S2);

  924.     CHECK(status.state == PLSR_STATE_IDLE);

  925.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  926.     CHECK(PlcDeviceReadSd(1011U, &errorBlock) == PLC_DEVICE_OK);

  927.     CHECK(errorCode == 2);

  928.     CHECK(errorBlock == 0);

  929. 

  930.     /* A valid retry clears the compatible parameter error. */

  931.     TestWriteSfdDword(902U, 3UL);

  932.     call.sequence = 33UL;

  933.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  934.     PlsrProcess();

  935.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  936.     CHECK(errorCode == 0);

  937.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  938. }

  939. 

  940. static void TestSoftLimitAndSegmentEvent(void)

  941. {

  942.     TEST_MEMORY memory;

  943.     PLSR_CALL call;

  944.     PLSR_COMMAND command;

  945.     PLSR_STATUS status;

  946.     PLC_DEVICE_EVENT_RECORD eventRecord;

  947.     int32_t errorCode;

  948.     int pulse;

  949.     int tick;

  950. 

  951.     TestResetEnvironment();

  952.     CHECK(PlcDeviceWriteSfd(900U, (1U << 2U)) == PLC_DEVICE_OK);

  953.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  954.     CHECK(PlcDeviceWriteSfd(912U, 0U) == PLC_DEVICE_OK);

  955.     CHECK(PlcDeviceWriteSfd(915U, 0xFFFFU) == PLC_DEVICE_OK);

  956.     TestWriteSfdDword(930U, 100UL);

  957.     TestWriteSfdDword(932U, (uint32_t)(int32_t)-100);

  958. 

  959.     command.sequence = 40UL;

  960.     command.axis = 0U;

  961.     command.opcode = PLSR_CMD_SET_POSITION;

  962.     command.argument = 100;

  963.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  964.     PlsrProcess();

  965. 

  966.     (void)memset(&memory, 0, sizeof(memory));

  967.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  968.     TestSetSegment(&memory, 1U, 1000U, 10);

  969.     call = TestMakeCall(&memory);

  970.     call.sequence = 41UL;

  971.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  972.     PlsrProcess();

  973.     status = TestGetStatus();

  974.     CHECK(status.lastCommandResult == PLSR_RESULT_LIMIT_POSITIVE);

  975.     CHECK(status.state == PLSR_STATE_IDLE);

  976.     CHECK(status.positiveLimitActive != 0U);

  977.     CHECK(status.error == PLSR_ERROR_LIMIT_POSITIVE);

  978.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  979.     CHECK(errorCode == 5);

  980. 

  981.     /* 正限位上只禁止正向，反向离开仍可正常完成。 */

  982.     TestSetSegment(&memory, 1U, 1000U, -10);

  983.     call.sequence = 42UL;

  984.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  985.     PlsrProcess();

  986.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  987.     for (pulse = 0; pulse < 10; pulse++)

  988.     {

  989.         PlsrHwTestTriggerUpdate(0U);

  990.     }

  991.     PlsrProcess();

  992.     status = TestGetStatus();

  993.     CHECK(status.state == PLSR_STATE_COMPLETED);

  994.     CHECK(status.logicalPosition == 90);

  995.     CHECK(status.error == PLSR_ERROR_NONE);

  996.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  997.     CHECK(eventRecord.count == 1UL);

  998.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_NORMAL_COMPLETE);

  999.     CHECK(eventRecord.pending != 0U);

  1000. 

  1001.     /* 运行中按预计制动距离触发软限位，PWM保持运行并按曲线缓停。 */

  1002.     TestResetEnvironment();

  1003.     CHECK(PlcDeviceWriteSfd(900U, (1U << 2U)) == PLC_DEVICE_OK);

  1004.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1005.     TestWriteSfdDword(930U, 50UL);

  1006.     TestWriteSfdDword(932U, (uint32_t)(int32_t)-50);

  1007.     command.sequence = 43UL;

  1008.     command.opcode = PLSR_CMD_SET_POSITION;

  1009.     command.argument = 0;

  1010.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1011.     PlsrProcess();

  1012.     (void)memset(&memory, 0, sizeof(memory));

  1013.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1014.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1015.     call = TestMakeCall(&memory);

  1016.     call.sequence = 44UL;

  1017.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1018.     PlsrProcess();

  1019.     for (pulse = 0; pulse < 49; pulse++)

  1020.     {

  1021.         PlsrHwTestTriggerUpdate(0U);

  1022.     }

  1023.     PlsrProcess();

  1024.     status = TestGetStatus();

  1025.     CHECK(status.state == PLSR_STATE_DECEL);

  1026.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1027.     CHECK(status.positiveLimitActive != 0U);

  1028.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1029.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  1030.     CHECK(errorCode == 5);

  1031.     for (tick = 0; tick < 20; tick++)

  1032.     {

  1033.         PlsrProcess();

  1034.     }

  1035.     status = TestGetStatus();

  1036.     CHECK(status.state == PLSR_STATE_STOPPED);

  1037.     CHECK(status.logicalPosition == 49);

  1038.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1039.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1040.     CHECK(eventRecord.count == 1UL);

  1041.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1042. }

  1043. 

  1044. static void TestHardLimitAndEmergencyLatch(void)

  1045. {

  1046.     TEST_MEMORY memory;

  1047.     PLSR_CALL call;

  1048.     PLSR_COMMAND command;

  1049.     PLSR_STATUS status;

  1050.     PLC_DEVICE_EVENT_RECORD eventRecord;

  1051. 

  1052.     TestResetEnvironment();

  1053.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1054.     CHECK(PlcDeviceWriteSfd(912U, 0U) == PLC_DEVICE_OK);

  1055.     CHECK(PlcDeviceWriteSfd(915U, 0xFF03U) == PLC_DEVICE_OK);

  1056.     (void)memset(&memory, 0, sizeof(memory));

  1057.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1058.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1059.     call = TestMakeCall(&memory);

  1060.     call.sequence = 50UL;

  1061.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1062.     PlsrProcess();

  1063.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1064.     memory.bits[0][3U] = 1U;

  1065.     PlsrProcess();

  1066.     status = TestGetStatus();

  1067.     CHECK(status.state == PLSR_STATE_DECEL);

  1068.     CHECK(status.positiveLimitActive != 0U);

  1069.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1070.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1071.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1072. 

  1073.     TestResetEnvironment();

  1074.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1075.     (void)memset(&memory, 0, sizeof(memory));

  1076.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1077.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1078.     call = TestMakeCall(&memory);

  1079.     call.sequence = 51UL;

  1080.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1081.     PlsrProcess();

  1082.     command.sequence = 52UL;

  1083.     command.axis = 0U;

  1084.     command.opcode = PLSR_CMD_RESET_ERROR;

  1085.     command.argument = 0;

  1086.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1087.     CHECK(PlsrPostEvent(0U,

  1088.                         PLSR_EVENT_LIMIT_POSITIVE

  1089.                             | PLSR_EVENT_SOFTWARE_EMERGENCY)

  1090.           == PLSR_RESULT_OK);

  1091.     PlsrProcess();

  1092.     status = TestGetStatus();

  1093.     CHECK(status.state == PLSR_STATE_STOPPED);

  1094.     CHECK(status.stopReason == PLSR_STOP_REASON_SOFTWARE_EMERGENCY);

  1095.     CHECK(status.error == PLSR_ERROR_EMERGENCY);

  1096.     CHECK(status.emergencyLatched != 0U);

  1097.     CHECK(status.lastCommandSequence == 52UL);

  1098.     CHECK(status.lastCommandResult == PLSR_RESULT_BUSY);

  1099.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1100.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1101.     CHECK(eventRecord.count == 1UL);

  1102.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_SOFTWARE_EMERGENCY);

  1103. 

  1104.     call.sequence = 53UL;

  1105.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1106.     PlsrProcess();

  1107.     status = TestGetStatus();

  1108.     CHECK(status.lastCommandResult == PLSR_RESULT_EMERGENCY_LATCHED);

  1109.     CHECK(status.state == PLSR_STATE_STOPPED);

  1110. 

  1111.     command.sequence = 54UL;

  1112.     command.axis = 0U;

  1113.     command.opcode = PLSR_CMD_RESET_ERROR;

  1114.     command.argument = 0;

  1115.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1116.     PlsrProcess();

  1117.     status = TestGetStatus();

  1118.     CHECK(status.state == PLSR_STATE_IDLE);

  1119.     CHECK(status.error == PLSR_ERROR_NONE);

  1120.     CHECK(status.emergencyLatched == 0U);

  1121. }

  1122. 

  1123. static void TestProductionSelfTestStartsAb(void)

  1124. {

  1125.     PLSR_STATUS status;

  1126. 

  1127.     TestResetEnvironment();

  1128.     CHECK(PlsrSelfTestQueue() == PLSR_RESULT_QUEUED);

  1129.     PlsrProcess();

  1130.     status = TestGetStatus();

  1131.     CHECK(status.lastCommandResult == PLSR_RESULT_OK);

  1132.     CHECK(status.outputMode == PLSR_OUTPUT_AB);

  1133.     CHECK(status.currentSegment == 1U);

  1134.     CHECK(status.state == PLSR_STATE_ACCEL);

  1135.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1136.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  1137.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  1138.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  1139. }

  1140. 

  1141. static void TestEquivalentSelfTest(void)

  1142. {

  1143.     PLSR_STATUS status;

  1144.     int32_t hsdPulses;

  1145.     int32_t hsdEquivalent;

  1146.     int ticks;

  1147. 

  1148.     TestResetEnvironment();

  1149.     CHECK(PlsrEquivalentSelfTestQueue() == PLSR_RESULT_QUEUED);

  1150.     PlsrProcess();

  1151. 

  1152.     /* SFD907=10ms. Advance the simulated hardware delay before segment 1. */

  1153.     for (ticks = 0; ticks < 10; ticks++)

  1154.     {

  1155.         PlsrProcess();

  1156.     }

  1157.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1158. 

  1159.     /* 3 pulses / 2 units: 1001 units emit 1501 pulses and keep 1/2 remainder. */

  1160.     for (ticks = 0; ticks < 1501; ticks++)

  1161.     {

  1162.         PlsrHwTestTriggerUpdate(0U);

  1163.     }

  1164.     PlsrProcess();

  1165.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1166. 

  1167.     /* Segment 2 consumes the remainder and therefore emits 1502 pulses. */

  1168.     for (ticks = 0; ticks < 1502; ticks++)

  1169.     {

  1170.         PlsrHwTestTriggerUpdate(0U);

  1171.     }

  1172.     PlsrProcess();

  1173. 

  1174.     status = TestGetStatus();

  1175.     CHECK(status.lastCommandResult == PLSR_RESULT_OK);

  1176.     CHECK(status.outputMode == PLSR_OUTPUT_PULSE_DIR);

  1177.     CHECK(status.state == PLSR_STATE_COMPLETED);

  1178.     CHECK(status.currentSegment == 2U);

  1179.     CHECK(status.logicalPosition == 3003);

  1180.     CHECK(status.taskPulses == 3003);

  1181.     CHECK(status.totalPulses == 3003);

  1182.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  1183.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  1184.     CHECK(hsdPulses == 3003);

  1185.     CHECK(hsdEquivalent == 2002);

  1186.     CHECK(TestReadSdDword(1002U) == 1502);

  1187.     CHECK(TestReadSdDword(1004U) == 1001);

  1188. }

  1189. 

  1190. static void TestProtectionSelfTest(void)

  1191. {

  1192.     PLC_DEVICE_EVENT_RECORD eventRecord;

  1193.     PLSR_STATUS status;

  1194.     uint32_t pulseAccumulator = 0UL;

  1195.     int32_t value;

  1196.     int ticks;

  1197. 

  1198.     TestResetEnvironment();

  1199.     CHECK(PlsrProtectionSelfTestQueue() == PLSR_RESULT_QUEUED);

  1200.     PlsrProcess();

  1201. 

  1202.     /* Complete the 10ms direction-settle interval. */

  1203.     for (ticks = 0; ticks < 10; ticks++)

  1204.     {

  1205.         PlsrProcess();

  1206.     }

  1207.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1208. 

  1209.     /* Convert the current frequency into simulated hardware updates over

  1210.      * each 1ms process tick.  This also models the falling pulse density

  1211.      * during the controlled stop. */

  1212.     status = TestGetStatus();

  1213.     for (ticks = 0; ticks < 600; ticks++)

  1214.     {

  1215.         pulseAccumulator += PlsrHwGetCurrentFrequencyHz(0U);

  1216.         while ((pulseAccumulator >= 1000UL)

  1217.                && (PlsrHwIsPulseActive(0U) != 0U))

  1218.         {

  1219.             PlsrHwTestTriggerUpdate(0U);

  1220.             pulseAccumulator -= 1000UL;

  1221.         }

  1222.         PlsrProcess();

  1223.         status = TestGetStatus();

  1224.         if (status.state == PLSR_STATE_STOPPED)

  1225.         {

  1226.             break;

  1227.         }

  1228.     }

  1229. 

  1230.     status = TestGetStatus();

  1231.     CHECK(status.state == PLSR_STATE_STOPPED);

  1232.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1233.     CHECK(status.error == PLSR_ERROR_LIMIT_POSITIVE);

  1234.     CHECK(status.emergencyLatched == 0U);

  1235.     CHECK(status.logicalPosition >= 499);

  1236.     CHECK(status.logicalPosition <= 501);

  1237.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1238.     CHECK(PlcDeviceReadSd(1010U, &value) == PLC_DEVICE_OK);

  1239.     CHECK(value == 5U);

  1240.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1241.     CHECK(eventRecord.count == 1UL);

  1242.     CHECK(eventRecord.pending != 0U);

  1243.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1244. }

  1245. 

  1246. static void TestStopStopsHardware(void)

  1247. {

  1248.     TEST_MEMORY memory;

  1249.     PLSR_CALL call;

  1250.     PLSR_COMMAND command;

  1251.     PLSR_STATUS status;

  1252.     int ticks;

  1253. 

  1254.     TestResetEnvironment();

  1255.     (void)memset(&memory, 0, sizeof(memory));

  1256.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1257.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1258. 

  1259.     call = TestMakeCall(&memory);

  1260.     call.sequence = 20UL;

  1261.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1262.     PlsrProcess();

  1263.     for (ticks = 0; ticks < 10; ticks++)

  1264.     {

  1265.         PlsrProcess();

  1266.     }

  1267.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  1268. 

  1269.     /* STOP_IMMEDIATE：硬件立即停止。 */

  1270.     command.sequence = 21UL;

  1271.     command.axis = 0U;

  1272.     command.opcode = PLSR_CMD_STOP_IMMEDIATE;

  1273.     command.argument = 0;

  1274.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1275.     PlsrProcess();

  1276.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  1277.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1278. 

  1279.     CHECK(PlsrPostEvent(0U, PLSR_EVENT_STOP_IMMEDIATE_DONE)

  1280.           == PLSR_RESULT_OK);

  1281.     PlsrProcess();

  1282.     status = TestGetStatus();

  1283.     CHECK(status.state == PLSR_STATE_STOPPED);

  1284. }

  1285. 

  1286. int main(void)

  1287. {

  1288.     TestMapping();

  1289.     TestDirDelaySequence();

  1290.     TestZeroFrequencyWaits();

  1291.     TestPulseCounting();

  1292.     TestAbPhaseAndCounting();

  1293.     TestTwoAbAxesIndependent();

  1294.     TestAbFrequencyLimits();

  1295.     TestStopAndInvalidArgs();

  1296.     TestEndToEndTwoSegments();

  1297.     TestEndToEndAbSegment();

  1298.     TestPositionOnImmediateStop();

  1299.     TestAbsolutePositionAccounting();

  1300.     TestEquivalentRemainderAccounting();

  1301.     TestEquivalentCompatibleError();

  1302.     TestSoftLimitAndSegmentEvent();

  1303.     TestHardLimitAndEmergencyLatch();

  1304.     TestProductionSelfTestStartsAb();

  1305.     TestEquivalentSelfTest();

  1306.     TestProtectionSelfTest();

  1307.     TestStopStopsHardware();

  1308. 

  1309.     if (TestFailures != 0)

  1310.     {

  1311.         (void)printf("FAIL: %d of %d PLSR HAL checks failed\n",

  1312.                      TestFailures,

  1313.                      TestChecks);

  1314.         return 1;

  1315.     }

  1316.     (void)printf("PASS: %d PLSR HAL checks\n", TestChecks);

  1317.     return 0;

  1318. }