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Modbus-rtu/PLSR/Test/test_plsr_hal.c

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  1. #include "plc_device.h"

  2. #include "plsr_core.h"

  3. #include "plsr_hal_f407.h"

  4. #include "plsr_job.h"

  5. #include "plsr_persistence.h"

  6. #include "plsr_resource.h"

  7. #include "plsr_self_test.h"

  8. #include <stdio.h>

  9. #include <string.h>

  10. 

  11. #define TEST_WORD_CAPACITY  (3000U)

  12. #define TEST_BIT_CAPACITY   (128U)

  13. #define TEST_S0_BASE        (100U)

  14. #define TEST_S1_BASE        (200U)

  15. 

  16. typedef struct

  17. {

  18.     uint16_t words[3][TEST_WORD_CAPACITY];

  19.     uint8_t bits[3][TEST_BIT_CAPACITY];

  20. } TEST_MEMORY;

  21. 

  22. static int TestFailures;

  23. static int TestChecks;

  24. 

  25. #define CHECK(condition)                                                     \

  26.     do                                                                       \

  27.     {                                                                        \

  28.         TestChecks++;                                                        \

  29.         if (!(condition))                                                    \

  30.         {                                                                    \

  31.             TestFailures++;                                                  \

  32.             (void)printf("FAIL line %d: %s\n", __LINE__, #condition);       \

  33.         }                                                                    \

  34.     } while (0)

  35. 

  36. static uint8_t TestValidateWords(void *context,

  37.                                  PLSR_DEVICE_TYPE device,

  38.                                  uint32_t firstAddress,

  39.                                  uint32_t wordCount)

  40. {

  41.     (void)context;

  42.     (void)device;

  43.     return (((uint64_t)firstAddress + wordCount) <= TEST_WORD_CAPACITY)

  44.                ? 1U

  45.                : 0U;

  46. }

  47. 

  48. static uint8_t TestReadWord(void *context,

  49.                             PLSR_DEVICE_TYPE device,

  50.                             uint32_t address,

  51.                             uint16_t *value)

  52. {

  53.     TEST_MEMORY *memory = (TEST_MEMORY *)context;

  54. 

  55.     if ((memory == NULL) || (value == NULL) || (device > PLSR_DEVICE_FD)

  56.         || (address >= TEST_WORD_CAPACITY))

  57.     {

  58.         return 0U;

  59.     }

  60.     *value = memory->words[device][address];

  61.     return 1U;

  62. }

  63. 

  64. static uint8_t TestReadBit(void *context,

  65.                            PLSR_DEVICE_TYPE device,

  66.                            uint32_t address,

  67.                            uint8_t *value)

  68. {

  69.     TEST_MEMORY *memory = (TEST_MEMORY *)context;

  70.     uint8_t index;

  71. 

  72.     if ((memory == NULL) || (value == NULL) || (device < PLSR_DEVICE_X)

  73.         || (device > PLSR_DEVICE_HM) || (address >= TEST_BIT_CAPACITY))

  74.     {

  75.         return 0U;

  76.     }

  77.     index = (uint8_t)(device - PLSR_DEVICE_X);

  78.     *value = memory->bits[index][address];

  79.     return 1U;

  80. }

  81. 

  82. static void TestWriteDword(TEST_MEMORY *memory,

  83.                            PLSR_DEVICE_TYPE device,

  84.                            uint32_t address,

  85.                            int32_t value)

  86. {

  87.     uint32_t raw = (uint32_t)value;

  88. 

  89.     memory->words[device][address] = (uint16_t)(raw & 0xFFFFUL);

  90.     memory->words[device][address + 1UL] = (uint16_t)(raw >> 16U);

  91. }

  92. 

  93. static void TestWriteSfdDword(uint16_t address, uint32_t value)

  94. {

  95.     CHECK(PlcDeviceWriteSfd(address, (uint16_t)(value & 0xFFFFUL))

  96.           == PLC_DEVICE_OK);

  97.     CHECK(PlcDeviceWriteSfd((uint16_t)(address + 1U),

  98.                             (uint16_t)(value >> 16U)) == PLC_DEVICE_OK);

  99. }

  100. 

  101. static void TestSetSegment(TEST_MEMORY *memory,

  102.                            uint16_t number,

  103.                            uint32_t frequency,

  104.                            int32_t pulses)

  105. {

  106.     uint32_t base = TEST_S0_BASE + (uint32_t)number * 10UL;

  107. 

  108.     TestWriteDword(memory, PLSR_DEVICE_D, base, (int32_t)frequency);

  109.     TestWriteDword(memory, PLSR_DEVICE_D, base + 2UL, pulses);

  110.     memory->words[PLSR_DEVICE_D][base + 4UL] = 0U;

  111.     TestWriteDword(memory, PLSR_DEVICE_D, base + 5UL, 0);

  112.     memory->words[PLSR_DEVICE_D][base + 7UL] = 0U;

  113.     TestWriteDword(memory, PLSR_DEVICE_D, base + 8UL, 0);

  114. }

  115. 

  116. static void TestResetEnvironment(void)

  117. {

  118.     PlsrPersistenceTestResetStorage();

  119.     CHECK(PlcDeviceInit() == PLC_DEVICE_OK);

  120.     CHECK(PlcDeviceWriteSfd(906U, 4) == PLC_DEVICE_OK);

  121.     CHECK(PlsrInit() == PLSR_RESULT_OK);

  122. }

  123. 

  124. static void TestCompleteFirstAbPrime(uint8_t axis)

  125. {

  126.     int quarter;

  127. 

  128.     CHECK(PlsrHwIsAbStartupPriming(axis) != 0U);

  129.     for (quarter = 0; quarter < 4; quarter++)

  130.     {

  131.         PlsrHwTestAdvanceAbQuarter(axis);

  132.     }

  133.     CHECK(PlsrHwIsAbStartupPriming(axis) == 0U);

  134.     CHECK(PlsrHwGetEmittedPulses(axis) == 0);

  135.     CHECK(PlsrHwTestGetAbQuarter(axis) == 0U);

  136. }

  137. 

  138. static PLSR_CALL TestMakeCall(TEST_MEMORY *memory)

  139. {

  140.     PLSR_CALL call;

  141. 

  142.     (void)memset(&call, 0, sizeof(call));

  143.     call.sequence = 10UL;

  144.     call.source.context = memory;

  145.     call.source.validateWords = TestValidateWords;

  146.     call.source.readWord = TestReadWord;

  147.     call.source.readBit = TestReadBit;

  148.     call.s0.device = PLSR_DEVICE_D;

  149.     call.s0.address = TEST_S0_BASE;

  150.     call.s1.device = PLSR_DEVICE_D;

  151.     call.s1.address = TEST_S1_BASE;

  152.     call.s2.type = PLSR_OPERAND_CONSTANT;

  153.     call.s2.constant = 1;

  154.     call.dAxis = 0U;

  155.     call.outputModeOverride = PLSR_OUTPUT_MODE_FROM_SFD;

  156.     return call;

  157. }

  158. 

  159. static PLSR_STATUS TestGetStatus(void)

  160. {

  161.     PLSR_STATUS status;

  162. 

  163.     (void)memset(&status, 0, sizeof(status));

  164.     CHECK(PlsrGetStatus(0U, &status) == PLSR_RESULT_OK);

  165.     return status;

  166. }

  167. 

  168. static int32_t TestReadSdDword(uint16_t lowAddress)

  169. {

  170.     int32_t lowWord = 0;

  171.     int32_t highWord = 0;

  172.     uint32_t rawValue;

  173. 

  174.     CHECK(PlcDeviceReadSd(lowAddress, &lowWord) == PLC_DEVICE_OK);

  175.     CHECK(PlcDeviceReadSd((uint16_t)(lowAddress + 1U), &highWord)

  176.           == PLC_DEVICE_OK);

  177.     rawValue = ((uint32_t)lowWord & 0xFFFFUL)

  178.                | (((uint32_t)highWord & 0xFFFFUL) << 16U);

  179.     return (int32_t)rawValue;

  180. }

  181. 

  182. /* ---- HAL 单测 ---- */

  183. 

  184. static void TestMapping(void)

  185. {

  186.     (void)PlsrHwInit();

  187.     CHECK(PlsrHwGetTimerClockHz(0U) == 168000000UL);

  188.     CHECK(PlsrHwGetTimerClockHz(1U) == 84000000UL);

  189.     CHECK(PlsrHwGetTimerClockHz(2U) == 168000000UL);

  190.     CHECK(PlsrHwGetTimerClockHz(3U) == 84000000UL);

  191.     CHECK(PlsrHwGetTimerClockHz(4U) == 0UL);

  192.     CHECK(PlsrHwResolveDirectionPoint(4U) != 0U);

  193.     CHECK(PlsrHwResolveDirectionPoint(8U) == 0U);

  194.     CHECK(PlsrHwResolveDirectionPoint(20U) != 0U);

  195.     CHECK(PlsrHwResolveDirectionPoint(21U) == 0U);

  196. }

  197. 

  198. static void TestDirDelaySequence(void)

  199. {

  200.     (void)PlsrHwInit();

  201.     PLSR_HW_START_PARAMS params;

  202.     uint16_t psc;

  203.     uint16_t arr;

  204.     int ticks;

  205. 

  206.     (void)memset(&params, 0, sizeof(params));

  207.     params.frequencyHz = 1000UL;

  208.     params.targetPulses = 100;

  209.     params.directionPoint = 4U;

  210.     params.directionPositive = 1U;

  211.     params.directionDelayMs = 10U;

  212. 

  213.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  214.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  215.     CHECK(PlsrHwTestGetDirLevel(0U) == 1U);

  216.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  217.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  218. 

  219.     for (ticks = 0; ticks < 9; ticks++)

  220.     {

  221.         PlsrHwTick(0U);

  222.     }

  223.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  224. 

  225.     PlsrHwTick(0U);

  226.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  227. 

  228.     /* 首个非零频率启动 PWM，ARR/CCR 与分频计算一致。 */

  229.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  230.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  231.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  232.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  233.     CHECK(PlsrCalculateTimerDivider(168000000UL, 1000UL, &psc, &arr)

  234.           == PLSR_RESULT_OK);

  235.     CHECK(PlsrHwTestGetArr(0U) == arr);

  236.     CHECK(PlsrHwTestGetPsc(0U) == psc);

  237.     CHECK(PlsrHwTestGetCcr(0U) == arr / 2UL);

  238.     /* PWM 模式 1（OC1M=110）：复位后 CCMR1=0 冻结，无此配置输出恒定电平。 */

  239.     CHECK((PlsrHwTestGetCcmr1(0U) & 0x70UL) == 0x60UL);

  240.     /* ARR/CCR 预装载（ARPE=CR1 bit7，OC1PE=CCMR1 bit3）：

  241.      * 运行中调频不产生提前回绕，否则加速段多出 ~ln(f1/f0) 个假脉冲。 */

  242.     CHECK((PlsrHwTestGetCr1(0U) & 0x80UL) == 0x80UL);

  243.     CHECK((PlsrHwTestGetCcmr1(0U) & 0x08UL) == 0x08UL);

  244. 

  245.     /* 段间同向衔接：方向不变时跳过方向延时，直接进入 PWM 待启动。 */

  246.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  247.     params.targetPulses = 50;

  248.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  249.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  250.     CHECK(PlsrHwTestGetDirLevel(0U) == 1U);

  251. 

  252.     /* 反向时方向延时仍生效。 */

  253.     params.directionPositive = 0U;

  254.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  255.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  256.     CHECK(PlsrHwTestGetDirLevel(0U) == 0U);

  257. }

  258. 

  259. static void TestZeroFrequencyWaits(void)

  260. {

  261.     (void)PlsrHwInit();

  262.     PLSR_HW_START_PARAMS params;

  263. 

  264.     (void)memset(&params, 0, sizeof(params));

  265.     params.frequencyHz = 0UL;

  266.     params.targetPulses = 50;

  267.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  268.     params.directionPositive = 1U;

  269.     params.directionDelayMs = 0U;

  270. 

  271.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  272.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  273.     PlsrHwTick(0U);

  274.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  275.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  276. 

  277.     /* 起始速度为 0：profile 升频后首个非零频率才启动 PWM。 */

  278.     CHECK(PlsrHwSetFrequency(0U, 10UL) == PLSR_RESULT_OK);

  279.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  280.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  281. }

  282. 

  283. static void TestPulseCounting(void)

  284. {

  285.     (void)PlsrHwInit();

  286.     PLSR_HW_START_PARAMS params;

  287.     int pulse;

  288. 

  289.     (void)memset(&params, 0, sizeof(params));

  290.     params.frequencyHz = 1000UL;

  291.     params.targetPulses = 5;

  292.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  293.     params.directionPositive = 1U;

  294.     params.directionDelayMs = 0U;

  295. 

  296.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  297.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  298.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  299.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  300. 

  301.     /* EGR.UG 只加载预装载寄存器，不能被当作物理脉冲。

  302.      * 共享 IRQ 入口在对应定时器没有 UIF 时也必须无动作。 */

  303.     PlsrHwOnTimerUpdate(0U);

  304.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  305. 

  306.     for (pulse = 0; pulse < 4; pulse++)

  307.     {

  308.         PlsrHwTestTriggerUpdate(0U);

  309.         CHECK(PlsrHwGetEmittedPulses(0U) == pulse + 1);

  310.         CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  311.     }

  312.     /* 第 5 个脉冲：到目标，停止 + 段完成事件。 */

  313.     PlsrHwTestTriggerUpdate(0U);

  314.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  315.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  316.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  317. 

  318.     /* 停止后再触发更新中断无动作。 */

  319.     PlsrHwTestTriggerUpdate(0U);

  320.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  321. }

  322. 

  323. static void TestAbPhaseAndCounting(void)

  324. {

  325.     PLSR_HW_START_PARAMS params;

  326.     static const uint8_t positiveA[4] = {1U, 1U, 0U, 0U};

  327.     static const uint8_t positiveB[4] = {0U, 1U, 1U, 0U};

  328.     static const uint8_t negativeA[4] = {0U, 1U, 1U, 0U};

  329.     static const uint8_t negativeB[4] = {1U, 1U, 0U, 0U};

  330.     uint32_t oldArr;

  331.     uint32_t oldBasePsc;

  332.     uint32_t oldPairPsc;

  333.     uint32_t newPeriod;

  334.     int quarter;

  335. 

  336.     (void)PlsrHwInit();

  337.     (void)memset(&params, 0, sizeof(params));

  338.     params.frequencyHz = 1000UL;

  339.     params.targetPulses = 4;

  340.     params.outputMode = PLSR_OUTPUT_AB;

  341.     params.directionPoint = 4U;       /* AB 模式必须忽略独立 DIR 点。 */

  342.     params.directionPositive = 1U;

  343.     params.directionDelayMs = 10U;    /* AB 模式不得执行方向延时。 */

  344. 

  345.     CHECK(PlsrHwStartPulse(1U, &params) == PLSR_RESULT_INVALID_AXIS);

  346.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  347.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_PWM_PENDING);

  348.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  349.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  350.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  351.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  352.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  353.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  354.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  355.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  356.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  357.     CHECK(PlsrHwTestGetCcr(0U) == PlsrHwTestGetCcr(1U));

  358.     CHECK(PlsrHwTestGetCcr(0U)

  359.           == (PlsrHwTestGetArr(0U) + 1UL) / 2UL);

  360.     /* 两相从精确 00 边界起步；CC1IF 会在开中断前再次清除。 */

  361.     CHECK(PlsrHwTestGetCnt(0U)

  362.           == ((PlsrHwTestGetArr(0U) + 1UL) * 3UL) / 4UL);

  363.     CHECK(PlsrHwTestGetCnt(1U) == PlsrHwTestGetCcr(1U));

  364.     TestCompleteFirstAbPrime(0U);

  365. 

  366.     /* 任一物理 timer update 不能直接计作完整 AB 周期。 */

  367.     PlsrHwTestTriggerUpdate(0U);

  368.     CHECK(PlsrHwGetEmittedPulses(0U) == 0);

  369. 

  370.     /* 正向：00→10→11→01→00；四次相位跳变只计一个脉冲。 */

  371.     for (quarter = 0; quarter < 4; quarter++)

  372.     {

  373.         PlsrHwTestAdvanceAbQuarter(0U);

  374.         CHECK(PlsrHwTestGetAbPhaseA(0U) == positiveA[quarter]);

  375.         CHECK(PlsrHwTestGetAbPhaseB(0U) == positiveB[quarter]);

  376.     }

  377.     CHECK(PlsrHwGetEmittedPulses(0U) == 1);

  378.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  379. 

  380.     /* 运行中调频先排队，不能让相差 1/4 周期的两路各自加载 ARR。 */

  381.     oldArr = PlsrHwTestGetArr(0U);

  382.     oldBasePsc = PlsrHwTestGetPsc(0U);

  383.     oldPairPsc = PlsrHwTestGetPsc(1U);

  384.     CHECK(PlsrHwSetFrequency(0U, 2000UL) == PLSR_RESULT_OK);

  385.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  386.     for (quarter = 0; quarter < 4; quarter++)

  387.     {

  388.         PlsrHwTestAdvanceAbQuarter(0U);

  389.     }

  390.     CHECK(PlsrHwGetEmittedPulses(0U) == 2);

  391.     CHECK(PlsrHwTestGetArr(0U) == oldArr);

  392.     CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  393.     CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  394. 

  395.     CHECK(PlsrHwSetFrequency(0U, 2000UL) == PLSR_RESULT_OK);

  396.     CHECK(PlsrHwTestGetAbQuarter(0U) == 0U);

  397.     CHECK(PlsrHwTestGetArr(0U) == oldArr);

  398.     CHECK(PlsrHwTestGetArr(1U) == oldArr);

  399.     CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  400.     CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  401. 

  402.     for (quarter = 0; quarter < 3; quarter++)

  403.     {

  404.         PlsrHwTestAdvanceAbQuarter(0U);

  405.         CHECK(PlsrHwTestGetArr(0U) == oldArr);

  406.         CHECK(PlsrHwTestGetArr(1U) == oldArr);

  407.         CHECK(PlsrHwTestGetPsc(0U) == oldBasePsc);

  408.         CHECK(PlsrHwTestGetPsc(1U) == oldPairPsc);

  409.     }

  410.     /* 回到 00 后，两路同时装载新频率并从精确 90° 位置重启。 */

  411.     PlsrHwTestAdvanceAbQuarter(0U);

  412.     CHECK(PlsrHwGetEmittedPulses(0U) == 3);

  413.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  414.     CHECK((PlsrHwTestGetArr(0U) != oldArr)

  415.           || (PlsrHwTestGetPsc(0U) != oldBasePsc));

  416.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  417.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  418.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  419.     newPeriod = PlsrHwTestGetArr(0U) + 1UL;

  420.     CHECK(PlsrHwTestGetCnt(0U) == (newPeriod * 3UL) / 4UL);

  421.     CHECK(PlsrHwTestGetCnt(1U) == newPeriod / 2UL);

  422. 

  423.     for (quarter = 0; quarter < 4; quarter++)

  424.     {

  425.         PlsrHwTestAdvanceAbQuarter(0U);

  426.     }

  427.     CHECK(PlsrHwGetEmittedPulses(0U) == 4);

  428.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  429.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  430.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  431.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  432.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  433. 

  434.     /* 反向：00→01→11→10→00。 */

  435.     params.targetPulses = 1;

  436.     params.directionPositive = 0U;

  437.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  438.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  439.     for (quarter = 0; quarter < 4; quarter++)

  440.     {

  441.         PlsrHwTestAdvanceAbQuarter(0U);

  442.         CHECK(PlsrHwTestGetAbPhaseA(0U) == negativeA[quarter]);

  443.         CHECK(PlsrHwTestGetAbPhaseB(0U) == negativeB[quarter]);

  444.     }

  445.     CHECK(PlsrHwGetEmittedPulses(0U) == 1);

  446.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  447. 

  448.     /* 紧急停止即使发生在周期中间，也必须回到安全 00。 */

  449.     params.targetPulses = 10;

  450.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  451.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  452.     PlsrHwTestAdvanceAbQuarter(0U);

  453.     CHECK(PlsrHwTestGetAbQuarter(0U) == 1U);

  454.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  455.     CHECK(PlsrHwTestGetAbQuarter(0U) == 0U);

  456.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  457.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 0U);

  458. }

  459. 

  460. static void TestTwoAbAxesIndependent(void)

  461. {

  462.     PLSR_HW_START_PARAMS params;

  463.     int quarter;

  464. 

  465.     (void)PlsrHwInit();

  466.     (void)memset(&params, 0, sizeof(params));

  467.     params.frequencyHz = 1000UL;

  468.     params.targetPulses = 1;

  469.     params.outputMode = PLSR_OUTPUT_AB;

  470.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  471.     params.directionPositive = 1U;

  472. 

  473.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  474.     CHECK(PlsrHwStartPulse(2U, &params) == PLSR_RESULT_OK);

  475.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  476.     CHECK(PlsrHwSetFrequency(2U, 2000UL) == PLSR_RESULT_OK);

  477.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  478.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  479.     CHECK(PlsrHwTestGetPwmEnabled(2U) != 0U);

  480.     CHECK(PlsrHwTestGetPwmEnabled(3U) != 0U);

  481. 

  482.     TestCompleteFirstAbPrime(0U);

  483.     TestCompleteFirstAbPrime(2U);

  484. 

  485.     for (quarter = 0; quarter < 4; quarter++)

  486.     {

  487.         PlsrHwTestAdvanceAbQuarter(0U);

  488.     }

  489.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  490.     CHECK(PlsrHwGetState(2U) == PLSR_HW_STATE_RUNNING);

  491.     CHECK(PlsrHwGetEmittedPulses(2U) == 0);

  492.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  493.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  494.     CHECK(PlsrHwTestGetPwmEnabled(2U) != 0U);

  495.     CHECK(PlsrHwTestGetPwmEnabled(3U) != 0U);

  496. 

  497.     for (quarter = 0; quarter < 4; quarter++)

  498.     {

  499.         PlsrHwTestAdvanceAbQuarter(2U);

  500.     }

  501.     CHECK(PlsrHwGetState(2U) == PLSR_HW_STATE_DONE);

  502.     CHECK(PlsrHwGetEmittedPulses(2U) == 1);

  503. }

  504. 

  505. static void TestAbFrequencyLimits(void)

  506. {

  507.     PLSR_HW_START_PARAMS params;

  508.     int quarter;

  509. 

  510.     (void)PlsrHwInit();

  511.     (void)memset(&params, 0, sizeof(params));

  512.     params.frequencyHz = 1UL;

  513.     params.targetPulses = 100;

  514.     params.outputMode = PLSR_OUTPUT_AB;

  515.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  516.     params.directionPositive = 1U;

  517. 

  518.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  519.     CHECK(PlsrHwSetFrequency(0U, 1UL) == PLSR_RESULT_OK);

  520.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  521.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  522.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  523.     CHECK(PlsrHwTestGetArr(0U) <= 65535UL);

  524. 

  525.     TestCompleteFirstAbPrime(0U);

  526. 

  527.     CHECK(PlsrHwSetFrequency(0U, 100000UL) == PLSR_RESULT_OK);

  528.     for (quarter = 0; quarter < 4; quarter++)

  529.     {

  530.         PlsrHwTestAdvanceAbQuarter(0U);

  531.     }

  532.     CHECK(PlsrHwTestGetArr(0U) == PlsrHwTestGetArr(1U));

  533.     CHECK((PlsrHwTestGetPsc(0U) + 1UL)

  534.           == 2UL * (PlsrHwTestGetPsc(1U) + 1UL));

  535.     CHECK(PlsrHwTestGetArr(0U) >= 3UL);

  536.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  537. }

  538. 

  539. static void TestStopAndInvalidArgs(void)

  540. {

  541.     (void)PlsrHwInit();

  542.     PLSR_HW_START_PARAMS params;

  543. 

  544.     (void)memset(&params, 0, sizeof(params));

  545.     params.frequencyHz = 1000UL;

  546.     params.targetPulses = 100;

  547.     params.directionPoint = PLSR_HW_DIR_POINT_NONE;

  548.     params.directionPositive = 1U;

  549.     params.directionDelayMs = 0U;

  550. 

  551.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_OK);

  552.     CHECK(PlsrHwSetFrequency(0U, 1000UL) == PLSR_RESULT_OK);

  553.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  554.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  555.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  556.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  557.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  558. 

  559.     CHECK(PlsrHwStartPulse(4U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  560.     CHECK(PlsrHwStartPulse(0U, NULL) == PLSR_RESULT_INVALID_ARGUMENT);

  561.     params.targetPulses = 0;

  562.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  563.     params.targetPulses = 1;

  564.     params.outputMode = PLSR_OUTPUT_CW_CCW;

  565.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_NOT_SUPPORTED);

  566.     params.outputMode = (PLSR_OUTPUT_MODE)99;

  567.     CHECK(PlsrHwStartPulse(0U, &params) == PLSR_RESULT_INVALID_ARGUMENT);

  568.     CHECK(PlsrHwSetFrequency(4U, 1000UL) == PLSR_RESULT_INVALID_ARGUMENT);

  569.     CHECK(PlsrHwStopPulse(4U) == PLSR_RESULT_INVALID_ARGUMENT);

  570. }

  571. 

  572. /* ---- 端到端集成：START → 硬件 → 计数 → 事件 → 段间 → 完成 ---- */

  573. 

  574. static void TestEndToEndTwoSegments(void)

  575. {

  576.     TEST_MEMORY memory;

  577.     PLSR_CALL call;

  578.     PLSR_STATUS status;

  579.     uint16_t initialPsc;

  580.     uint16_t initialArr;

  581.     int ticks;

  582.     int pulse;

  583. 

  584.     TestResetEnvironment();

  585.     (void)memset(&memory, 0, sizeof(memory));

  586.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 2);

  587.     TestSetSegment(&memory, 1U, 1000U, 100);

  588.     TestSetSegment(&memory, 2U, 2000U, 200);

  589. 

  590.     call = TestMakeCall(&memory);

  591.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  592.     PlsrProcess();

  593.     status = TestGetStatus();

  594.     CHECK(status.state == PLSR_STATE_ACCEL);

  595.     CHECK(status.currentSegment == 1U);

  596.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DIR_SETTLING);

  597. 

  598.     /* DIR 延时 10ms → PWM 启动（段1 起始速度 0，profile 升频后启动）。 */

  599.     for (ticks = 0; ticks < 9; ticks++)

  600.     {

  601.         PlsrProcess();

  602.     }

  603.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  604.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 1U);

  605.     CHECK(PlsrCalculateTimerDivider(168000000UL, 75UL,

  606.                                     &initialPsc, &initialArr)

  607.           == PLSR_RESULT_OK);

  608.     CHECK(PlsrHwTestGetPsc(0U) == initialPsc);

  609.     CHECK(PlsrHwTestGetArr(0U) == initialArr);

  610. 

  611.     /* 加速完成 → 状态机进入 RUN。 */

  612.     for (ticks = 0; ticks < 500; ticks++)

  613.     {

  614.         PlsrProcess();

  615.         if (TestGetStatus().state == PLSR_STATE_RUN)

  616.         {

  617.             break;

  618.         }

  619.     }

  620.     status = TestGetStatus();

  621.     CHECK(status.state == PLSR_STATE_RUN);

  622.     CHECK(status.currentSegment == 1U);

  623. 

  624.     /* 段1 脉冲完成：100 次更新中断 → SEGMENT_COMPLETE → 段2 启动。 */

  625.     for (pulse = 0; pulse < 100; pulse++)

  626.     {

  627.         PlsrHwTestTriggerUpdate(0U);

  628.     }

  629.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  630.     PlsrProcess();

  631.     status = TestGetStatus();

  632.     CHECK(status.state == PLSR_STATE_ACCEL);

  633.     CHECK(status.currentSegment == 2U);

  634.     CHECK(status.logicalPosition == 100);

  635.     CHECK(status.taskPulses == 100);

  636.     CHECK(status.totalPulses == 100);

  637.     CHECK(TestReadSdDword(1000U) == 2);

  638.     CHECK(TestReadSdDword(1002U) == 0);

  639. 

  640.     /* 段2：DIR 延时 → PWM → 加速 → RUN。 */

  641.     for (ticks = 0; ticks < 600; ticks++)

  642.     {

  643.         PlsrProcess();

  644.         if (TestGetStatus().state == PLSR_STATE_RUN)

  645.         {

  646.             break;

  647.         }

  648.     }

  649.     status = TestGetStatus();

  650.     CHECK(status.state == PLSR_STATE_RUN);

  651.     CHECK(status.currentSegment == 2U);

  652. 

  653.     /* 段2 脉冲完成 → 任务结束。 */

  654.     for (pulse = 0; pulse < 200; pulse++)

  655.     {

  656.         PlsrHwTestTriggerUpdate(0U);

  657.     }

  658.     PlsrProcess();

  659.     status = TestGetStatus();

  660.     CHECK(status.state == PLSR_STATE_COMPLETED);

  661.     CHECK(status.done != 0U);

  662.     CHECK(status.logicalPosition == 300);

  663.     CHECK(status.taskPulses == 300);

  664.     CHECK(status.totalPulses == 300);

  665.     CHECK(TestReadSdDword(1000U) == 2);

  666.     CHECK(TestReadSdDword(1002U) == 200);

  667.     CHECK(TestReadSdDword(1004U) == 200);

  668.     CHECK(TestReadSdDword(1006U) == 0);

  669.     {

  670.         int32_t hsdPulses;

  671.         int32_t hsdEquivalent;

  672. 

  673.         CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  674.         CHECK(hsdPulses == 300);

  675.         CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent)

  676.               == PLC_DEVICE_OK);

  677.         CHECK(hsdEquivalent == 300);

  678.     }

  679.     /* 终态转换后 HAL 回 IDLE（允许重新启动），脉冲已停止。 */

  680.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  681.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  682. }

  683. 

  684. static void TestEndToEndAbSegment(void)

  685. {

  686.     TEST_MEMORY memory;

  687.     PLSR_CALL call;

  688.     PLSR_STATUS status;

  689.     int quarter;

  690. 

  691.     TestResetEnvironment();

  692.     (void)memset(&memory, 0, sizeof(memory));

  693.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  694.     TestSetSegment(&memory, 1U, 1000U, -2);

  695. 

  696.     call = TestMakeCall(&memory);

  697.     call.sequence = 15UL;

  698.     call.outputModeOverride = PLSR_OUTPUT_AB;

  699.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  700.     PlsrProcess();

  701.     status = TestGetStatus();

  702.     CHECK(status.state == PLSR_STATE_ACCEL);

  703.     CHECK(status.outputMode == PLSR_OUTPUT_AB);

  704.     CHECK(status.directionPoint == PLSR_DIRECTION_POINT_NONE);

  705.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  706.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  707.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  708. 

  709.     TestCompleteFirstAbPrime(0U);

  710. 

  711.     /* 负脉冲选择反向相序，完整两个周期后由同一事件链结束任务。 */

  712.     PlsrHwTestAdvanceAbQuarter(0U);

  713.     CHECK(PlsrHwTestGetAbPhaseA(0U) == 0U);

  714.     CHECK(PlsrHwTestGetAbPhaseB(0U) == 1U);

  715.     for (quarter = 1; quarter < 8; quarter++)

  716.     {

  717.         PlsrHwTestAdvanceAbQuarter(0U);

  718.     }

  719.     CHECK(PlsrHwGetEmittedPulses(0U) == 2);

  720.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_DONE);

  721.     PlsrProcess();

  722.     status = TestGetStatus();

  723.     CHECK(status.state == PLSR_STATE_COMPLETED);

  724.     CHECK(status.done != 0U);

  725.     CHECK(status.directionPositive == 0U);

  726.     CHECK(status.logicalPosition == -2);

  727.     CHECK(status.taskPulses == -2);

  728.     CHECK(status.totalPulses == 2);

  729.     CHECK(TestReadSdDword(1002U) == -2);

  730.     CHECK(TestReadSdDword(1004U) == -2);

  731.     CHECK(status.highResourceMask == 0U);

  732.     CHECK(PlsrHwTestGetPwmEnabled(0U) == 0U);

  733.     CHECK(PlsrHwTestGetPwmEnabled(1U) == 0U);

  734. }

  735. 

  736. static void TestPositionOnImmediateStop(void)

  737. {

  738.     TEST_MEMORY memory;

  739.     PLSR_CALL call;

  740.     PLSR_COMMAND command;

  741.     PLSR_STATUS status;

  742.     int pulse;

  743.     int tick;

  744. 

  745.     TestResetEnvironment();

  746.     (void)memset(&memory, 0, sizeof(memory));

  747.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  748.     TestSetSegment(&memory, 1U, 1000U, 100);

  749.     call = TestMakeCall(&memory);

  750.     call.sequence = 30UL;

  751.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  752.     PlsrProcess();

  753.     for (tick = 0; tick < 10; tick++)

  754.     {

  755.         PlsrProcess();

  756.     }

  757.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  758. 

  759.     for (pulse = 0; pulse < 37; pulse++)

  760.     {

  761.         PlsrHwTestTriggerUpdate(0U);

  762.     }

  763.     PlsrProcess();

  764.     status = TestGetStatus();

  765.     CHECK(status.logicalPosition == 37);

  766.     CHECK(status.taskPulses == 37);

  767.     CHECK(status.totalPulses == 37);

  768. 

  769.     command.sequence = 31UL;

  770.     command.axis = 0U;

  771.     command.opcode = PLSR_CMD_STOP_IMMEDIATE;

  772.     command.argument = 0;

  773.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  774.     PlsrProcess();

  775.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  776.     CHECK(PlsrPostEvent(0U, PLSR_EVENT_STOP_IMMEDIATE_DONE)

  777.           == PLSR_RESULT_OK);

  778.     PlsrProcess();

  779.     status = TestGetStatus();

  780.     CHECK(status.state == PLSR_STATE_STOPPED);

  781.     CHECK(status.logicalPosition == 37);

  782.     CHECK(status.taskPulses == 37);

  783.     CHECK(status.totalPulses == 37);

  784.     CHECK(TestReadSdDword(1002U) == 37);

  785. 

  786.     command.sequence = 32UL;

  787.     command.opcode = PLSR_CMD_CLEAR_TOTAL;

  788.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  789.     PlsrProcess();

  790.     status = TestGetStatus();

  791.     CHECK(status.logicalPosition == 37);

  792.     CHECK(status.totalPulses == 0);

  793. }

  794. 

  795. static void TestAbsolutePositionAccounting(void)

  796. {

  797.     TEST_MEMORY memory;

  798.     PLSR_CALL call;

  799.     PLSR_COMMAND command;

  800.     PLSR_STATUS status;

  801.     int32_t hsdPosition;

  802.     int pulse;

  803.     int tick;

  804. 

  805.     TestResetEnvironment();

  806.     command.sequence = 40UL;

  807.     command.axis = 0U;

  808.     command.opcode = PLSR_CMD_SET_POSITION;

  809.     command.argument = 100;

  810.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  811.     PlsrProcess();

  812. 

  813.     (void)memset(&memory, 0, sizeof(memory));

  814.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  815.     TestSetSegment(&memory, 1U, 1000U, 130);

  816.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S1_BASE, 1);

  817.     call = TestMakeCall(&memory);

  818.     call.sequence = 41UL;

  819.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  820.     PlsrProcess();

  821.     for (tick = 0; tick < 10; tick++)

  822.     {

  823.         PlsrProcess();

  824.     }

  825.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  826.     for (pulse = 0; pulse < 30; pulse++)

  827.     {

  828.         PlsrHwTestTriggerUpdate(0U);

  829.     }

  830.     PlsrProcess();

  831.     status = TestGetStatus();

  832.     CHECK(status.state == PLSR_STATE_COMPLETED);

  833.     CHECK(status.logicalPosition == 130);

  834.     CHECK(status.taskPulses == 30);

  835.     CHECK(status.totalPulses == 30);

  836.     CHECK(status.positionValid != 0U);

  837.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPosition) == PLC_DEVICE_OK);

  838.     CHECK(hsdPosition == 130);

  839. }

  840. 

  841. static void TestEquivalentRemainderAccounting(void)

  842. {

  843.     TEST_MEMORY memory;

  844.     PLSR_CALL call;

  845.     PLSR_STATUS status;

  846.     int32_t hsdPulses;

  847.     int32_t hsdEquivalent;

  848. 

  849.     TestResetEnvironment();

  850.     CHECK(PlcDeviceWriteSfd(900U, (1U << 8U)) == PLC_DEVICE_OK);

  851.     TestWriteSfdDword(902U, 3UL);

  852.     TestWriteSfdDword(904U, 2UL);

  853.     TestWriteSfdDword(956U, 60000UL);

  854.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  855. 

  856.     (void)memset(&memory, 0, sizeof(memory));

  857.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  858.     TestSetSegment(&memory, 1U, 1000U, 1);

  859.     call = TestMakeCall(&memory);

  860.     call.sequence = 30UL;

  861.     call.outputModeOverride = PLSR_OUTPUT_PULSE_DIR;

  862. 

  863.     /* 3脉冲/2单位：第一次1单位只输出1脉冲并保存1/2余数。 */

  864.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  865.     PlsrProcess();

  866.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  867.     PlsrHwTestTriggerUpdate(0U);

  868.     PlsrProcess();

  869.     status = TestGetStatus();

  870.     CHECK(status.state == PLSR_STATE_COMPLETED);

  871.     CHECK(status.logicalPosition == 1);

  872.     CHECK(status.taskPulses == 1);

  873.     CHECK(status.totalPulses == 1);

  874.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  875.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  876.     CHECK(hsdPulses == 1);

  877.     CHECK(hsdEquivalent == 0);

  878. 

  879.     /* 第二次1单位合并余数后输出2脉冲；两次合计精确为3脉冲/2单位。 */

  880.     call.sequence = 31UL;

  881.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  882.     PlsrProcess();

  883.     PlsrHwTestTriggerUpdate(0U);

  884.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  885.     PlsrHwTestTriggerUpdate(0U);

  886.     PlsrProcess();

  887.     status = TestGetStatus();

  888.     CHECK(status.state == PLSR_STATE_COMPLETED);

  889.     CHECK(status.logicalPosition == 3);

  890.     CHECK(status.taskPulses == 2);

  891.     CHECK(status.totalPulses == 3);

  892.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  893.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  894.     CHECK(hsdPulses == 3);

  895.     CHECK(hsdEquivalent == 2);

  896.     CHECK(TestReadSdDword(1002U) == 2);

  897.     CHECK(TestReadSdDword(1004U) == 1);

  898. }

  899. 

  900. static void TestEquivalentCompatibleError(void)

  901. {

  902.     TEST_MEMORY memory;

  903.     PLSR_CALL call;

  904.     PLSR_STATUS status;

  905.     int32_t errorCode = -1;

  906.     int32_t errorBlock = -1;

  907. 

  908.     TestResetEnvironment();

  909.     CHECK(PlcDeviceWriteSfd(900U, (1U << 8U)) == PLC_DEVICE_OK);

  910.     TestWriteSfdDword(902U, 0UL);

  911.     TestWriteSfdDword(904U, 2UL);

  912.     TestWriteSfdDword(956U, 60000UL);

  913. 

  914.     (void)memset(&memory, 0, sizeof(memory));

  915.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  916.     TestSetSegment(&memory, 1U, 1000U, 1);

  917.     call = TestMakeCall(&memory);

  918.     call.sequence = 32UL;

  919.     call.outputModeOverride = PLSR_OUTPUT_PULSE_DIR;

  920. 

  921.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  922.     PlsrProcess();

  923.     status = TestGetStatus();

  924.     CHECK(status.lastCommandResult == PLSR_RESULT_INVALID_S2);

  925.     CHECK(status.state == PLSR_STATE_IDLE);

  926.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  927.     CHECK(PlcDeviceReadSd(1011U, &errorBlock) == PLC_DEVICE_OK);

  928.     CHECK(errorCode == 2);

  929.     CHECK(errorBlock == 0);

  930. 

  931.     /* A valid retry clears the compatible parameter error. */

  932.     TestWriteSfdDword(902U, 3UL);

  933.     call.sequence = 33UL;

  934.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  935.     PlsrProcess();

  936.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  937.     CHECK(errorCode == 0);

  938.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  939. }

  940. 

  941. static void TestSoftLimitAndSegmentEvent(void)

  942. {

  943.     TEST_MEMORY memory;

  944.     PLSR_CALL call;

  945.     PLSR_COMMAND command;

  946.     PLSR_STATUS status;

  947.     PLC_DEVICE_EVENT_RECORD eventRecord;

  948.     int32_t errorCode;

  949.     int pulse;

  950.     int tick;

  951. 

  952.     TestResetEnvironment();

  953.     CHECK(PlcDeviceWriteSfd(900U, (1U << 2U)) == PLC_DEVICE_OK);

  954.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  955.     CHECK(PlcDeviceWriteSfd(912U, 0U) == PLC_DEVICE_OK);

  956.     CHECK(PlcDeviceWriteSfd(915U, 0xFFFFU) == PLC_DEVICE_OK);

  957.     TestWriteSfdDword(930U, 100UL);

  958.     TestWriteSfdDword(932U, (uint32_t)(int32_t)-100);

  959. 

  960.     command.sequence = 40UL;

  961.     command.axis = 0U;

  962.     command.opcode = PLSR_CMD_SET_POSITION;

  963.     command.argument = 100;

  964.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  965.     PlsrProcess();

  966. 

  967.     (void)memset(&memory, 0, sizeof(memory));

  968.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  969.     TestSetSegment(&memory, 1U, 1000U, 10);

  970.     call = TestMakeCall(&memory);

  971.     call.sequence = 41UL;

  972.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  973.     PlsrProcess();

  974.     status = TestGetStatus();

  975.     CHECK(status.lastCommandResult == PLSR_RESULT_LIMIT_POSITIVE);

  976.     CHECK(status.state == PLSR_STATE_IDLE);

  977.     CHECK(status.positiveLimitActive != 0U);

  978.     CHECK(status.error == PLSR_ERROR_LIMIT_POSITIVE);

  979.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  980.     CHECK(errorCode == 5);

  981. 

  982.     /* 正限位上只禁止正向，反向离开仍可正常完成。 */

  983.     TestSetSegment(&memory, 1U, 1000U, -10);

  984.     call.sequence = 42UL;

  985.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  986.     PlsrProcess();

  987.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  988.     for (pulse = 0; pulse < 10; pulse++)

  989.     {

  990.         PlsrHwTestTriggerUpdate(0U);

  991.     }

  992.     PlsrProcess();

  993.     status = TestGetStatus();

  994.     CHECK(status.state == PLSR_STATE_COMPLETED);

  995.     CHECK(status.logicalPosition == 90);

  996.     CHECK(status.error == PLSR_ERROR_NONE);

  997.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  998.     CHECK(eventRecord.count == 1UL);

  999.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_NORMAL_COMPLETE);

  1000.     CHECK(eventRecord.pending != 0U);

  1001. 

  1002.     /* 运行中按预计制动距离触发软限位，PWM保持运行并按曲线缓停。 */

  1003.     TestResetEnvironment();

  1004.     CHECK(PlcDeviceWriteSfd(900U, (1U << 2U)) == PLC_DEVICE_OK);

  1005.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1006.     TestWriteSfdDword(930U, 50UL);

  1007.     TestWriteSfdDword(932U, (uint32_t)(int32_t)-50);

  1008.     command.sequence = 43UL;

  1009.     command.opcode = PLSR_CMD_SET_POSITION;

  1010.     command.argument = 0;

  1011.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1012.     PlsrProcess();

  1013.     (void)memset(&memory, 0, sizeof(memory));

  1014.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1015.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1016.     call = TestMakeCall(&memory);

  1017.     call.sequence = 44UL;

  1018.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1019.     PlsrProcess();

  1020.     for (pulse = 0; pulse < 49; pulse++)

  1021.     {

  1022.         PlsrHwTestTriggerUpdate(0U);

  1023.     }

  1024.     PlsrProcess();

  1025.     status = TestGetStatus();

  1026.     CHECK(status.state == PLSR_STATE_DECEL);

  1027.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1028.     CHECK(status.positiveLimitActive != 0U);

  1029.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1030.     CHECK(PlcDeviceReadSd(1010U, &errorCode) == PLC_DEVICE_OK);

  1031.     CHECK(errorCode == 5);

  1032.     for (tick = 0; tick < 20; tick++)

  1033.     {

  1034.         PlsrProcess();

  1035.     }

  1036.     status = TestGetStatus();

  1037.     CHECK(status.state == PLSR_STATE_STOPPED);

  1038.     CHECK(status.logicalPosition == 49);

  1039.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1040.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1041.     CHECK(eventRecord.count == 1UL);

  1042.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1043. }

  1044. 

  1045. static void TestHardLimitAndEmergencyLatch(void)

  1046. {

  1047.     TEST_MEMORY memory;

  1048.     PLSR_CALL call;

  1049.     PLSR_COMMAND command;

  1050.     PLSR_STATUS status;

  1051.     PLC_DEVICE_EVENT_RECORD eventRecord;

  1052. 

  1053.     TestResetEnvironment();

  1054.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1055.     CHECK(PlcDeviceWriteSfd(912U, 0U) == PLC_DEVICE_OK);

  1056.     CHECK(PlcDeviceWriteSfd(915U, 0xFF03U) == PLC_DEVICE_OK);

  1057.     (void)memset(&memory, 0, sizeof(memory));

  1058.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1059.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1060.     call = TestMakeCall(&memory);

  1061.     call.sequence = 50UL;

  1062.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1063.     PlsrProcess();

  1064.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1065.     memory.bits[0][3U] = 1U;

  1066.     PlsrProcess();

  1067.     status = TestGetStatus();

  1068.     CHECK(status.state == PLSR_STATE_DECEL);

  1069.     CHECK(status.positiveLimitActive != 0U);

  1070.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1071.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1072.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1073. 

  1074.     TestResetEnvironment();

  1075.     CHECK(PlcDeviceWriteSfd(907U, 0U) == PLC_DEVICE_OK);

  1076.     (void)memset(&memory, 0, sizeof(memory));

  1077.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1078.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1079.     call = TestMakeCall(&memory);

  1080.     call.sequence = 51UL;

  1081.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1082.     PlsrProcess();

  1083.     command.sequence = 52UL;

  1084.     command.axis = 0U;

  1085.     command.opcode = PLSR_CMD_RESET_ERROR;

  1086.     command.argument = 0;

  1087.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1088.     CHECK(PlsrPostEvent(0U,

  1089.                         PLSR_EVENT_LIMIT_POSITIVE

  1090.                             | PLSR_EVENT_SOFTWARE_EMERGENCY)

  1091.           == PLSR_RESULT_OK);

  1092.     PlsrProcess();

  1093.     status = TestGetStatus();

  1094.     CHECK(status.state == PLSR_STATE_STOPPED);

  1095.     CHECK(status.stopReason == PLSR_STOP_REASON_SOFTWARE_EMERGENCY);

  1096.     CHECK(status.error == PLSR_ERROR_EMERGENCY);

  1097.     CHECK(status.emergencyLatched != 0U);

  1098.     CHECK(status.lastCommandSequence == 52UL);

  1099.     CHECK(status.lastCommandResult == PLSR_RESULT_BUSY);

  1100.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1101.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1102.     CHECK(eventRecord.count == 1UL);

  1103.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_SOFTWARE_EMERGENCY);

  1104. 

  1105.     call.sequence = 53UL;

  1106.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1107.     PlsrProcess();

  1108.     status = TestGetStatus();

  1109.     CHECK(status.lastCommandResult == PLSR_RESULT_EMERGENCY_LATCHED);

  1110.     CHECK(status.state == PLSR_STATE_STOPPED);

  1111. 

  1112.     command.sequence = 54UL;

  1113.     command.axis = 0U;

  1114.     command.opcode = PLSR_CMD_RESET_ERROR;

  1115.     command.argument = 0;

  1116.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1117.     PlsrProcess();

  1118.     status = TestGetStatus();

  1119.     CHECK(status.state == PLSR_STATE_IDLE);

  1120.     CHECK(status.error == PLSR_ERROR_NONE);

  1121.     CHECK(status.emergencyLatched == 0U);

  1122. }

  1123. 

  1124. static void TestProductionSelfTestStartsAb(void)

  1125. {

  1126.     PLSR_STATUS status;

  1127. 

  1128.     TestResetEnvironment();

  1129.     CHECK(PlsrSelfTestQueue() == PLSR_RESULT_QUEUED);

  1130.     PlsrProcess();

  1131.     status = TestGetStatus();

  1132.     CHECK(status.lastCommandResult == PLSR_RESULT_OK);

  1133.     CHECK(status.outputMode == PLSR_OUTPUT_AB);

  1134.     CHECK(status.currentSegment == 1U);

  1135.     CHECK(status.state == PLSR_STATE_ACCEL);

  1136.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1137.     CHECK(PlsrHwTestGetPwmEnabled(0U) != 0U);

  1138.     CHECK(PlsrHwTestGetPwmEnabled(1U) != 0U);

  1139.     CHECK(PlsrHwStopPulse(0U) == PLSR_RESULT_OK);

  1140. }

  1141. 

  1142. static void TestEquivalentSelfTest(void)

  1143. {

  1144.     PLSR_STATUS status;

  1145.     int32_t hsdPulses;

  1146.     int32_t hsdEquivalent;

  1147.     int ticks;

  1148. 

  1149.     TestResetEnvironment();

  1150.     CHECK(PlsrEquivalentSelfTestQueue() == PLSR_RESULT_QUEUED);

  1151.     PlsrProcess();

  1152. 

  1153.     /* SFD907=10ms. Advance the simulated hardware delay before segment 1. */

  1154.     for (ticks = 0; ticks < 10; ticks++)

  1155.     {

  1156.         PlsrProcess();

  1157.     }

  1158.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1159. 

  1160.     /* 3 pulses / 2 units: 1001 units emit 1501 pulses and keep 1/2 remainder. */

  1161.     for (ticks = 0; ticks < 1501; ticks++)

  1162.     {

  1163.         PlsrHwTestTriggerUpdate(0U);

  1164.     }

  1165.     PlsrProcess();

  1166.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1167. 

  1168.     /* Segment 2 consumes the remainder and therefore emits 1502 pulses. */

  1169.     for (ticks = 0; ticks < 1502; ticks++)

  1170.     {

  1171.         PlsrHwTestTriggerUpdate(0U);

  1172.     }

  1173.     PlsrProcess();

  1174. 

  1175.     status = TestGetStatus();

  1176.     CHECK(status.lastCommandResult == PLSR_RESULT_OK);

  1177.     CHECK(status.outputMode == PLSR_OUTPUT_PULSE_DIR);

  1178.     CHECK(status.state == PLSR_STATE_COMPLETED);

  1179.     CHECK(status.currentSegment == 2U);

  1180.     CHECK(status.logicalPosition == 3003);

  1181.     CHECK(status.taskPulses == 3003);

  1182.     CHECK(status.totalPulses == 3003);

  1183.     CHECK(PlcDeviceReadHsdDword(0U, &hsdPulses) == PLC_DEVICE_OK);

  1184.     CHECK(PlcDeviceReadHsdDword(2U, &hsdEquivalent) == PLC_DEVICE_OK);

  1185.     CHECK(hsdPulses == 3003);

  1186.     CHECK(hsdEquivalent == 2002);

  1187.     CHECK(TestReadSdDword(1002U) == 1502);

  1188.     CHECK(TestReadSdDword(1004U) == 1001);

  1189. }

  1190. 

  1191. static void TestProtectionSelfTest(void)

  1192. {

  1193.     PLC_DEVICE_EVENT_RECORD eventRecord;

  1194.     PLSR_STATUS status;

  1195.     uint32_t pulseAccumulator = 0UL;

  1196.     int32_t value;

  1197.     int ticks;

  1198. 

  1199.     TestResetEnvironment();

  1200.     CHECK(PlsrProtectionSelfTestQueue() == PLSR_RESULT_QUEUED);

  1201.     PlsrProcess();

  1202. 

  1203.     /* Complete the 10ms direction-settle interval. */

  1204.     for (ticks = 0; ticks < 10; ticks++)

  1205.     {

  1206.         PlsrProcess();

  1207.     }

  1208.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_RUNNING);

  1209. 

  1210.     /* Convert the current frequency into simulated hardware updates over

  1211.      * each 1ms process tick.  This also models the falling pulse density

  1212.      * during the controlled stop. */

  1213.     status = TestGetStatus();

  1214.     for (ticks = 0; ticks < 600; ticks++)

  1215.     {

  1216.         pulseAccumulator += PlsrHwGetCurrentFrequencyHz(0U);

  1217.         while ((pulseAccumulator >= 1000UL)

  1218.                && (PlsrHwIsPulseActive(0U) != 0U))

  1219.         {

  1220.             PlsrHwTestTriggerUpdate(0U);

  1221.             pulseAccumulator -= 1000UL;

  1222.         }

  1223.         PlsrProcess();

  1224.         status = TestGetStatus();

  1225.         if (status.state == PLSR_STATE_STOPPED)

  1226.         {

  1227.             break;

  1228.         }

  1229.     }

  1230. 

  1231.     status = TestGetStatus();

  1232.     CHECK(status.state == PLSR_STATE_STOPPED);

  1233.     CHECK(status.stopReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1234.     CHECK(status.error == PLSR_ERROR_LIMIT_POSITIVE);

  1235.     CHECK(status.emergencyLatched == 0U);

  1236.     CHECK(status.logicalPosition >= 499);

  1237.     CHECK(status.logicalPosition <= 501);

  1238.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1239.     CHECK(PlcDeviceReadSd(1010U, &value) == PLC_DEVICE_OK);

  1240.     CHECK(value == 5U);

  1241.     CHECK(PlcDeviceReadEvent(6000U, &eventRecord) == PLC_DEVICE_OK);

  1242.     CHECK(eventRecord.count == 1UL);

  1243.     CHECK(eventRecord.pending != 0U);

  1244.     CHECK(eventRecord.lastReason == PLSR_STOP_REASON_LIMIT_POSITIVE);

  1245. }

  1246. 

  1247. static void TestFourAxisSelfTest(void)

  1248. {

  1249.     static const uint32_t expectedFrequency[PLSR_AXIS_COUNT] =

  1250.     {

  1251.         1000UL, 2000UL, 3000UL, 4000UL

  1252.     };

  1253.     static const int32_t expectedPulses[PLSR_AXIS_COUNT] =

  1254.     {

  1255.         1000, 2000, 3000, 4000

  1256.     };

  1257.     PLC_DEVICE_EVENT_RECORD eventRecord;

  1258.     PLSR_RESOURCE_STATUS resources;

  1259.     PLSR_STATUS status;

  1260.     int32_t hsdPulses;

  1261.     int subTick;

  1262.     int ticks;

  1263.     uint8_t axis;

  1264. 

  1265.     TestResetEnvironment();

  1266.     CHECK(PlsrFourAxisSelfTestQueue() == PLSR_RESULT_QUEUED);

  1267.     PlsrProcess();

  1268. 

  1269.     for (ticks = 0; ticks < 10; ticks++)

  1270.     {

  1271.         PlsrProcess();

  1272.     }

  1273.     for (axis = 0U; axis < PLSR_AXIS_COUNT; axis++)

  1274.     {

  1275.         CHECK(PlsrGetStatus(axis, &status) == PLSR_RESULT_OK);

  1276.         CHECK(status.state == PLSR_STATE_RUN);

  1277.         CHECK(status.outputMode == PLSR_OUTPUT_PULSE_DIR);

  1278.         CHECK(status.directionPoint == (uint8_t)(4U + axis));

  1279.         CHECK(status.directionPositive != 0U);

  1280.         CHECK(PlsrHwGetState(axis) == PLSR_HW_STATE_RUNNING);

  1281.         CHECK(PlsrHwGetCurrentFrequencyHz(axis)

  1282.               == expectedFrequency[axis]);

  1283.     }

  1284. 

  1285.     /* A 0.25ms base slot produces 1/2/3/4kHz update ratios while all four

  1286.      * hardware channels are active concurrently for one simulated second. */

  1287.     for (subTick = 0; subTick < 4000; subTick++)

  1288.     {

  1289.         if ((subTick & 3) == 0)

  1290.         {

  1291.             PlsrHwTestTriggerUpdate(0U);

  1292.         }

  1293.         if ((subTick & 1) == 0)

  1294.         {

  1295.             PlsrHwTestTriggerUpdate(1U);

  1296.         }

  1297.         if ((subTick & 3) != 3)

  1298.         {

  1299.             PlsrHwTestTriggerUpdate(2U);

  1300.         }

  1301.         PlsrHwTestTriggerUpdate(3U);

  1302. 

  1303.         if ((subTick & 3) == 3)

  1304.         {

  1305.             PlsrProcess();

  1306.         }

  1307.     }

  1308. 

  1309.     for (axis = 0U; axis < PLSR_AXIS_COUNT; axis++)

  1310.     {

  1311.         CHECK(PlsrGetStatus(axis, &status) == PLSR_RESULT_OK);

  1312.         CHECK(status.state == PLSR_STATE_COMPLETED);

  1313.         CHECK(status.stopReason == PLSR_STOP_REASON_NORMAL_COMPLETE);

  1314.         CHECK(status.done != 0U);

  1315.         CHECK(status.logicalPosition == expectedPulses[axis]);

  1316.         CHECK(status.taskPulses == expectedPulses[axis]);

  1317.         CHECK(status.totalPulses == expectedPulses[axis]);

  1318.         CHECK(PlsrHwGetState(axis) == PLSR_HW_STATE_IDLE);

  1319.         CHECK(PlcDeviceReadHsdDword((uint16_t)(axis * 4U),

  1320.                                     &hsdPulses) == PLC_DEVICE_OK);

  1321.         CHECK(hsdPulses == expectedPulses[axis]);

  1322.         CHECK(PlcDeviceReadEvent((uint16_t)(6000U

  1323.                                             + (uint16_t)axis * 100U),

  1324.                                  &eventRecord) == PLC_DEVICE_OK);

  1325.         CHECK(eventRecord.count == 1UL);

  1326.         CHECK(eventRecord.pending != 0U);

  1327.         CHECK(eventRecord.lastReason == PLSR_STOP_REASON_NORMAL_COMPLETE);

  1328.     }

  1329.     PlsrResourceGetStatus(&resources);

  1330.     CHECK(resources.outputMask == 0UL);

  1331.     CHECK(resources.highMask == 0U);

  1332.     CHECK(PlsrResourceCheckInvariant() != 0U);

  1333. }

  1334. 

  1335. static void TestStopStopsHardware(void)

  1336. {

  1337.     TEST_MEMORY memory;

  1338.     PLSR_CALL call;

  1339.     PLSR_COMMAND command;

  1340.     PLSR_STATUS status;

  1341.     int ticks;

  1342. 

  1343.     TestResetEnvironment();

  1344.     (void)memset(&memory, 0, sizeof(memory));

  1345.     TestWriteDword(&memory, PLSR_DEVICE_D, TEST_S0_BASE, 1);

  1346.     TestSetSegment(&memory, 1U, 1000U, 10000);

  1347. 

  1348.     call = TestMakeCall(&memory);

  1349.     call.sequence = 20UL;

  1350.     CHECK(PlsrPostCall(&call) == PLSR_RESULT_QUEUED);

  1351.     PlsrProcess();

  1352.     for (ticks = 0; ticks < 10; ticks++)

  1353.     {

  1354.         PlsrProcess();

  1355.     }

  1356.     CHECK(PlsrHwIsPulseActive(0U) == 1U);

  1357. 

  1358.     /* STOP_IMMEDIATE：硬件立即停止。 */

  1359.     command.sequence = 21UL;

  1360.     command.axis = 0U;

  1361.     command.opcode = PLSR_CMD_STOP_IMMEDIATE;

  1362.     command.argument = 0;

  1363.     CHECK(PlsrPostCommand(&command) == PLSR_RESULT_QUEUED);

  1364.     PlsrProcess();

  1365.     CHECK(PlsrHwIsPulseActive(0U) == 0U);

  1366.     CHECK(PlsrHwGetState(0U) == PLSR_HW_STATE_IDLE);

  1367. 

  1368.     CHECK(PlsrPostEvent(0U, PLSR_EVENT_STOP_IMMEDIATE_DONE)

  1369.           == PLSR_RESULT_OK);

  1370.     PlsrProcess();

  1371.     status = TestGetStatus();

  1372.     CHECK(status.state == PLSR_STATE_STOPPED);

  1373. }

  1374. 

  1375. int main(void)

  1376. {

  1377.     TestMapping();

  1378.     TestDirDelaySequence();

  1379.     TestZeroFrequencyWaits();

  1380.     TestPulseCounting();

  1381.     TestAbPhaseAndCounting();

  1382.     TestTwoAbAxesIndependent();

  1383.     TestAbFrequencyLimits();

  1384.     TestStopAndInvalidArgs();

  1385.     TestEndToEndTwoSegments();

  1386.     TestEndToEndAbSegment();

  1387.     TestPositionOnImmediateStop();

  1388.     TestAbsolutePositionAccounting();

  1389.     TestEquivalentRemainderAccounting();

  1390.     TestEquivalentCompatibleError();

  1391.     TestSoftLimitAndSegmentEvent();

  1392.     TestHardLimitAndEmergencyLatch();

  1393.     TestProductionSelfTestStartsAb();

  1394.     TestEquivalentSelfTest();

  1395.     TestProtectionSelfTest();

  1396.     TestFourAxisSelfTest();

  1397.     TestStopStopsHardware();

  1398. 

  1399.     if (TestFailures != 0)

  1400.     {

  1401.         (void)printf("FAIL: %d of %d PLSR HAL checks failed\n",

  1402.                      TestFailures,

  1403.                      TestChecks);

  1404.         return 1;

  1405.     }

  1406.     (void)printf("PASS: %d PLSR HAL checks\n", TestChecks);

  1407.     return 0;

  1408. }