From ee89720fff64e54fce9d9d4d52cf8087cb42cf40 Mon Sep 17 00:00:00 2001 From: ywh <2227158009@qq.com> Date: Thu, 13 Aug 2026 12:50:03 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=80=E5=A0=86bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 1 + Core/Inc/stm32f4xx_it.h | 2 + Core/Src/main.c | 6 +- Core/Src/stm32f4xx_it.c | 10 +- Document/PLSR_document/PLSR地址映射.md | 147 +- .../PLSR测试报告_2026-08-12.md | 376 ++ .../更新的需求/参数表-2026.xlsx | Bin 0 -> 12541 bytes ...现PLSR指令(2026) - 需求明确版.md | 248 ++ ...现PLSR指令(2026) - 需求明确版.pdf | Bin 0 -> 299297 bytes .../虞文昊_PLSR_2026.8.13.zip | Bin 0 -> 286088 bytes .../PLSR_document/虞文昊_PLSR_2026.8.6.zip | Bin 303852 -> 0 bytes .../~$设计方案书.docx | Bin 0 -> 162 bytes .../设计方案书.docx | Bin 279917 -> 261286 bytes .../需求规格书.docx | Bin 46350 -> 47070 bytes Document/PLSR_document/设计方案书.docx | Bin 261159 -> 261286 bytes EWARM/Modbus.ewp | 30 + .../plsr_control_panel.cpython-314.pyc | Bin 0 -> 65830 bytes .../plsr_modbus_product_test.cpython-314.pyc | Bin 0 -> 135478 bytes HostComputer/plsr_control_panel.py | 212 +- HostComputer/plsr_modbus_product_test.py | 1819 ++++++++- .../Third_Party/Micrium/Config/app_cfg.h | 7 +- Modbus/Inc/modbus_rtu_slave.h | 1 + Modbus/Src/modbus_rtu_slave.c | 43 +- PLSR/Inc/plsr.h | 40 + PLSR/Src/plsr.c | 1474 ++++++- PLSR/Src/plsr_internal.h | 5 + PLSR/Src/plsr_platform.h | 71 +- PLSR/Src/plsr_platform_f407.c | 3383 +++++++++++++++-- tests/plsr_host/test_plsr_host.c | 2161 +++++++++-- 29 files changed, 9180 insertions(+), 856 deletions(-) create mode 100644 Document/PLSR_document/PLSR测试报告_2026-08-12.md create mode 100644 Document/PLSR_document/更新的需求/参数表-2026.xlsx create mode 100644 Document/PLSR_document/更新的需求/实现PLSR指令(2026) - 需求明确版.md create mode 100644 Document/PLSR_document/更新的需求/实现PLSR指令(2026) - 需求明确版.pdf create mode 100644 Document/PLSR_document/虞文昊_PLSR_2026.8.13.zip delete mode 100644 Document/PLSR_document/虞文昊_PLSR_2026.8.6.zip create mode 100644 Document/PLSR_document/虞文昊_PLSR_2026.8.6/~$设计方案书.docx create mode 100644 HostComputer/__pycache__/plsr_control_panel.cpython-314.pyc create mode 100644 HostComputer/__pycache__/plsr_modbus_product_test.cpython-314.pyc diff --git a/.gitignore b/.gitignore index 81d6927..533ef4d 100644 --- a/.gitignore +++ b/.gitignore @@ -26,3 +26,4 @@ .DS_Store Thumbs.db Desktop.ini +tmp/ diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index ae330a9..885d93d 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -64,6 +64,8 @@ void TIM1_UP_TIM10_IRQHandler(void); void TIM8_UP_TIM13_IRQHandler(void); void TIM1_TRG_COM_TIM11_IRQHandler(void); void TIM8_TRG_COM_TIM14_IRQHandler(void); +void TIM1_BRK_TIM9_IRQHandler(void); +void TIM8_BRK_TIM12_IRQHandler(void); /* USER CODE END EFP */ #ifdef __cplusplus diff --git a/Core/Src/main.c b/Core/Src/main.c index f84d298..346df0c 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -75,8 +75,12 @@ static void AppTaskStart(void *pArg) while (1) { - PlsrPoll1ms(); ModbusSlavePoll(); + PlsrPoll1ms(); + if (ModbusSlaveIsIdle() != 0U) + { + PlsrServicePersistence(); + } OSTimeDly(1U); } } diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index 2a13a5c..5da38a8 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -47,7 +47,7 @@ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ - +extern void PlsrPlatformForceSafeOutputsFromFault(void); /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ @@ -89,7 +89,7 @@ void NMI_Handler(void) void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ - + PlsrPlatformForceSafeOutputsFromFault(); /* USER CODE END HardFault_IRQn 0 */ while (1) { @@ -104,7 +104,7 @@ void HardFault_Handler(void) void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - + PlsrPlatformForceSafeOutputsFromFault(); /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { @@ -119,7 +119,7 @@ void MemManage_Handler(void) void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ - + PlsrPlatformForceSafeOutputsFromFault(); /* USER CODE END BusFault_IRQn 0 */ while (1) { @@ -134,7 +134,7 @@ void BusFault_Handler(void) void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ - + PlsrPlatformForceSafeOutputsFromFault(); /* USER CODE END UsageFault_IRQn 0 */ while (1) { diff --git a/Document/PLSR_document/PLSR地址映射.md b/Document/PLSR_document/PLSR地址映射.md index f2016d9..c58c661 100644 --- a/Document/PLSR_document/PLSR地址映射.md +++ b/Document/PLSR_document/PLSR地址映射.md @@ -1,50 +1,121 @@ -# PLSR 地址映射 +# PLSR Modbus 地址映射（2026） -> 文档版本：V1.0 -> 适用轴：Y0～Y3 +> 文档版本：V2.0 +> 字节序：每个 32 位量均为低 16 位字在前、高 16 位字在后 +> 访问方式：配置和控制支持 FC06/FC16，状态和诊断仅支持 FC03 -## 1 固定配置参数 +## 1 固定配置区 `0x1000..0x1197` -| 地址 | 用途 | -|---|---| -| HSD460～539 | K0参数区 | -| SFD900～1419 | 公共参数及K1～K4参数区 | +### 1.1 公共参数 `0x1000..0x1013` -## 2 固定运行状态 +| 地址 | 类型 | 名称 | 取值/单位 | +|---|---|---|---| +| `0x1000` | U16 | 脉冲输出 | `0..3`，对应 Y0..Y3 | +| `0x1001` | U16 | 方向输出 | `0..3`，对应 Y12..Y15；AB 模式忽略 | +| `0x1002` | U16 | 等待输入 | `0=X4`，`1=X5` | +| `0x1003` | U16 | 外部中断输入 | `0=X4`，`1=X5` | +| `0x1004` | U16 | 发送模式 | `0=完整发送`，`1=后续发送` | +| `0x1005` | U16 | 方向延时 | ms；AB 模式忽略 | +| `0x1006` | U16 | 方向负逻辑 | `0/1`；AB 模式忽略 | +| `0x1007` | U16 | 曲线模式 | `0=直线`，`1=S 曲线`，`2=正弦曲线` | +| `0x1008` | U16 | 位置模式 | `0=相对`，`1=绝对` | +| `0x1009` | U16 | 有效段数 | `1..10` | +| `0x100A` | U16 | 起始段 | `1..10`，启动时不得超过有效段数 | +| `0x100B..0x100C` | U32 | 默认速度 | Hz，`1..100000` | +| `0x100D..0x100E` | U32 | 起始速度 | Hz，`0..100000` | +| `0x100F` | U16 | 保留 | 读为 0，仅允许写 0 | +| `0x1010..0x1011` | U32 | 停止速度 | Hz，`0..100000` | +| `0x1012` | U16 | 加速时间 | ms | +| `0x1013` | U16 | 减速时间 | ms | -| 地址 | 用途 | -|---|---| -| HSD0～15 | 累计脉冲状态 | -| SM1000、SM1001 | Y0运行和方向状态 | -| SM1020、SM1021 | Y1运行和方向状态 | -| SM1040、SM1041 | Y2运行和方向状态 | -| SM1060、SM1061 | Y3运行和方向状态 | -| SD1000～1011 | Y0实时运行状态 | -| SD1020～1031 | Y1实时运行状态 | -| SD1040～1051 | Y2实时运行状态 | -| SD1060～1071 | Y3实时运行状态 | +`0x1014..0x10FF` 为保留区，读为 0，仅允许写 0。32 位参数必须在同一次请求中完整访问两个寄存器。 -## 3 固定事件入口 +### 1.2 分段参数 `0x1100..0x1197` -| 地址 | 用途 | -|---|---| -| I6000～6399 | Y0～Y3每段事件入口 | +第 `n` 段（`n=1..10`）首地址为 `0x1100 + (n-1)*0x10`。 -## 4 动态数据地址 +| 段内偏移 | 类型 | 名称 | 取值/单位 | +|---|---|---|---| +| `+0x0..+0x1` | U32 | 段频率 | Hz，`1..100000` | +| `+0x2..+0x3` | I32 | 位移/脉冲数 | 正数为正向，负数为反向 | +| `+0x4` | U16 | 等待类型 | `0=定时等待`，`1=信号等待`，`2=定时动作`，`3=外部信号`，`4=外部或完成` | +| `+0x5` | U16 | 等待时间 | ms | +| `+0x6` | U16 | 动作时间 | ms | +| `+0x7` | U16 | 跳转段 | `0=不跳转`，`1..10=目标段` | +| `+0x8..+0xF` | U16 | 保留 | 读为 0，仅允许写 0 | -| 地址 | 用途 | -|---|---| -| S0 | 路径数据块，首地址动态指定 | -| S1 | 执行参数块，首地址动态指定 | +## 2 扩展配置区 `0x1200` -汇总 +| 地址 | 类型 | 名称 | 取值 | +|---|---|---|---| +| `0x1200` | U16 | 输出模式 | `0=PULSE/DIR`，`1=AB 正交脉冲` | +该参数参与持久化。AB 模式只允许 `0x1000=0`（Y0/Y1）或 `0x1000=2`（Y2/Y3）；其他组合返回非法数据值。运行期间不得修改输出模式或脉冲输出。 -| 类别 | 固定地址 | -|---|---:| -| K0参数 | HSD460～539 | -| 公共参数及K1～K4参数 | SFD900～1419 | -| 累计脉冲状态 | HSD0～15 | -| 正在发脉冲、方向标志 | SM1000~SM1001、SM1020~SM1021、SM1040~SM1041、SM1060~SM1061 | -| 实时运行状态 | SD1000～1011、SD1020～1031、SD1040～1051、SD1060～1071 | -| 每段事件入口 | I6000～6099、I6100～6199、I6200～6299、I6300～6399 | \ No newline at end of file +AB 模式的频率单位是完整正交周期/秒，一个 `00` 起止的四状态周期等于一个指令脉冲： + +- 正向：`00 -> 10 -> 11 -> 01 -> 00` +- 反向：`00 -> 01 -> 11 -> 10 -> 00` + +方向由段位移的符号决定。独立 DIR 输出、DIR 极性和 DIR 延时在 AB 模式中不参与输出。 + +## 3 固定状态区 `0x2000..0x2006`（只读） + +| 地址 | 类型 | 名称 | 说明 | +|---|---|---|---| +| `0x2000..0x2001` | I32 | 当前位置 | 累计指令脉冲位置 | +| `0x2002..0x2003` | U32 | 当前频率 | Hz | +| `0x2004` | U16 | 运行状态 | `0=未初始化`，`1=空闲`，`2=加速`，`3=运行`，`4=减速`，`5=等待`，`6=暂停`，`7=完成`，`8=停止`，`9=错误` | +| `0x2005` | U16 | 当前段 | `0=无`，`1..10=段号` | +| `0x2006` | U16 | 错误码 | `0=无错误`，其余见 `PLSR_ERROR` 定义 | + +## 4 扩展诊断区 `0x2100..0x2119`（只读） + +| 地址 | 类型 | 名称 | 说明 | +|---|---|---|---| +| `0x2100` | U16 | 诊断标志 | 位定义见下表 | +| `0x2101` | U16 | 首个锁存原因 | `0=无`，`1=计数`，`2=频率`，`3=曲线`，`4=无效采样` | +| `0x2102` | U16 | 段号 | 当前或末次诊断段 | +| `0x2103` | U16 | 模式与方向 | bit0..7=输出模式，bit8=`1` 正向/`0` 反向 | +| `0x2104..0x2105` | U32 | 期望脉冲数 | 当前或末次诊断段的完整指令脉冲数 | +| `0x2106..0x2107` | U32 | 实测脉冲数 | 当前或末次诊断段的实测值；目标板来自独立硬件计数链 | +| `0x2108..0x2109` | I32 | 计数误差 | `实测 - 期望` | +| `0x210A..0x210B` | U32 | 请求频率 | Hz，规划器本次请求值 | +| `0x210C..0x210D` | U32 | 期望定时器频率 | Hz，根据实际 PSC/ARR 可实现的量化值 | +| `0x210E..0x210F` | U32 | 活动定时器频率 | Hz，实际生效的定时器配置值 | +| `0x2110..0x2111` | I32 | 请求量化误差 | `期望定时器频率 - 请求频率`，Hz | +| `0x2112..0x2113` | U32 | 采样数 | 本次诊断累计的有效样本数 | +| `0x2114..0x2115` | U32 | 不匹配数 | 频率或曲线不匹配的累计样本数 | +| `0x2116..0x2117` | U32 | 最大频率误差 | `abs(活动定时器频率 - 期望定时器频率)`，Hz | +| `0x2118..0x2119` | U32 | 首个不匹配样本 | 无不匹配时为 `0xFFFFFFFF` | + +`0x2100` 标志位： + +| 位 | 名称 | 置位条件 | +|---|---|---| +| bit0 | `monitoring_active` | 正在采集诊断数据 | +| bit1 | `count_checked` | 已完成计数核对 | +| bit2 | `count_pass` | 计数核对通过 | +| bit3 | `frequency_checked` | 已执行频率核对 | +| bit4 | `frequency_pass` | 频率核对通过 | +| bit5 | `curve_checked` | 已执行加减速次序核对 | +| bit6 | `curve_pass` | 曲线核对通过 | +| bit7 | `fault_latched` | 至少一个诊断故障已锁存 | + +诊断使用定时器分频值、完整周期计数和频率变化次序核对输出配置。它能发现内部计数、频率和曲线不一致，但不能代替逻辑分析仪对端子占空比、窄脉冲或电气波形的验收。 + +## 5 控制区 + +| 地址 | 类型 | 名称 | 写入值 | +|---|---|---|---| +| `0x3000` | U16 | PLSR 命令 | `0=无操作`，`1=START`，`2=STOP`，`4=CLEAR` | +| `0x3100` | U16 | 诊断控制 | `0=无操作`，`1=清除诊断锁存和统计` | + +控制寄存器读取恒为 0。除上述单一值外的位组合均返回非法数据值。 +运行期间写 `0x3100=1` 返回设备忙，避免清除正在采集的诊断上下文。 + +## 6 地址边界 + +- 原固定区 `0x1000..0x1197`、`0x2000..0x2006`、`0x3000` 保持不变。 +- 扩展区仅增加 `0x1200`、`0x2100..0x2119`、`0x3100`。 +- 完全落在 PLSR 地址之外的请求返回“不处理”，跨越 PLSR 地址与空洞的请求返回“非法地址”。 diff --git a/Document/PLSR_document/PLSR测试报告_2026-08-12.md b/Document/PLSR_document/PLSR测试报告_2026-08-12.md new file mode 100644 index 0000000..f54d829 --- /dev/null +++ b/Document/PLSR_document/PLSR测试报告_2026-08-12.md @@ -0,0 +1,376 @@ +# PLSR 2026 重写测试报告 + +> 测试日期：2026-08-12 +> +> 测试分支：`codex/plsr-2026-minimal` +> +> 测试代码基线：`bf314a2343002a3df78bce5049badb29d11eae2e` +> +> PLSR 实现提交：`c7b851659ea26f9af8563e146bf5332c3c8d6dfd` +> +> 分支起点：`e35595aae18690a46a03445865bd6218a166bd89` +> +> 结论口径：只记录本次 2026 PLSR 最小重写实际执行过的测试 + +## 1. 总结 + +本次重写的 Host 回归、Python 离线自检、IAR 全量构建、固件烧录、真实 Modbus RTU 板测、Y0～Y3 逐路选择、X4/X5 实体回环、硬复位持久化和最终默认状态复核均通过。 + +| 类别 | 最终结果 | 数量或关键结果 | +|---|---|---| +| C Host 回归 | PASS | 44 个测试组，1,694,007 次断言，0 失败 | +| Python 产品测试脚本离线自检 | PASS | 未打开串口 | +| Python 控制面板离线自检 | PASS | 未打开 GUI 或串口 | +| IAR EWARM 全量构建 | PASS | 0 errors，0 warnings | +| 固件烧录和校验 | PASS | `Verification...OK`，SHA256 与板测固件一致 | +| Modbus RTU/运动板测 | PASS | 9 组 | +| X4/X5 实体回环板测 | PASS | 9 个用例 | +| 硬复位持久化 | PASS | 配置和位置恢复，运动不自动续跑 | +| 最终默认状态复核 | PASS | 位置、配置、输入和夹具输出均恢复 | +| 逻辑分析仪测试 | 未执行 | 不在本轮验收范围内 | + +这里的“Y0～Y3 验证”是**同一个逻辑 PLSR 依次选择 Y0、Y1、Y2、Y3 作为脉冲输出**，不是四轴同时运动或四轴联动。 + +`1,694,007 assertions` 是逐脉冲检查、边界检查和随机算术比对产生的断言总数，不代表 169 万个独立测试场景。 + +## 2. 测试范围和口径 + +### 2.1 纳入本报告 + +- 本次重写新增的固定产品寄存器区：`0x1000～0x1197`、`0x2000～0x2006`、`0x3000`。 +- 单个逻辑 PLSR 的配置、状态、控制、运动、短段曲线、动态调频和停止。 +- 单个逻辑 PLSR 对 Y0～Y3 的逐路选择。 +- X4/X5 的 WAIT、EXT 和 EXT_OR_COMPLETE 实体输入回环。 +- 产品配置与逻辑位置的保存、硬复位恢复和默认值恢复。 +- 最小 Modbus RTU 的真实串口访问和异常响应。 +- 当前代码基线的 Host、Python、IAR 和固件产物复核。 + +### 2.2 不纳入本报告 + +旧工程曾做过的四轴并发、双 AB、软限位、长稳、USB CDC 并发和逻辑分析仪波形测试属于另一套实现，不能作为本次重写的通过证据，因此没有合并到本报告。 + +## 3. 环境与产物 + +| 项目 | 实际环境或结果 | +|---|---| +| 目标板 | 信捷 XDM-60T4-E，STM32F407IG | +| RTOS | uC/OS-II | +| 串口 | `COM5`，9600 bit/s，8E1，从站 1 | +| Host 编译器 | GCC 4.9.2 (`tdm64-1`) | +| Host 编译选项 | C99，`-Wall -Wextra -Werror`，`PLSR_HOST_TEST` | +| IAR | EWARM 8.3.4，配置 `Modbus` | +| IAR 工程 | `EWARM/Modbus.ewp` | +| HEX | `EWARM/Modbus/Exe/Modbus.hex` | +| HEX 文本文件大小 | 142,131 B | +| Intel HEX 有效数据 | 50,513 B | +| HEX 地址范围 | `0x08000000..0x0800C550` | +| SHA256 | `97956D9EF30A9B274140B9B82F412EDD77F9637F563FCC3F552BB4B140772343` | + +IAR 链接结果： + +```text +49,004 bytes of readonly code memory + 1,509 bytes of readonly data memory +18,660 bytes of readwrite data memory +Errors: none +Warnings: none +``` + +## 4. 最终自动化回归 + +### 4.1 C Host 回归 + +执行命令： + +```powershell +powershell.exe -NoProfile -ExecutionPolicy Bypass ` + -File .\tests\plsr_host\run_tests.ps1 +``` + +最终输出： + +```text +SUMMARY tests=44 assertions=1694007 failures=0 +``` + +44 个测试组全部 PASS： + +| # | 测试组 | 实际验证内容 | +|---:|---|---| +| 1 | `u64_by_u32_division` | 用 8 个边界被除数、9 个边界除数和 250,000 组确定性伪随机数据，比对 64 位除 32 位算法与 C 原生除法的商和余数。 | +| 2 | `protocol_boundaries` | 覆盖区间外、跨区、地址溢出、零长度、空缓冲、只读区、保留字、32 位字段不完整写入、非法值和控制字宽度，并确认失败写入不破坏原值。 | +| 3 | `wait_zero_one_ms` | 验证 `WAIT_TIME=0` 按最小 1 ms 处理，先进入 WAITING，1 ms 后才进入下一段。 | +| 4 | `act_zero_no_pulse` | 验证 `ACT_TIME=0` 的段不产生脉冲并在下一次 1 ms 调度跳过，后续段正常执行。 | +| 5 | `relative_absolute_zero` | 验证相对位移 0、相对位移 +5，以及当前位置等于绝对目标时的零位移完成。 | +| 6 | `self_jump_stop` | 验证单段自跳转可循环运行，并能由 STOP 正常终止。 | +| 7 | `stop_deceleration` | 验证 STOP 从 1000 Hz 按 1000 ms 减速至 100 Hz 后停止；重复 STOP 不重启减速，最终位置 902。 | +| 8 | `stop_pending_boundary` | 验证最后脉冲已完成但 Poll 尚未处理时收到 STOP，最终为 STOPPED 而非 COMPLETED。 | +| 9 | `direction_delay_one_ms` | 验证 1 ms 方向建立延时结束前不输出脉冲，满 1 ms 后启动。 | +| 10 | `ext_edge_at_natural_boundary` | 验证 EXT 边沿和自然末脉冲同时发生时只处理一次，不重复切段或计数。 | +| 11 | `ext_cut_natural_boundary_interleavings` | 覆盖 EXT 切断与自然边界的两种临界交错顺序，均正确进入后续 2000 Hz 段。 | +| 12 | `ext_edge_during_direction_delay` | 验证方向延时期间的 EXT 边沿不会在首脉冲前错误切段。 | +| 13 | `stopped_clears_pending_ext` | 验证 STOP 清除方向延时期间挂起的 EXT 边沿，重新 START 不消费旧边沿。 | +| 14 | `ext_edge_seamless_epoch` | 验证上一段的 EXT 竞态不会误切无缝衔接后的下一段。 | +| 15 | `ramp_seamless_epoch` | 验证上一段遗留的调速更新不会重定向无缝衔接后的下一段。 | +| 16 | `short_profile_boundary_matrix` | 覆盖直线、平滑、正弦三曲线与 1、2、10、99、100、101 脉冲，检查频率范围、升降趋势、对称性、计数和理论时长。 | +| 17 | `short_final_no_poll` | 验证三种曲线的 10 脉冲最终短段在脉冲间无 1 ms Poll 时仍逐脉冲减速并准确完成。 | +| 18 | `zero_to_maximum_ramp_duration` | 验证三种曲线从 0 加速到 100 kHz、1000 脉冲、20 ms 配置的单调性、峰值和总时长。 | +| 19 | `maximum_pulse_ramp_duration` | 验证三种曲线在 65,535 脉冲和 1311 ms 加速条件下采用可达峰值并准确计数。 | +| 20 | `maximum_single_ramp_no_poll` | 验证三种曲线的 65,535 脉冲单段在无 Poll 时持续逐脉冲更新并准确完成。 | +| 21 | `short_timer_failure` | 注入短段频率更新失败，验证立即关闭输出并进入 `ERROR/TIMER`，位置保留为 1。 | +| 22 | `stop_after_subsequent_handoff` | 验证无缝切入第二段后立即 STOP 能从新段频率正常减速并停止。 | +| 23 | `short_zero_speed_edges` | 验证起始/停止速度均为 0 时，1 脉冲和 2 脉冲短段仍以有效非零硬件频率准确执行。 | +| 24 | `short_dynamic_retarget` | 验证 50 脉冲短段中把目标频率由 1000 改为 2000 Hz 后安全上升，随后 STOP 正常停止。 | +| 25 | `short_ext_cut` | 验证短段执行 3 脉冲后触发 EXT，在下一脉冲边界切断，最终位置 4。 | +| 26 | `current_frequency_dynamic` | 验证当前段动态频率按安全脉冲边界生效，状态反映实际输出，运行中改脉冲数不改变启动快照。 | +| 27 | `poll_mailbox_failure` | 注入动态调频失败，验证 Poll 仅提交更新，失败在脉冲边界转为 `ERROR/TIMER`。 | +| 28 | `future_frequency_on_arrival` | 普通逐段模式中修改未来第二段频率，当前段不受影响，到达第二段时采用新值。 | +| 29 | `subsequent_future_frequency_handoff` | 无缝模式中修改未来段频率，验证预装衔接重建并以新频率无缝进入第二段。 | +| 30 | `future_frequency_last_pulse_race` | 验证未来段调频与当前段最后脉冲竞态时，第二段仍以新频率启动并准确完成。 | +| 31 | `latched_update_before_future_frequency_commit` | 验证屏蔽中断期间锁存的物理脉冲先消费旧衔接，再提交新的未来频率预装。 | +| 32 | `subsequent_no_poll_gap` | 验证两段只靠 ISR 无缝衔接，中间不依赖 Poll，输出不停止，最终位置 7。 | +| 33 | `three_single_pulse_no_poll` | 验证三个各 1 脉冲、1000/2000/3000 Hz 的段在无 Poll 时连续衔接。 | +| 34 | `handoff_queue_failures` | 两种时序下注入下一段频率排队失败，均关闭输出并转为 `ERROR/TIMER`。 | +| 35 | `command_state_restrictions` | 验证 IDLE/RUNNING 状态下 START、STOP、CLEAR、静态/动态配置写入及非法组合的限制。 | +| 36 | `command_mailbox_start_snapshot` | 验证 START 延迟执行与配置快照，后续写入和重复 START 不覆盖首个快照。 | +| 37 | `command_mailbox_stop_clear_deferred` | 验证重复 STOP/CLEAR 可幂等入队，状态变化延迟到 Poll，冲突命令返回 BUSY。 | +| 38 | `command_mailbox_validation` | 验证 START 入队前检查起始段和绝对位置有效性，非法配置不启动。 | +| 39 | `command_mailbox_start_failure` | 注入底层启动失败，验证 Poll 后进入 `ERROR/INVALID_RESOURCE`，CLEAR 可恢复。 | +| 40 | `wait_signal_positive` | 验证段后进入 WAITING，选定输入有效后由下一次 Poll 结束等待。 | +| 41 | `persistence_reinit` | 在 Host 存储模拟中验证输出、方向、2345 Hz 配置和位置 4 跨 `PlsrInit()` 恢复，CLEAR 后位置保持 0。 | +| 42 | `position_flash_save` | 验证位置稳定约 1000 ms 后仅保存一次，CLEAR 后延时产生第二次保存。 | +| 43 | `busy_reset_absolute_gate` | 模拟运动中复位，保留位置但取消绝对位置可信标志；CLEAR 后恢复绝对运动。 | +| 44 | `position_overflow` | 验证 `INT32_MAX` 正向溢出时立即停脉冲并进入 `ERROR/COUNT`。 | + +说明：Host 测试直接调用寄存器 API 和平台替身，不能代替真实 RTU 串口板测；真实 RTU 结果见第 7 节。 + +### 4.2 Python 产品测试脚本离线自检 + +执行命令： + +```powershell +py -B HostComputer\plsr_modbus_product_test.py --self-test +``` + +结果： + +```text +Self-test passed; no serial port was opened +``` + +覆盖： + +- Modbus CRC16 参考向量及线上低字节在前的字节序。 +- 6 组有符号 32 位数的双 WORD 拆分与合并。 +- 1200 Hz 请求的 1 Hz 容差边界。 +- ST-LINK GPIO 位读回文本解析。 + +### 4.3 Python 控制面板离线自检 + +执行命令： + +```powershell +py -B HostComputer\plsr_control_panel.py --self-test +``` + +结果： + +```text +PLSR control panel self-test passed; no GUI or serial port was opened +``` + +覆盖 9600 波特率、X4/X5 选项、10 段地址步进、整数解析和越界拒绝、公共区 20 WORD 编码、段区 8 WORD 编码、负脉冲补码及跳转段范围校验。 + +## 5. IAR 构建 + +执行命令： + +```powershell +& 'F:\IAR Systems\Embedded Workbench 8.3\common\bin\IarBuild.exe' ` + 'EWARM\Modbus.ewp' -build Modbus -log warnings +``` + +最终结果： + +```text +Total number of errors: 0 +Total number of warnings: 0 +``` + +`EWARM/Modbus/List/Modbus.map` 同时报告 `Errors: none`、`Warnings: none`，内存数据见第 3 节。 + +## 6. 烧录与固件产物校验 + +### 6.1 烧录 + +最终烧录使用 `EWARM/Modbus/Exe/Modbus.hex`，只擦除并写入应用占用的 Sector 0～3。ST-LINK 最终输出： + +```text +Verification...OK +``` + +开发过程中还用 STM32CubeProgrammer 执行过两次下载校验，用于确认当时固件可以下载和校验。它们属于中间版本的烧录链路记录，不是功能测试，也不作为最终交付固件的产物证据；最终结论以上述 ST-LINK 烧录、最终 SHA256 和后续完整板测为准。 + +### 6.2 持久化区保护 + +烧录前后均读取并检查 Sector 10/11。应用 HEX 地址上限为 `0x0800C550`，不覆盖持久化区；烧录流程也没有擦除 Sector 10/11。该检查用于确认后续持久化板测不是由重新烧录清空后伪造出的初始状态。 + +### 6.3 产物一致性 + +板测烧录件和当前分支重新构建产物的 SHA256 均为： + +```text +97956D9EF30A9B274140B9B82F412EDD77F9637F563FCC3F552BB4B140772343 +``` + +## 7. 真实 Modbus RTU 和运动板测 + +执行入口： + +```powershell +py -B HostComputer\plsr_modbus_product_test.py ` + --port COM5 --run --phase all --allow-motion +``` + +最终 `phase=all` 的 9 组测试全部 PASS： + +| # | 用例 | 实际验证内容 | 结果 | +|---:|---|---|---| +| 1 | `fixed_map_and_exceptions` | 真实 FC03/06/10 访问固定配置、段、状态和控制区；检查保留字读零、控制字读零；验证不支持 FC01 返回 0x01，非法/跨区/只读地址返回 0x02，保留字非零、半个 DWORD 和组合控制命令返回 0x03。 | PASS | +| 2 | `positive_negative_absolute_zero` | 验证正向相对、负向相对、绝对定位及零位移，检查方向、终态和逻辑位置。 | PASS | +| 3 | `all_outputs_100khz` | 同一个 PLSR 依次选择 Y0、Y1、Y2、Y3，每路请求 100 kHz、执行 1000 个逻辑脉冲并检查完成位置。不是四轴并发。 | PASS | +| 4 | `short_final_profiles` | 对直线、平滑、正弦三种曲线执行最终 10 脉冲短段，检查终态和准确位置。 | PASS | +| 5 | `wait_time` | 执行 10 脉冲后进入 WAITING，配置等待 120 ms；检查不会异常提前完成，之后正常完成。 | PASS | +| 6 | `act_time` | 2000 脉冲目标配合 80 ms ACT，检查时间到后在 0～2000 之间切断并正常完成。 | PASS | +| 7 | `dynamic_frequency_repeated_stop` | 当前段从 500 Hz 动态改为 1200 Hz；真实状态读回 1199 Hz，在允许的 1 Hz 容差内；运行中静态输出选择写入返回 BUSY；重复 STOP 正常减速停止且未跑满 3000 脉冲。 | PASS | +| 8 | `future_segment_frequency_on_arrival` | 普通逐段模式运行第一段时修改未来第二段频率，确认当前段仍为 400 Hz，进入第二段后采用 900 Hz。 | PASS | +| 9 | `subsequent_future_frequency_handoff` | SUBSEQUENT 模式运行第一段时修改未来段频率，确认当前段不变，第二段以 900 Hz 衔接并最终累计 400 脉冲。 | PASS | + +脚本在退出时停止仍在运行的任务，并恢复进入测试前保存的公共配置和前两段配置。 + +正式烧录后还在完整 `phase=all` 之前单独执行过一次 `--phase smoke`，固定映射和异常码检查 PASS。第 9 节恢复默认值并再次硬复位后又执行了一次 smoke，结果仍为 PASS。 + +## 8. X4/X5 实体回环板测 + +### 8.1 接线和方法 + +本轮保留的自动化回环接线： + +```text +Y4 -> X4 +Y5 -> X5 +``` + +脚本通过 ST-LINK 临时把 Y4/Y5 对应 GPIO 配置为输出，驱动 PLC 输入并直接读回 X4/X5 输入位；产品协议和正式固件没有为测试夹具新增私有寄存器。 + +开发期夹具最初尝试写 GPIO 的只写 BSRR 寄存器。旧版 `ST-LINK_CLI 3.5.0` 会在写后回读校验，因 BSRR 不可按普通寄存器回读而返回码 4。夹具随后改用 PI8/PE6 的 ODR 位带地址 `0x424402A0`、`0x42420298` 驱动输出。该失败是调试工具与只写寄存器的校验方式不兼容，不是接线、X4/X5 输入或 PLSR 功能故障。 + +执行入口： + +```powershell +py -B HostComputer\plsr_modbus_product_test.py ` + --port COM5 --run --phase x45 --allow-motion +``` + +### 8.2 九个用例 + +| # | 用例 | 实际验证内容 | 结果 | +|---:|---|---|---| +| 1 | `x45_electrical_scan` | Y4/Y5 均关闭时 X4/X5 均为低；分别打开 Y4、Y5 时对应输入为高、另一路保持低；关闭后恢复低，验证双路电气扫描和隔离。 | PASS | +| 2 | `X4_wait_signal` | 选择 X4；50 脉冲后进入 WAITING，X4 低时保持，Y4 拉有效后完成，位置仍为 50。 | PASS | +| 3 | `X4_ext_signal` | 选择 X4；5000 脉冲运动中由 Y4 触发 EXT_SIGNAL，提前切段并正常完成。 | PASS | +| 4 | `X4_ext_or_complete_natural` | 选择 X4；不触发输入，50 脉冲自然完成。 | PASS | +| 5 | `X4_ext_or_complete_trigger` | 选择 X4；5000 脉冲运动中由 Y4 外部触发，提前完成。 | PASS | +| 6 | `X5_wait_signal` | 选择 X5；50 脉冲后进入 WAITING，X5 低时保持，Y5 拉有效后完成，位置仍为 50。 | PASS | +| 7 | `X5_ext_signal` | 选择 X5；5000 脉冲运动中由 Y5 触发 EXT_SIGNAL，提前切段并正常完成。 | PASS | +| 8 | `X5_ext_or_complete_natural` | 选择 X5；不触发输入，50 脉冲自然完成。 | PASS | +| 9 | `X5_ext_or_complete_trigger` | 选择 X5；5000 脉冲运动中由 Y5 外部触发，提前完成。 | PASS | + +ODR 位带夹具修正后先完成独立电气扫描，再执行完整九项用例。异常清理顺序修正后又执行了第二次完整九项回归，结果仍全部 PASS。 + +### 8.3 最终夹具清理状态 + +测试结束或异常退出均按以下顺序清理：先关闭 Y4/Y5，再停止仍在运行的 PLSR，恢复测试前配置，最后把 PI8/PE6 恢复为输入高阻并清除上下拉。最终复核结果： + +- Y4/Y5 均关闭。 +- PI8/PE6 均为输入高阻、无内部上下拉。 +- X4/X5 读回均为低。 + +## 9. 持久化与硬复位板测 + +持久化测试使用真实目标板和 100 ms 硬复位，不以 Host 内存模拟代替。 + +### 9.1 保存准备 + +执行 `persistence-prepare`： + +- 清零逻辑位置。 +- 写入 500 Hz、7 脉冲的特征配置。 +- 执行运动并确认 COMPLETED、位置为 7。 +- 等待后台保存完成。 + +### 9.2 第一次硬复位和恢复检查 + +执行 100 ms 硬复位后运行 `persistence-verify --cleanup`，结果： + +- 上电状态为 IDLE，没有自动续跑复位前任务。 +- 逻辑位置恢复为 7。 +- 第一段频率恢复为 500 Hz。 +- 第一段脉冲数恢复为 7。 + +随后执行 CLEAR，把位置恢复为 0；写回默认配置并等待保存。 + +### 9.3 第二次硬复位和默认状态检查 + +再次执行 100 ms 硬复位后运行 `defaults-verify`，结果： + +- 状态为 IDLE，逻辑位置为 0。 +- 默认方向建立延时为 10 ms。 +- 默认速度为 1000 Hz，起始速度和停止速度均为 100 Hz。 +- 第 1 段为 1000 Hz、1000 脉冲。 +- 第 2～10 段频率均为 1000 Hz、脉冲数均为 0。 + +最后又执行一次固定映射 smoke，确认默认配置恢复后 RTU 访问和异常码仍通过。 + +## 10. 测试过程中出现的问题和修复回归 + +本节记录中间失败；这些结果不是最终失败，而是用于说明本轮调试实际发现并关闭了哪些问题。 + +| 阶段 | 中间现象 | 原因与处理 | 修复后结果 | +|---|---|---|---| +| 旧架构 PDU 试验 | `length == 8U`、`TestStatusAndControl() == 0` 失败 | 试验基于待废弃的旧 PDU 架构。需求复核后没有继续补旧架构，而是按 2026 固定产品接口重写；该试验路线整体废弃。 | 新固定接口由 Host `protocol_boundaries` 和真实 `fixed_map_and_exceptions` 覆盖并通过。 | +| 初期 Host | `12 tests / 262 assertions / 2 failures` | 失败项是 `wait_zero_rejected`、`act_zero_rejected`。复核明确需求后确认正确语义为 `WAIT=0` 按 1 ms，`ACT=0` 零脉冲跳段，代码和测试按正确语义修正。 | `wait_zero_one_ms`、`act_zero_no_pulse` 通过；最终 44/1,694,007/0。 | +| 扩充 EXT 测试 | Host 编译失败，`PLSR_EXT_SIGNAL` 未声明 | 测试扩充时枚举和测试引用未同步，补齐枚举/接口后重跑。 | Host 编译和完整回归通过。 | +| Modbus 裁剪中间态 | IAR `10 errors / 2 warnings` | 头文件先精简，旧源文件与 `main.c` 尚未同步清理；不是运动算法失败。随后完成最小 RTU 源文件和入口同步。 | IAR 全量构建 `0 errors / 0 warnings`。 | +| Host 脚本启动 | Windows 默认策略阻止直接运行 `.ps1` | 改用 `powershell.exe -NoProfile -ExecutionPolicy Bypass -File ...`。 | Host 脚本正常执行并通过。 | +| X4/X5 夹具初版 | `ST-LINK_CLI 3.5.0` 写 BSRR 返回码 4 | BSRR 是只写寄存器，旧 CLI 的写后回读校验不适用。改用 PI8/PE6 的 ODR 位带地址驱动 Y4/Y5。 | 独立电气扫描和完整 X4/X5 九项通过；判定为夹具工具限制，不计为产品失败。 | +| X4/X5 夹具审查 | 异常退出清理顺序不够安全 | 调整为先关闭 Y4/Y5，再停止运动、恢复配置，最后释放 GPIO；保证清理期间不会继续保持输入触发。 | 完整 X4/X5 九项重新执行并通过，最终 GPIO/输入状态复核通过。 | + +中间失败均保留在本报告中，但最终交付结论以当前基线重新执行的结果为准。 + +## 11. 明确未执行和结论边界 + +以下项目本轮**未执行**，不得从本报告的 PASS 推导为已验证： + +- 未使用逻辑分析仪，因此没有验证端子真实占空比、每路真实边沿数、毛刺、窄脉冲、方向建立时间或段间物理波形连续性。 +- 未对 MCU 中断最坏响应时间和 100 kHz 下的 ISR 最坏时延做仪器测量。 +- 未做四轴同时运动或四轴联动；本实现只有一个逻辑 PLSR，Y0～Y3 是逐路选择。 +- 未做 USB CDC 与 Modbus/运动并发长稳。 +- 未做本次最小重写的长时间压力、断线重连或坏 CRC 长稳矩阵。 +- 未做真实 VBAT 断主电源测试。本轮实际执行的是调试器控制的 100 ms 硬复位；它能证明复位恢复路径，不能等价证明 VBAT/完全掉电保持。 +- Host 的持久化用例使用内存模拟；真实 Flash/复位结论仅来自第 9 节板测。 +- Host 直接调用寄存器 API，不证明 RTU 物理链路；真实 RTU 覆盖仅限第 7～9 节列出的板测。 +- 未用 IAR 8.40 构建；本轮实际验证版本为 IAR EWARM 8.3.4。 + +## 12. 最终状态 + +测试结束后目标板处于以下状态： + +- 固件为 SHA256 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起始执行段数：脉冲指令从“起始执行段数”开始执行； +* 等待条件 + - 当前段脉冲发送完成后，进入等待，“等待条件”满足后，跳转至指定段； + - 等待条件包括：Wait时间、Wait信号（X点）、ACT时间、EXT信号（X点）、EXT信号或脉冲发送完成； + * 单段脉冲参数配置： + * 脉冲频率，范围：1HZ~100KHZ，脉冲频率在脉冲指令执行过程中修改后立即生效； + * 脉冲个数，范围：-2147483648~2147483647，设置负数表示反向发脉冲； + * 跳转段数，如果设置为0，表示默认跳转至下一段脉冲，最后一段脉冲的跳转段数设置为0，表示结束脉冲输出功能； +* 断电保存数据： + * 系统参数数据、记录数据可掉电保持； + * 上电后自动加载保存数据，并进行参数配置; +* 配置参数； + + * 脉冲方向端子可选择； + * 脉冲输出端子可选择； + * 脉冲总段数可设置； + * 起始执行段数可设置； + * 运行模式可设置； + * 加减速模式可设置； + * 等待条件可设置； + * 加速时间、减速时间可设置； + * 第n段的脉冲频率、脉冲个数、跳转段数可设置（n:1~10）; +* PLSR指令功能自测； + +### 4、通信任务要求 + +- 使用一种通信方式(modbus)监控和实时修改PLSR的参数; +- 自制触摸屏或者上位机界面，实现PLSR题目涉及的参数读、写功能。（二选一，需要触摸屏可申领） + +### 5、可选要求 + +* 实现PLSR输出AB相脉冲，可控制输出方向； +* 支持对输出的脉冲信号进行诊断： + - 诊断输出脉冲的个数是否与设置一致； + - 诊断输出脉冲的频率、加减速曲线是否与设置一致； + +## 二、时间要求 + +1个月（4周） + +## 三、任务器材和软件工具 + +| 序号 | 器材 | 数量 | +| ---- | ---------------------------------------- | ---- | +| 1 | XDM-60T4-E/XDM-60T10-E | 1台 | +| 2 | ST-LINK | 1台 | +| 3 | 电源线 | 1根 | +| 4 | XVP线 | 1根 | +| 5 | USB转串 | 1个 | +| 6 | DB9F侧线 | 1根 | +| 7 | 编码器线CP-SP-M-03 | 1根 | +| 8 | 动力线CM-P15-01 | 1根 | +| 9 | 开关电源 | 1个 | +| 10 | 驱动器DF3E-0410 | 1个 | +| 11 | 电机MF3S-60CS30B1-504 | 1个 | +| | **6~11是伺服相关的设备，一组有一套即可** | | + +| 软件工具 | 版本 | +| -------- | ---- | +| | | +| | | +| IAR8.40 | 8.40 | + + + +## 四、XDM-60T4-E硬件信息 + +- 芯片型号： STM32F407IG ，晶振12MHz。 +- 引脚信息 + +| 芯片引脚 | 实际作用 | +| --------- | -------- | +| I0 | PH10 | +| I1 | PH11 | +| I2 | PG8 | +| I3 | PB4 | +| I4 | PB5 | +| I5 | PG12 | +| I6 | PB6 | +| I7 | PB7 | +| I10 | PF10 | +| I11 | PA15 | +| I12 | PB3 | +| I13 | PA14 | +| I14 | PI4 | +| I15 | PI5 | +| I16 | PI6 | +| I17 | PI7 | +| I20 | PE2 | +| Q0 | PF6 | +| Q1 | PF8 | +| Q2 | PF7 | +| Q3 | PF9 | +| Q4 | PI8 | +| Q5 | PE6 | +| Q6 | PE5 | +| Q7 | PE4 | +| Q10 | PG7 | +| Q11 | PG6 | +| Q12 | PH9 | +| Q13 | PH8 | +| Q14 | PH7 | +| Q15 | PH6 | +| Q16 | PF11 | +| Q17 | PB0 | +| Q20 | PH5 | +| USART1_TX | PA9 | +| USART1_RX | PA10 | + +## 五、XDM-60T10-E硬件信息 + +- 芯片型号：STM32F407ZG，晶振12MHz。 +- 引脚信息 + +| 芯片引脚 | 实际作用 | +| --------- | -------- | +| I0 | PA0 | +| I1 | PA1 | +| I2 | PG8 | +| I3 | PB4 | +| I4 | PB5 | +| I5 | PG12 | +| I6 | PB6 | +| I7 | PB7 | +| I10 | PF10 | +| I11 | PA15 | +| I12 | PB3 | +| I13 | PA14 | +| Q0 | PF6 | +| Q1 | PF8 | +| Q2 | PF7 | +| Q3 | PF9 | +| USART1_TX | PA9 | +| USART1_RX | PA10 | + +## 六、Modbus 参数地址表 + +本节整理自《参数表-2026.xlsx》。表内地址为 Modbus 寄存器地址；所有双字参数均占用两个连续的 +16 位寄存器，并按“低地址存低 16 位、高地址存高 16 位”的顺序保存。 + +### 1、公共配置参数 + +| Modbus 地址 | 参数 | 取值及说明 | +| --- | --- | --- | +| `0x1000` | 脉冲发送端子 | `0`：Y0；`1`：Y1；`2`：Y2；`3`：Y3 | +| `0x1001` | 脉冲方向端子 | `0`：Y12；`1`：Y13；`2`：Y14；`3`：Y15 | +| `0x1002` | WAIT 信号 | `0`：X4；`1`：X5 | +| `0x1003` | EXT 信号 | `0`：X4；`1`：X5 | +| `0x1004` | 脉冲发送模式 | `0`：完成模式；`1`：后续模式 | +| `0x1005` | 脉冲方向延时时间 | 单位：ms | +| `0x1006` | 脉冲方向逻辑 | `0`：正逻辑；`1`：负逻辑 | +| `0x1007` | 脉冲加减速模式 | `0`：直线；`1`：S 曲线；`2`：正弦曲线 | +| `0x1008` | 运行模式 | `0`：相对模式；`1`：绝对模式 | +| `0x1009` | 脉冲总段数 | 范围：1～10 | +| `0x100A` | 起始执行段数 | 指令从指定段开始执行 | +| `0x100B～0x100C` | 脉冲默认速度 | 32 位，单位：Hz | +| `0x100D～0x100E` | 脉冲起始速度 | 32 位，单位：Hz | +| `0x1010～0x1011` | 脉冲终止速度 | 32 位，单位：Hz | +| `0x1012` | 默认速度加速时间 | 单位：ms | +| `0x1013` | 默认速度减速时间 | 单位：ms | + +### 2、单段参数布局 + +每段占用一个 `0x10` 寄存器跨度。第 `n` 段的基地址为： + +```text +segment_base = 0x1100 + (n - 1) × 0x10，n = 1～10 +``` + +| 相对偏移 | 参数 | 取值及说明 | +| --- | --- | --- | +| `+0～+1` | 第 n 段脉冲频率 | 32 位，单位：Hz，范围：1 Hz～100 kHz | +| `+2～+3` | 第 n 段脉冲个数 | 32 位有符号数；负数表示反向 | +| `+4` | 第 n 段等待条件 | `0`：WAIT 时间；`1`：WAIT 信号；`2`：ACT 时间；`3`：EXT 信号；`4`：EXT 信号或脉冲发送完成 | +| `+5` | WAIT 时间 | 单位：ms | +| `+6` | ACT 时间 | 单位：ms | +| `+7` | 第 n 段跳转编号 | `0` 表示默认跳转至下一段；最后一段为 `0` 时结束输出 | + +各段具体地址如下： + +| 段号 | 脉冲频率 | 脉冲个数 | 等待条件 | WAIT 时间 | ACT 时间 | 跳转编号 | +| ---: | --- | --- | --- | --- | --- | --- | +| 1 | `0x1100～0x1101` | `0x1102～0x1103` | `0x1104` | `0x1105` | `0x1106` | `0x1107` | +| 2 | `0x1110～0x1111` | `0x1112～0x1113` | `0x1114` | `0x1115` | `0x1116` | `0x1117` | +| 3 | `0x1120～0x1121` | `0x1122～0x1123` | `0x1124` | `0x1125` | `0x1126` | `0x1127` | +| 4 | `0x1130～0x1131` | `0x1132～0x1133` | `0x1134` | `0x1135` | `0x1136` | `0x1137` | +| 5 | `0x1140～0x1141` | `0x1142～0x1143` | `0x1144` | `0x1145` | `0x1146` | `0x1147` | +| 6 | `0x1150～0x1151` | `0x1152～0x1153` | `0x1154` | `0x1155` | `0x1156` | `0x1157` | +| 7 | `0x1160～0x1161` | `0x1162～0x1163` | `0x1164` | `0x1165` | `0x1166` | `0x1167` | +| 8 | `0x1170～0x1171` | `0x1172～0x1173` | `0x1174` | `0x1175` | `0x1176` | `0x1177` | +| 9 | `0x1180～0x1181` | `0x1182～0x1183` | `0x1184` | `0x1185` | `0x1186` | `0x1187` | +| 10 | `0x1190～0x1191` | `0x1192～0x1193` | `0x1194` | `0x1195` | `0x1196` | `0x1197` | + +### 3、运行监控 + +| Modbus 地址 | 参数 | 说明 | +| --- | --- | --- | +| `0x2000～0x2001` | 脉冲累计数量监控 | 32 位有符号数，可读取负数 | +| `0x2002～0x2003` | 当前脉冲发送频率 | 32 位 | +| `0x2004` | 运行状态 | 状态编码由实现定义并在通信协议中说明 | +| `0x2005` | 当前执行段 | 当前正在执行的段号 | +| `0x2006` | 错误码 | 错误码定义由实现说明 | + +### 4、控制寄存器 + +| Modbus 地址 | 位 | 功能 | +| --- | ---: | --- | +| `0x3000` | bit0 | 启动脉冲输出 | +| `0x3000` | bit1 | 停止脉冲输出（可参考） | +| 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enumerate(re.findall( + r"[0-9a-f]{8}", match.group(2), flags=re.IGNORECASE)): + observed[line_address + offset * 4] = int(value, 16) + words = [] + for offset in range(count): + word_address = address + offset * 4 + require(word_address in observed, + "ST-LINK output did not contain address 0x%08X" + % word_address) + words.append(observed[word_address]) + return words class X45Fixture: @@ -138,6 +208,22 @@ class X45Fixture: ) return result.stdout + def read_words(self, address, count): + require(count > 0, "ST-LINK read count must be positive") + output = self._run("-r32", hex(address), str(count * 4)) + return parse_stlink_words(output, address, count) + + def write_words(self, address, values): + require(values, "ST-LINK write values must not be empty") + arguments = [] + for offset, value in enumerate(values): + arguments.extend(( + "-w32", + hex(address + offset * 4), + hex(value & 0xFFFFFFFF), + )) + self._run(*arguments) + def prepare(self): self._run( "-w32", hex(GPIOE_CLOCK_BIT), "1", @@ -244,6 +330,137 @@ class Status: error: int +@dataclasses.dataclass +class Diagnostic: + flags: int + reason: int + segment: int + output_mode: int + direction_positive: bool + expected_pulses: int + actual_pulses: int + count_error: int + requested_hz: int + expected_timer_hz: int + active_timer_hz: int + request_error_hz: int + sample_count: int + mismatch_count: int + maximum_frequency_error_hz: int + first_mismatch_sample: int + + +@dataclasses.dataclass +class PersistenceLiveStats: + attempts: int + successful: int + timeouts: int + maximum_attempt_seconds: float + elapsed_seconds: float + + +@dataclasses.dataclass(frozen=True) +class IrqCycleStats: + count: tuple + last_cycles: tuple + maximum_cycles: tuple + + +@dataclasses.dataclass(frozen=True) +class ProducerCycleStats: + item_count: int + total_cycles: int + maximum_item_cycles: int + + @property + def average_cycles(self): + require(self.item_count > 0, + "producer timing did not record any generated item") + return self.total_cycles / float(self.item_count) + + +@dataclasses.dataclass(frozen=True) +class FinalArmCycleStats: + queue_count: tuple + job_last_cycles: tuple + job_maximum_cycles: tuple + queue_to_stop_last_cycles: tuple + queue_to_stop_maximum_cycles: tuple + + +class TimingFixture: + IRQ_SYMBOLS = ( + "PlsrIrqCount", + "PlsrIrqLastCycles", + "PlsrIrqMaxCycles", + ) + PRODUCER_SYMBOLS = ( + "PlsrProfileProducerItemCount", + "PlsrProfileProducerTotalCycles", + "PlsrProfileProducerMaxItemCycles", + ) + FINAL_ARM_SYMBOLS = ( + "PlsrFinalArmQueueCount", + "PlsrFinalArmJobLastCycles", + "PlsrFinalArmJobMaxCycles", + "PlsrFinalArmQueueToStopLastCycles", + "PlsrFinalArmQueueToStopMaxCycles", + ) + + def __init__(self, probe, map_path): + self.probe = probe + try: + map_text = Path(map_path).read_text( + encoding="utf-8", errors="replace") + except OSError as error: + raise TestFailure("could not read IAR map %s: %s" + % (map_path, error)) from error + self.addresses = { + symbol: parse_iar_map_symbol_address(map_text, symbol) + for symbol in (self.IRQ_SYMBOLS + self.PRODUCER_SYMBOLS + + self.FINAL_ARM_SYMBOLS) + } + + def reset(self): + for symbol in self.IRQ_SYMBOLS: + self.probe.write_words(self.addresses[symbol], [0] * 4) + for symbol in self.PRODUCER_SYMBOLS: + self.probe.write_words(self.addresses[symbol], [0]) + for symbol in self.FINAL_ARM_SYMBOLS: + self.probe.write_words(self.addresses[symbol], [0] * 4) + + def read(self): + irq = IrqCycleStats( + count=tuple(self.probe.read_words( + self.addresses["PlsrIrqCount"], 4)), + last_cycles=tuple(self.probe.read_words( + self.addresses["PlsrIrqLastCycles"], 4)), + maximum_cycles=tuple(self.probe.read_words( + self.addresses["PlsrIrqMaxCycles"], 4)), + ) + producer = ProducerCycleStats( + item_count=self.probe.read_words( + self.addresses["PlsrProfileProducerItemCount"], 1)[0], + total_cycles=self.probe.read_words( + self.addresses["PlsrProfileProducerTotalCycles"], 1)[0], + maximum_item_cycles=self.probe.read_words( + self.addresses["PlsrProfileProducerMaxItemCycles"], 1)[0], + ) + final_arm = FinalArmCycleStats( + queue_count=tuple(self.probe.read_words( + self.addresses["PlsrFinalArmQueueCount"], 4)), + job_last_cycles=tuple(self.probe.read_words( + self.addresses["PlsrFinalArmJobLastCycles"], 4)), + job_maximum_cycles=tuple(self.probe.read_words( + self.addresses["PlsrFinalArmJobMaxCycles"], 4)), + queue_to_stop_last_cycles=tuple(self.probe.read_words( + self.addresses["PlsrFinalArmQueueToStopLastCycles"], 4)), + queue_to_stop_maximum_cycles=tuple(self.probe.read_words( + self.addresses["PlsrFinalArmQueueToStopMaxCycles"], 4)), + ) + return irq, producer, final_arm + + class RtuClient: def __init__(self, port, baud, slave, timeout): self.port_name = port @@ -306,11 +523,30 @@ class RtuClient: if not waiting: time.sleep(0.0005) + waiting = self.serial_port.in_waiting + if waiting: + response.extend(self.serial_port.read(waiting)) + if len(response) >= 2 and response[1] == (pdu[0] | 0x80): + expected_length = 5 + elif pdu[0] == 0x03 and len(response) >= 3: + expected_length = response[2] + 5 + elif pdu[0] in (0x06, 0x10): + expected_length = 8 + self.last_request_finished = time.monotonic() - require(response, "no Modbus response to %s" % request.hex(" ")) - require(expected_length is not None, "response header is incomplete") + if not response: + raise RtuTimeout("no Modbus response to %s" % request.hex(" ")) + if expected_length is None: + raise RtuTimeout( + "Modbus response header timed out: %s" % response.hex(" ") + ) + if len(response) < expected_length: + raise RtuTimeout( + "Modbus response timed out after %d/%d bytes: %s" + % (len(response), expected_length, response.hex(" ")) + ) require(len(response) == expected_length, - "incomplete or oversized Modbus response: %s" % response.hex(" ")) + "oversized Modbus response: %s" % response.hex(" ")) require(len(response) >= 5, "short Modbus response: %s" % response.hex(" ")) received_crc = response[-2] | (response[-1] << 8) require( @@ -402,6 +638,93 @@ def read_status(client): ) +def parse_diagnostic(words): + require(len(words) == DIAGNOSTIC_WORDS, + "diagnostic register count must be %d" % DIAGNOSTIC_WORDS) + mode_direction = words[3] + return Diagnostic( + flags=words[0], + reason=words[1], + segment=words[2], + output_mode=mode_direction & 0xFF, + direction_positive=bool(mode_direction & 0x0100), + expected_pulses=join_u32(words[4], words[5]), + actual_pulses=join_u32(words[6], words[7]), + count_error=join_i32(words[8], words[9]), + requested_hz=join_u32(words[10], words[11]), + expected_timer_hz=join_u32(words[12], words[13]), + active_timer_hz=join_u32(words[14], words[15]), + request_error_hz=join_i32(words[16], words[17]), + sample_count=join_u32(words[18], words[19]), + mismatch_count=join_u32(words[20], words[21]), + maximum_frequency_error_hz=join_u32(words[22], words[23]), + first_mismatch_sample=join_u32(words[24], words[25]), + ) + + +def read_diagnostic(client): + return parse_diagnostic( + client.read_holding(DIAGNOSTIC_BASE, DIAGNOSTIC_WORDS) + ) + + +def clear_diagnostic(client): + client.write_single(DIAGNOSTIC_CONTROL, DIAGNOSTIC_CLEAR) + diagnostic = read_diagnostic(client) + require(diagnostic.flags == 0, "diagnostic CLEAR did not clear flags") + require(diagnostic.reason == 0, "diagnostic CLEAR did not clear reason") + require(diagnostic.first_mismatch_sample == 0xFFFFFFFF, + "diagnostic CLEAR first mismatch sentinel is invalid") + + +def require_diagnostic_pass(diagnostic, expected_pulses, expected_mode, + direction_positive, label, expected_segment=1): + require((diagnostic.flags & DIAG_COMPLETE_PASS) == DIAG_COMPLETE_PASS, + "%s diagnostic checks incomplete or failed: flags=0x%04X" + % (label, diagnostic.flags)) + require(not (diagnostic.flags & DIAG_MONITORING), + "%s diagnostic remained active" % label) + require(not (diagnostic.flags & DIAG_FAULT_LATCHED), + "%s diagnostic latched fault %d" % (label, diagnostic.reason)) + require(diagnostic.reason == 0, "%s diagnostic reason is %d" + % (label, diagnostic.reason)) + require(diagnostic.segment == expected_segment, + "%s diagnostic segment expected %d, got %d" + % (label, expected_segment, diagnostic.segment)) + require(diagnostic.output_mode == expected_mode, + "%s diagnostic output mode expected %d, got %d" + % (label, expected_mode, diagnostic.output_mode)) + require(diagnostic.direction_positive == direction_positive, + "%s diagnostic direction mismatch" % label) + require(diagnostic.expected_pulses == expected_pulses, + "%s diagnostic expected pulse count %d, got %d" + % (label, expected_pulses, diagnostic.expected_pulses)) + require(diagnostic.actual_pulses == expected_pulses, + "%s diagnostic actual pulse count %d, got %d" + % (label, expected_pulses, diagnostic.actual_pulses)) + require(diagnostic.count_error == 0, + "%s diagnostic count error %d" % (label, diagnostic.count_error)) + require(diagnostic.requested_hz > 0, + "%s diagnostic requested frequency is zero" % label) + require(diagnostic.expected_timer_hz > 0, + "%s diagnostic expected timer frequency is zero" % label) + require(diagnostic.active_timer_hz == diagnostic.expected_timer_hz, + "%s diagnostic active/expected frequency %d/%d" + % (label, diagnostic.active_timer_hz, + diagnostic.expected_timer_hz)) + require(diagnostic.sample_count > 0, + "%s diagnostic did not capture curve samples" % label) + require(diagnostic.mismatch_count == 0, + "%s diagnostic curve mismatch count %d" + % (label, diagnostic.mismatch_count)) + require(diagnostic.maximum_frequency_error_hz == 0, + "%s diagnostic maximum active frequency error %d Hz" + % (label, diagnostic.maximum_frequency_error_hz)) + require(diagnostic.first_mismatch_sample == 0xFFFFFFFF, + "%s diagnostic first mismatch sample is %d" + % (label, diagnostic.first_mismatch_sample)) + + def wait_for_status(client, predicate, timeout, description): deadline = time.monotonic() + timeout last_status = None @@ -441,6 +764,14 @@ def expect_exception(operation, expected_code, label): raise TestFailure("%s did not return a Modbus exception" % label) +def expect_test_failure(operation, label): + try: + operation() + except TestFailure: + return + raise TestFailure("%s unexpectedly passed" % label) + + def make_common( position_mode=0, segment_count=1, @@ -496,7 +827,24 @@ def configure(client, common, segment_1, segment_2=None): client.write_multiple(SEGMENT_2_BASE, segment_2) +def configure_segments(client, common, segments): + require(1 <= len(segments) <= 10, + "segment configuration count must be 1..10") + client.write_multiple(CONFIG_BASE, common) + for index, segment in enumerate(segments): + client.write_multiple(SEGMENT_1_BASE + index * 0x10, segment) + + +def configure_pulse_dir(client, common, segment_1, segment_2=None): + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) + require(client.read_holding(OUTPUT_MODE, 1) == [OUTPUT_PULSE_DIR], + "PULSE/DIR output mode readback failed") + configure(client, common, segment_1, segment_2) + clear_diagnostic(client) + + def restore_default_configuration(client): + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) common = make_common( default_hz=1000, start_hz=100, @@ -535,10 +883,19 @@ def test_fixed_map_and_exceptions(client): segment = client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS) status = read_status(client) control = client.read_holding(CONTROL, 1) + output_mode = client.read_holding(OUTPUT_MODE, 1) + diagnostic = read_diagnostic(client) + diagnostic_control = client.read_holding(DIAGNOSTIC_CONTROL, 1) require(len(common) == COMMON_WORDS, "common map read failed") require(len(segment) == SEGMENT_WORDS, "segment map read failed") require(0 <= status.state <= STATUS_ERROR, "status enum is out of range") require(control == [0], "control register must read as zero") + require(output_mode[0] in (OUTPUT_PULSE_DIR, OUTPUT_AB), + "output mode is out of range") + require(diagnostic.output_mode in (OUTPUT_PULSE_DIR, OUTPUT_AB), + "diagnostic output mode is out of range") + require(diagnostic_control == [0], + "diagnostic control register must read as zero") require(client.read_holding(0x100F, 1) == [0], "reserved word is not zero") require(client.read_holding(0x1108, 1) == [0], "segment padding is not zero") @@ -577,25 +934,64 @@ def test_fixed_map_and_exceptions(client): EX_ILLEGAL_VALUE, "combined control command", ) + expect_exception( + lambda: client.read_holding(0x11FF, 2), + EX_ILLEGAL_ADDRESS, + "range crossing into output mode", + ) + expect_exception( + lambda: client.read_holding(0x2119, 2), + EX_ILLEGAL_ADDRESS, + "range crossing diagnostic end", + ) + expect_exception( + lambda: client.write_single(DIAGNOSTIC_BASE, 0), + EX_ILLEGAL_ADDRESS, + "diagnostic write", + ) + expect_exception( + lambda: client.write_single(DIAGNOSTIC_CONTROL, 2), + EX_ILLEGAL_VALUE, + "invalid diagnostic command", + ) + expect_exception( + lambda: client.write_single(OUTPUT_MODE, 2), + EX_ILLEGAL_VALUE, + "invalid output mode", + ) def test_positive_negative_and_absolute_zero(client): clear_position(client) common = make_common(position_mode=0, start_hz=500) - configure(client, common, make_segment(500, 25)) + configure_pulse_dir(client, common, make_segment(500, 25)) command(client, COMMAND_START) status = wait_terminal(client, 3.0) require(status.state == STATUS_COMPLETED, "positive move did not complete") require(status.position == 25, "positive accumulation expected 25") + require_diagnostic_pass( + read_diagnostic(client), + 25, + OUTPUT_PULSE_DIR, + True, + "positive move", + ) - configure(client, common, make_segment(500, -10)) + configure_pulse_dir(client, common, make_segment(500, -10)) command(client, COMMAND_START) status = wait_terminal(client, 3.0) require(status.state == STATUS_COMPLETED, "negative move did not complete") require(status.position == 15, "negative accumulation expected 15") + require_diagnostic_pass( + read_diagnostic(client), + 10, + OUTPUT_PULSE_DIR, + False, + "negative move", + ) absolute = make_common(position_mode=1, start_hz=500) - configure(client, absolute, make_segment(500, 15)) + configure_pulse_dir(client, absolute, make_segment(500, 15)) before = read_status(client) command(client, COMMAND_START) status = wait_terminal(client, 1.0) @@ -603,6 +999,160 @@ def test_positive_negative_and_absolute_zero(client): require(status.position == before.position, "absolute zero changed position") +def test_ten_segments_in_sequence(client): + clear_position(client) + common = make_common( + segment_count=10, + default_hz=1000, + start_hz=1000, + stop_hz=1000, + ) + pulse_counts = [100 + index for index in range(10)] + segments = [make_segment(1000, pulses) for pulses in pulse_counts] + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) + configure_segments(client, common, segments) + clear_diagnostic(client) + require(client.read_holding(CONFIG_BASE + 0x09, 2) == [10, 1], + "ten-segment count/start readback mismatch") + + command(client, COMMAND_START) + for segment_number in range(1, 11): + wait_for_status( + client, + lambda item, expected=segment_number: + item.segment == expected and item.state in ACTIVE_STATES, + 2.0, + "sequential segment %d" % segment_number, + ) + + status = wait_terminal(client, 3.0) + expected_position = sum(pulse_counts) + require(status.state == STATUS_COMPLETED, + "ten-segment sequence did not complete") + require(status.position == expected_position, + "ten-segment sequence position expected %d, got %d" + % (expected_position, status.position)) + require_diagnostic_pass( + read_diagnostic(client), + pulse_counts[-1], + OUTPUT_PULSE_DIR, + True, + "ten-segment sequence final segment", + expected_segment=10, + ) + + +def test_start_segment_ten(client): + clear_position(client) + common = make_common( + segment_count=10, + start_segment=10, + default_hz=1000, + start_hz=1000, + stop_hz=1000, + ) + segment_ten_pulses = 200 + segments = [make_segment(1000, 11 + index) for index in range(9)] + segments.append(make_segment(1000, segment_ten_pulses)) + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) + configure_segments(client, common, segments) + clear_diagnostic(client) + require(client.read_holding(CONFIG_BASE + 0x09, 2) == [10, 10], + "startSegment=10 readback mismatch") + + command(client, COMMAND_START) + wait_for_status( + client, + lambda item: item.segment == 10 and item.state in ACTIVE_STATES, + 2.0, + "startSegment=10 active segment", + ) + status = wait_terminal(client, 3.0) + require(status.state == STATUS_COMPLETED, + "startSegment=10 move did not complete") + require(status.position == segment_ten_pulses, + "startSegment=10 executed an earlier segment: position=%d" + % status.position) + require_diagnostic_pass( + read_diagnostic(client), + segment_ten_pulses, + OUTPUT_PULSE_DIR, + True, + "startSegment=10", + expected_segment=10, + ) + + +def test_direction_output_and_polarity_matrix(client): + pulse_count = 25 + direction_delay_ms = 500 + + for direction_output in range(4): + for negative_logic in range(2): + for direction in (1, -1): + label = "Y%d DIR %s %s logic" % ( + direction_output + 12, + "positive" if direction > 0 else "negative", + "negative" if negative_logic else "positive", + ) + clear_position(client) + common = make_common( + default_hz=500, + start_hz=500, + stop_hz=500, + ) + common[0x01] = direction_output + common[0x05] = direction_delay_ms + common[0x06] = negative_logic + target = direction * pulse_count + segment = make_segment(500, target) + configure_pulse_dir(client, common, segment) + + common_readback = client.read_holding(CONFIG_BASE, COMMON_WORDS) + segment_readback = client.read_holding( + SEGMENT_1_BASE, SEGMENT_WORDS) + require(common_readback[0x01] == direction_output, + "%s direction output readback mismatch" % label) + require(common_readback[0x05] == direction_delay_ms, + "%s direction delay readback mismatch" % label) + require(common_readback[0x06] == negative_logic, + "%s direction polarity readback mismatch" % label) + require(join_i32(segment_readback[2], segment_readback[3]) + == target, + "%s signed target readback mismatch" % label) + + command(client, COMMAND_START) + before_pulses = wait_for_status( + client, + lambda item: item.state == STATUS_ACCELERATING + and item.segment == 1, + 0.25, + "%s direction-delay state" % label, + ) + require(before_pulses.segment == 1, + "%s direction delay selected wrong segment" % label) + require(before_pulses.position == 0, + "%s counted a logical pulse during direction delay" + % label) + require(before_pulses.frequency_hz == 0, + "%s reported a pulse frequency during direction delay" + % label) + + status = wait_terminal(client, 3.0) + require(status.state == STATUS_COMPLETED, + "%s did not complete" % label) + require(status.position == target, + "%s position expected %d, got %d" + % (label, target, status.position)) + require_diagnostic_pass( + read_diagnostic(client), + pulse_count, + OUTPUT_PULSE_DIR, + direction > 0, + label, + ) + + def test_all_outputs_at_100khz(client): for output in range(4): clear_position(client) @@ -613,7 +1163,7 @@ def test_all_outputs_at_100khz(client): ) common[0x00] = output common[0x01] = output - configure(client, common, make_segment(100000, 1000)) + configure_pulse_dir(client, common, make_segment(100000, 1000)) command(client, COMMAND_START) status = wait_terminal(client, 2.0) require(status.state == STATUS_COMPLETED, @@ -621,6 +1171,13 @@ def test_all_outputs_at_100khz(client): require(status.position == 1000, "output %d count expected 1000, got %d" % (output, status.position)) + require_diagnostic_pass( + read_diagnostic(client), + 1000, + OUTPUT_PULSE_DIR, + True, + "output %d 100 kHz" % output, + ) def test_short_final_profiles(client): @@ -633,7 +1190,7 @@ def test_short_final_profiles(client): stop_hz=100, deceleration_ms=1000, ) - configure(client, common, make_segment(100000, 10)) + configure_pulse_dir(client, common, make_segment(100000, 10)) command(client, COMMAND_START) status = wait_terminal(client, 2.0) require(status.state == STATUS_COMPLETED, @@ -644,11 +1201,234 @@ def test_short_final_profiles(client): require(status.position == 10, "short curve %d count expected 10, got %d" % (curve_mode, status.position)) + require_diagnostic_pass( + read_diagnostic(client), + 10, + OUTPUT_PULSE_DIR, + True, + "short curve %d" % curve_mode, + ) + + +def test_long_millisecond_ramp(client): + pulses = 65535 + label = "65,535-pulse 1 ms ramp" + clear_position(client) + common = make_common( + curve_mode=2, + default_hz=100000, + start_hz=1000, + stop_hz=1000, + acceleration_ms=100, + deceleration_ms=100, + ) + configure_pulse_dir(client, common, make_segment(100000, pulses)) + command(client, COMMAND_START) + status = wait_terminal(client, 5.0) + require(status.state == STATUS_COMPLETED, + "%s did not complete" % label) + require(status.position == pulses, + "%s expected %d pulses, got %d" + % (label, pulses, status.position)) + diagnostic = read_diagnostic(client) + require(frequency_matches(diagnostic.requested_hz, 1000), + "%s final requested frequency expected 1000 Hz, got %d Hz" + % (label, diagnostic.requested_hz)) + require_diagnostic_pass( + diagnostic, + pulses, + OUTPUT_PULSE_DIR, + True, + label, + ) + + +def require_irq_cycle_budget(stats, expected_outputs, label): + for output in expected_outputs: + require(stats.count[output] > 0, + "%s output Y%d recorded no IRQ samples" % (label, output)) + maximum = stats.maximum_cycles[output] + require(maximum > 0, + "%s output Y%d recorded a zero IRQ maximum" + % (label, output)) + require(maximum < IRQ_CYCLE_BUDGET_100KHZ, + "%s output Y%d IRQ maximum %d cycles exceeds < %d budget" + % (label, output, maximum, IRQ_CYCLE_BUDGET_100KHZ)) + print("INFO %s Y%d irq_count=%d last=%d max=%d cycles" + % (label, output, stats.count[output], + stats.last_cycles[output], maximum)) + + +def require_producer_cycle_budget(stats, label): + average = stats.average_cycles + require(stats.total_cycles >= stats.maximum_item_cycles, + "%s producer timing counters are inconsistent" % label) + require(average < IRQ_CYCLE_BUDGET_100KHZ, + "%s producer average %.2f cycles/item exceeds < %d budget" + % (label, average, IRQ_CYCLE_BUDGET_100KHZ)) + print("INFO %s producer_items=%d total=%d average=%.2f max=%d cycles" + % (label, stats.item_count, stats.total_cycles, + average, stats.maximum_item_cycles)) + + +def require_no_producer_activity(stats, label): + require(stats.item_count == 0, + "%s unexpectedly generated %d short-profile items" + % (label, stats.item_count)) + require(stats.total_cycles == 0, + "%s unexpectedly recorded %d producer cycles" + % (label, stats.total_cycles)) + require(stats.maximum_item_cycles == 0, + "%s unexpectedly recorded a %d-cycle producer maximum" + % (label, stats.maximum_item_cycles)) + print("INFO %s producer_items=0 total=0 max=0 cycles" % label) + + +def require_final_arm_cycle_budget(stats, expected_outputs, label): + for output in expected_outputs: + require(stats.queue_count[output] > 0, + "%s output Y%d queued no final-arm jobs" % (label, output)) + job_maximum = stats.job_maximum_cycles[output] + latency_maximum = stats.queue_to_stop_maximum_cycles[output] + require(job_maximum > 0, + "%s output Y%d recorded a zero final-arm job maximum" + % (label, output)) + require(latency_maximum > 0, + "%s output Y%d recorded a zero queue-to-stop maximum" + % (label, output)) + require(job_maximum < IRQ_CYCLE_BUDGET_100KHZ, + "%s output Y%d final-arm job maximum %d cycles exceeds < %d budget" + % (label, output, job_maximum, + IRQ_CYCLE_BUDGET_100KHZ)) + require(latency_maximum < IRQ_CYCLE_BUDGET_100KHZ, + "%s output Y%d queue-to-stop maximum %d cycles exceeds < %d budget" + % (label, output, latency_maximum, + IRQ_CYCLE_BUDGET_100KHZ)) + print( + "INFO %s Y%d final_arm_count=%d job_last=%d job_max=%d " + "queue_to_stop_last=%d queue_to_stop_max=%d cycles" + % (label, output, stats.queue_count[output], + stats.job_last_cycles[output], job_maximum, + stats.queue_to_stop_last_cycles[output], latency_maximum)) + + +def test_ab_100khz_timing_paths(client): + pulses_per_case = 100000 + for output, direction in ((0, 1), (2, -1)): + target = direction * pulses_per_case + label = "AB Y%d/Y%d %s timing" % ( + output, + output + 1, + "positive" if direction > 0 else "negative", + ) + clear_position(client) + configure_ab( + client, + output, + make_common( + default_hz=100000, + start_hz=100000, + stop_hz=100000, + ), + make_segment(100000, target), + ) + clear_diagnostic(client) + command(client, COMMAND_START) + wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES + and abs(item.position) >= 100 + and frequency_matches(item.frequency_hz, 100000), + 2.0, + "%s initial 100 kHz" % label, + ) + + # Both writes are committed at an AB zero boundary. The first measures + # PlsrAbLoadAndStart while the incoming cycle is still 100 kHz; the + # second returns the final gate path to the worst-case 10 us period. + client.write_multiple(SEGMENT_1_BASE, split_u32(80000)) + wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES + and frequency_matches(item.frequency_hz, 80000), + 2.0, + "%s dynamic 80 kHz" % label, + ) + client.write_multiple(SEGMENT_1_BASE, split_u32(100000)) + wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES + and frequency_matches(item.frequency_hz, 100000), + 2.0, + "%s restored 100 kHz" % label, + ) + status = wait_terminal(client, 3.0) + require(status.state == STATUS_COMPLETED, + "%s did not complete" % label) + require(status.position == target, + "%s position expected %d, got %d" + % (label, target, status.position)) + require_diagnostic_pass( + read_diagnostic(client), + pulses_per_case, + OUTPUT_AB, + direction > 0, + label, + ) + + +def run_timing(client, timing, keep_config): + snapshot = ( + client.read_holding(OUTPUT_MODE, 1)[0], + client.read_holding(CONFIG_BASE, COMMON_WORDS), + client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS), + client.read_holding(SEGMENT_2_BASE, SEGMENT_WORDS), + ) + try: + timing.reset() + run_case("timing_constant_100khz_four_outputs", + lambda: test_all_outputs_at_100khz(client)) + irq, _, _ = timing.read() + require_irq_cycle_budget(irq, range(4), "constant 100 kHz") + + timing.reset() + run_case("timing_short_final_profiles", + lambda: test_short_final_profiles(client)) + irq, producer, _ = timing.read() + require_irq_cycle_budget(irq, (0,), "10-pulse profiles") + require_producer_cycle_budget(producer, "10-pulse profiles") + + timing.reset() + run_case("timing_long_millisecond_ramp", + lambda: test_long_millisecond_ramp(client)) + irq, producer, _ = timing.read() + require_irq_cycle_budget(irq, (0,), "65,535-pulse 1 ms ramp") + require_no_producer_activity(producer, "65,535-pulse 1 ms ramp") + + timing.reset() + run_case("timing_ab_100khz_reload_and_fast_gate", + lambda: test_ab_100khz_timing_paths(client)) + irq, _, final_arm = timing.read() + require_irq_cycle_budget( + irq, (0, 2), "AB 100 kHz reload and fast gate") + require_final_arm_cycle_budget( + final_arm, (0, 2), "AB 100 kHz final arm") + finally: + if keep_config: + cleanup_preserving_primary_error( + lambda: safe_stop(client), + "timing motion stop", + ) + else: + cleanup_preserving_primary_error( + lambda: restore_configuration(client, snapshot), + "timing configuration restore", + ) def test_wait_time(client): clear_position(client) - configure( + configure_pulse_dir( client, make_common(start_hz=500), make_segment(500, 10, wait_type=WAIT_TIME, wait_time_ms=120), @@ -666,11 +1446,18 @@ def test_wait_time(client): observed_wait = time.monotonic() - waiting_at require(status.state == STATUS_COMPLETED, "WAIT_TIME did not complete") require(observed_wait >= 0.050, "WAIT_TIME completed implausibly early") + require_diagnostic_pass( + read_diagnostic(client), + 10, + OUTPUT_PULSE_DIR, + True, + "WAIT_TIME", + ) def test_act_time(client): clear_position(client) - configure( + configure_pulse_dir( client, make_common(start_hz=1000), make_segment(1000, 2000, wait_type=ACT_TIME, act_time_ms=80), @@ -683,7 +1470,7 @@ def test_act_time(client): def test_dynamic_frequency_and_repeated_stop(client): clear_position(client) - configure( + configure_pulse_dir( client, make_common(start_hz=500, deceleration_ms=150), make_segment(500, 3000), @@ -722,7 +1509,7 @@ def test_future_segment_frequency_applies_on_arrival(client): common = make_common(segment_count=2, start_hz=400) segment_1 = make_segment(400, 200) segment_2 = make_segment(700, 200) - configure(client, common, segment_1, segment_2) + configure_pulse_dir(client, common, segment_1, segment_2) command(client, COMMAND_START) wait_for_status( client, @@ -744,6 +1531,14 @@ def test_future_segment_frequency_applies_on_arrival(client): ) status = wait_terminal(client, 3.0) require(status.state == STATUS_COMPLETED, "two-segment move did not complete") + require_diagnostic_pass( + read_diagnostic(client), + 200, + OUTPUT_PULSE_DIR, + True, + "updated segment 2 frequency", + expected_segment=2, + ) def test_subsequent_future_frequency_rebuilds_handoff(client): @@ -755,7 +1550,7 @@ def test_subsequent_future_frequency_rebuilds_handoff(client): ) segment_1 = make_segment(400, 200) segment_2 = make_segment(700, 200) - configure(client, common, segment_1, segment_2) + configure_pulse_dir(client, common, segment_1, segment_2) command(client, COMMAND_START) wait_for_status( client, @@ -784,6 +1579,14 @@ def test_subsequent_future_frequency_rebuilds_handoff(client): "subsequent two-segment move did not complete") require(status.position == 400, "subsequent two-segment position expected 400") + require_diagnostic_pass( + read_diagnostic(client), + 200, + OUTPUT_PULSE_DIR, + True, + "subsequent segment 2 frequency", + expected_segment=2, + ) def require_fixture_level(fixture, input_selection, expected, label): @@ -817,7 +1620,11 @@ def test_wait_signal_input(client, fixture, input_selection): stop_hz=1000, ) common[0x02] = input_selection - configure(client, common, make_segment(1000, 50, wait_type=WAIT_SIGNAL)) + configure_pulse_dir( + client, + common, + make_segment(1000, 50, wait_type=WAIT_SIGNAL), + ) command(client, COMMAND_START) waiting = wait_for_status( client, @@ -833,6 +1640,13 @@ def test_wait_signal_input(client, fixture, input_selection): status = wait_terminal(client, 2.0) require(status.state == STATUS_COMPLETED, "WAIT_SIGNAL did not complete") require(status.position == 50, "WAIT_SIGNAL changed completed position") + require_diagnostic_pass( + read_diagnostic(client), + 50, + OUTPUT_PULSE_DIR, + True, + "X%d WAIT_SIGNAL" % (input_selection + 4), + ) fixture.drive(input_selection, False) @@ -845,7 +1659,11 @@ def test_ext_signal_input(client, fixture, input_selection, wait_type): stop_hz=1000, ) common[0x03] = input_selection - configure(client, common, make_segment(1000, 5000, wait_type=wait_type)) + configure_pulse_dir( + client, + common, + make_segment(1000, 5000, wait_type=wait_type), + ) command(client, COMMAND_START) wait_for_status( client, @@ -871,7 +1689,7 @@ def test_ext_or_complete_natural(client, fixture, input_selection): stop_hz=1000, ) common[0x03] = input_selection - configure( + configure_pulse_dir( client, common, make_segment(1000, 50, wait_type=EXT_OR_COMPLETE), @@ -882,15 +1700,24 @@ def test_ext_or_complete_natural(client, fixture, input_selection): "EXT_OR_COMPLETE natural branch did not complete") require(status.position == 50, "EXT_OR_COMPLETE natural branch expected 50 pulses") + require_diagnostic_pass( + read_diagnostic(client), + 50, + OUTPUT_PULSE_DIR, + True, + "X%d EXT_OR_COMPLETE natural" % (input_selection + 4), + ) def run_x45(client, fixture, keep_config): snapshot = ( + client.read_holding(OUTPUT_MODE, 1)[0], client.read_holding(CONFIG_BASE, COMMON_WORDS), client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS), client.read_holding(SEGMENT_2_BASE, SEGMENT_WORDS), ) try: + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) fixture.prepare() run_case("x45_electrical_scan", lambda: test_x45_electrical_scan(fixture)) @@ -920,32 +1747,295 @@ def run_x45(client, fixture, keep_config): ) finally: try: - fixture.all_off() + cleanup_preserving_primary_error( + fixture.all_off, + "X4/X5 output shutdown", + ) finally: try: - safe_stop(client) - if not keep_config: - restore_configuration(client, snapshot) + if keep_config: + cleanup_preserving_primary_error( + lambda: safe_stop(client), + "X4/X5 motion stop", + ) + else: + cleanup_preserving_primary_error( + lambda: restore_configuration(client, snapshot), + "X4/X5 configuration restore", + ) finally: - fixture.release() + cleanup_preserving_primary_error( + fixture.release, + "X4/X5 fixture release", + ) def safe_stop(client): + status = read_status(client) + if status.state in ACTIVE_STATES: + command(client, COMMAND_STOP) + wait_terminal(client, 3.0) + + +def cleanup_preserving_primary_error(cleanup, label, warning_stream=None): + primary_error = sys.exc_info()[1] try: - status = read_status(client) - if status.state in ACTIVE_STATES: - command(client, COMMAND_STOP) - wait_terminal(client, 3.0) - except (ModbusException, TestFailure, serial.SerialException): - pass + cleanup() + except Exception as cleanup_error: + if primary_error is None: + raise + message = "%s failed during error cleanup: %s: %s" % ( + label, + type(cleanup_error).__name__, + cleanup_error, + ) + if hasattr(primary_error, "add_note"): + primary_error.add_note(message) + if warning_stream is None: + warning_stream = sys.stderr + print("WARN: %s" % message, file=warning_stream) def restore_configuration(client, snapshot): safe_stop(client) command(client, COMMAND_CLEAR) - client.write_multiple(CONFIG_BASE, snapshot[0]) - client.write_multiple(SEGMENT_1_BASE, snapshot[1]) - client.write_multiple(SEGMENT_2_BASE, snapshot[2]) + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) + client.write_multiple(CONFIG_BASE, snapshot[1]) + segments = snapshot[2] if len(snapshot) == 3 else snapshot[2:] + for index, segment in enumerate(segments): + client.write_multiple(SEGMENT_1_BASE + index * 0x10, segment) + client.write_single(OUTPUT_MODE, snapshot[0]) + + +def snapshot_ab_configuration(client): + return ( + client.read_holding(OUTPUT_MODE, 1)[0], + client.read_holding(CONFIG_BASE, COMMON_WORDS), + client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS), + ) + + +def restore_ab_configuration(client, snapshot): + safe_stop(client) + command(client, COMMAND_CLEAR) + # PULSE/DIR accepts every pulse output, so use it while restoring a + # possible Y1/Y3 configuration that would be invalid in AB mode. + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) + client.write_multiple(CONFIG_BASE, snapshot[1]) + client.write_multiple(SEGMENT_1_BASE, snapshot[2]) + client.write_single(OUTPUT_MODE, snapshot[0]) + clear_diagnostic(client) + + +def configure_ab(client, output, common, segment): + require(output in (0, 2), "AB output must select Y0/Y1 or Y2/Y3") + common = list(common) + common[0x00] = output + client.write_multiple(CONFIG_BASE, common) + client.write_multiple(SEGMENT_1_BASE, segment) + client.write_single(OUTPUT_MODE, OUTPUT_AB) + require(client.read_holding(OUTPUT_MODE, 1) == [OUTPUT_AB], + "AB output mode readback failed") + + +def run_isolated_ab_case(client, name, function): + def isolated(): + snapshot = snapshot_ab_configuration(client) + try: + function() + finally: + cleanup_preserving_primary_error( + lambda: restore_ab_configuration(client, snapshot), + "%s configuration restore" % name, + ) + + run_case(name, isolated) + + +def test_ab_completed_motion(client, output, frequency_hz, pulses, curve_mode, + start_hz, stop_hz, acceleration_ms, + deceleration_ms, timeout, label): + clear_position(client) + configure_ab( + client, + output, + make_common( + curve_mode=curve_mode, + default_hz=frequency_hz, + start_hz=start_hz, + stop_hz=stop_hz, + acceleration_ms=acceleration_ms, + deceleration_ms=deceleration_ms, + ), + make_segment(frequency_hz, pulses), + ) + clear_diagnostic(client) + command(client, COMMAND_START) + status = wait_terminal(client, timeout) + require(status.state == STATUS_COMPLETED, + "%s did not complete" % label) + require(status.position == pulses, + "%s position expected %d, got %d" + % (label, pulses, status.position)) + diagnostic = read_diagnostic(client) + require_diagnostic_pass( + diagnostic, + abs(pulses), + OUTPUT_AB, + pulses >= 0, + label, + ) + print( + "INFO %s pair=Y%d/Y%d direction=%s requested=%dHz " + "timer=%dHz pulses=%d samples=%d" + % ( + label, + output, + output + 1, + "positive" if pulses >= 0 else "negative", + frequency_hz, + diagnostic.active_timer_hz, + diagnostic.actual_pulses, + diagnostic.sample_count, + ) + ) + + +def test_ab_stop(client): + expected_pulses = 50000 + clear_position(client) + configure_ab( + client, + 0, + make_common( + default_hz=2000, + start_hz=500, + stop_hz=500, + acceleration_ms=100, + deceleration_ms=100, + ), + make_segment(2000, expected_pulses), + ) + clear_diagnostic(client) + command(client, COMMAND_START) + wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES and item.position >= 10, + 3.0, + "AB STOP active motion", + ) + expect_exception( + lambda: client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR), + EX_DEVICE_BUSY, + "AB output mode write while busy", + ) + command(client, COMMAND_STOP) + status = wait_terminal(client, 4.0) + require(status.state == STATUS_STOPPED, "AB STOP did not enter STOPPED") + require(0 < status.position < expected_pulses, + "AB STOP did not cut the active move") + diagnostic = read_diagnostic(client) + require(not (diagnostic.flags & DIAG_MONITORING), + "AB STOP diagnostic remained active") + require(not (diagnostic.flags & DIAG_FAULT_LATCHED), + "AB STOP latched diagnostic fault %d" % diagnostic.reason) + require(not (diagnostic.flags & DIAG_COUNT_CHECKED), + "AB STOP incorrectly marked incomplete count as checked") + require(diagnostic.expected_pulses == expected_pulses, + "AB STOP diagnostic target mismatch") + require(0 < diagnostic.actual_pulses < expected_pulses, + "AB STOP diagnostic actual count is implausible") + require(diagnostic.output_mode == OUTPUT_AB, + "AB STOP diagnostic mode mismatch") + require(diagnostic.direction_positive, + "AB STOP diagnostic direction mismatch") + + +def test_ab_dynamic_frequency(client): + expected_pulses = 6000 + clear_position(client) + configure_ab( + client, + 2, + make_common( + default_hz=800, + start_hz=800, + stop_hz=800, + ), + make_segment(800, -expected_pulses), + ) + clear_diagnostic(client) + command(client, COMMAND_START) + wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES and item.position <= -10 + and frequency_matches(item.frequency_hz, 800), + 3.0, + "AB dynamic initial frequency", + ) + client.write_multiple(SEGMENT_1_BASE, split_u32(3200)) + dynamic = wait_for_status( + client, + lambda item: item.state in ACTIVE_STATES + and frequency_matches(item.frequency_hz, 3200), + 3.0, + "AB dynamic updated frequency", + ) + print("INFO AB dynamic frequency requested=3200 actual=%d" + % dynamic.frequency_hz) + status = wait_terminal(client, 6.0) + require(status.state == STATUS_COMPLETED, + "AB dynamic-frequency move did not complete") + require(status.position == -expected_pulses, + "AB dynamic-frequency position mismatch") + require_diagnostic_pass( + read_diagnostic(client), + expected_pulses, + OUTPUT_AB, + False, + "AB dynamic frequency", + ) + + +def run_ab(client): + cases = ( + ( + "ab_y0_y1_positive_1hz_linear_short", + lambda: test_ab_completed_motion( + client, 0, 1, 1, 0, 1, 1, 0, 0, 5.0, + "AB Y0/Y1 positive 1 Hz linear short", + ), + ), + ( + "ab_y0_y1_negative_typical_s_curve", + lambda: test_ab_completed_motion( + client, 0, 2500, -1200, 1, 250, 250, 80, 80, 5.0, + "AB Y0/Y1 negative typical S curve", + ), + ), + ( + "ab_y2_y3_positive_100khz_sine", + lambda: test_ab_completed_motion( + client, 2, 100000, 5000, 2, 1000, 1000, 20, 20, 4.0, + "AB Y2/Y3 positive 100 kHz sine", + ), + ), + ( + "ab_y2_y3_negative_typical_linear", + lambda: test_ab_completed_motion( + client, 2, 5000, -600, 0, 500, 500, 20, 20, 4.0, + "AB Y2/Y3 negative typical linear", + ), + ), + ) + for name, function in cases: + run_isolated_ab_case(client, name, function) + run_isolated_ab_case(client, "ab_stop", lambda: test_ab_stop(client)) + run_isolated_ab_case( + client, + "ab_dynamic_frequency", + lambda: test_ab_dynamic_frequency(client), + ) def run_smoke(client): @@ -954,16 +2044,24 @@ def run_smoke(client): def run_all(client, keep_config): snapshot = ( + client.read_holding(OUTPUT_MODE, 1)[0], client.read_holding(CONFIG_BASE, COMMON_WORDS), - client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS), - client.read_holding(SEGMENT_2_BASE, SEGMENT_WORDS), + [client.read_holding(SEGMENT_1_BASE + index * 0x10, SEGMENT_WORDS) + for index in range(10)], ) try: + client.write_single(OUTPUT_MODE, OUTPUT_PULSE_DIR) run_smoke(client) run_case( "positive_negative_absolute_zero", lambda: test_positive_negative_and_absolute_zero(client), ) + run_case("ten_segments_sequence", + lambda: test_ten_segments_in_sequence(client)) + run_case("start_segment_ten", + lambda: test_start_segment_ten(client)) + run_case("direction_output_polarity_matrix", + lambda: test_direction_output_and_polarity_matrix(client)) run_case("all_outputs_100khz", lambda: test_all_outputs_at_100khz(client)) run_case("short_final_profiles", @@ -984,31 +2082,232 @@ def run_all(client, keep_config): ) finally: if keep_config: - safe_stop(client) + cleanup_preserving_primary_error( + lambda: safe_stop(client), + "motion stop", + ) else: - restore_configuration(client, snapshot) + cleanup_preserving_primary_error( + lambda: restore_configuration(client, snapshot), + "configuration restore", + ) -def persistence_prepare(client): - clear_position(client) - configure( - client, - make_common(start_hz=500), - make_segment(500, 7), +def validate_persistence_live_parameters(duration_seconds, interval_seconds): + require(math.isfinite(duration_seconds), + "persistence-live duration must be finite") + require(duration_seconds >= PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + "persistence-live duration must be at least %.1f seconds" + % PERSISTENCE_LIVE_MIN_DURATION_SECONDS) + require(math.isfinite(interval_seconds), + "persistence-live interval must be finite") + require(0.0 < interval_seconds <= PERSISTENCE_LIVE_MAX_INTERVAL_SECONDS, + "persistence-live interval must be > 0 and <= %.3f seconds" + % PERSISTENCE_LIVE_MAX_INTERVAL_SECONDS) + + +def require_persistence_live_stats(stats, duration_seconds, label): + require(stats.attempts > 0, "%s made no FC03 attempts" % label) + require(stats.successful >= 0 and stats.timeouts >= 0, + "%s contains a negative counter" % label) + require(stats.attempts == stats.successful + stats.timeouts, + "%s counters are inconsistent" % label) + require(stats.timeouts == 0, + "%s had %d FC03 timeout(s)" % (label, stats.timeouts)) + require(stats.successful == stats.attempts, + "%s did not complete every FC03 request" % label) + require(math.isfinite(stats.maximum_attempt_seconds) + and stats.maximum_attempt_seconds >= 0.0, + "%s maximum attempt latency is invalid" % label) + require(stats.elapsed_seconds >= duration_seconds, + "%s probe ran %.3f s, expected at least %.3f s" + % (label, stats.elapsed_seconds, duration_seconds)) + + +def probe_persistence_live_window(client, duration_seconds, interval_seconds): + validate_persistence_live_parameters(duration_seconds, interval_seconds) + start = time.monotonic() + deadline = start + duration_seconds + next_request = start + attempts = 0 + successful = 0 + timeouts = 0 + maximum_attempt_seconds = 0.0 + reads = ( + (STATUS_BASE, STATUS_WORDS), + (PERSISTENCE_LIVE_CONFIG_ADDRESS, 1), + ) + + while True: + now = time.monotonic() + if now >= deadline: + break + if now < next_request: + time.sleep(min(next_request - now, deadline - now)) + now = time.monotonic() + if now >= deadline: + break + + address, quantity = reads[attempts % len(reads)] + request_started = time.monotonic() + attempts += 1 + try: + client.read_holding(address, quantity) + except RtuTimeout: + timeouts += 1 + else: + successful += 1 + attempt_seconds = time.monotonic() - request_started + maximum_attempt_seconds = max( + maximum_attempt_seconds, + attempt_seconds, + ) + + next_request += interval_seconds + if next_request < time.monotonic(): + next_request = time.monotonic() + + elapsed_seconds = time.monotonic() - start + return PersistenceLiveStats( + attempts=attempts, + successful=successful, + timeouts=timeouts, + maximum_attempt_seconds=maximum_attempt_seconds, + elapsed_seconds=elapsed_seconds, ) - command(client, COMMAND_START) - status = wait_terminal(client, 3.0) - require(status.state == STATUS_COMPLETED, "persistence move did not complete") - require(status.position == 7, "persistence position expected 7") - time.sleep(1.2) - require(read_status(client).position == 7, "position changed before reset") - print("PREPARED: release COM, reset/power-cycle the MCU, then run verify phase") + + +def print_persistence_live_result(label, stats, config_value): + print( + "INFO persistence-live window=%s attempts=%d successful=%d " + "timeouts=%d max_attempt_ms=%.3f elapsed_s=%.3f " + "config_0x%04X=%d" + % ( + label, + stats.attempts, + stats.successful, + stats.timeouts, + stats.maximum_attempt_seconds * 1000.0, + stats.elapsed_seconds, + PERSISTENCE_LIVE_CONFIG_ADDRESS, + config_value, + ) + ) + + +def persistence_live(client, duration_seconds, interval_seconds): + validate_persistence_live_parameters(duration_seconds, interval_seconds) + original = client.read_holding(PERSISTENCE_LIVE_CONFIG_ADDRESS, 1)[0] + changed = (original + 1) & 0xFFFF + original_timeout = client.timeout + client.timeout = min( + original_timeout, + PERSISTENCE_LIVE_REQUEST_TIMEOUT_SECONDS, + ) + print( + "INFO persistence-live duration_s=%.3f interval_ms=%.3f " + "request_timeout_ms=%.3f" + % ( + duration_seconds, + interval_seconds * 1000.0, + client.timeout * 1000.0, + ) + ) + + def restore_original_configuration(): + client.write_single(PERSISTENCE_LIVE_CONFIG_ADDRESS, original) + restore_stats = probe_persistence_live_window( + client, + duration_seconds, + interval_seconds, + ) + restore_readback = client.read_holding( + PERSISTENCE_LIVE_CONFIG_ADDRESS, + 1, + )[0] + print_persistence_live_result( + "restore", + restore_stats, + restore_readback, + ) + require_persistence_live_stats( + restore_stats, + duration_seconds, + "persistence-live restore window", + ) + require(restore_readback == original, + "persistence-live original config was not restored") + + try: + try: + client.write_single(PERSISTENCE_LIVE_CONFIG_ADDRESS, changed) + change_stats = probe_persistence_live_window( + client, + duration_seconds, + interval_seconds, + ) + change_readback = client.read_holding( + PERSISTENCE_LIVE_CONFIG_ADDRESS, + 1, + )[0] + print_persistence_live_result( + "change", + change_stats, + change_readback, + ) + require_persistence_live_stats( + change_stats, + duration_seconds, + "persistence-live change window", + ) + require(change_readback == changed, + "persistence-live changed config readback mismatch") + finally: + cleanup_preserving_primary_error( + restore_original_configuration, + "persistence-live configuration restore", + ) + finally: + client.timeout = original_timeout + + +def persistence_prepare(client, motion_timeout=3.0, settle_seconds=1.2, + announce=True): + snapshot = snapshot_ab_configuration(client) + prepared = False + try: + clear_position(client) + configure_ab( + client, + 0, + make_common(start_hz=500), + make_segment(500, 7), + ) + command(client, COMMAND_START) + status = wait_terminal(client, motion_timeout) + require(status.state == STATUS_COMPLETED, + "persistence move did not complete") + require(status.position == 7, "persistence position expected 7") + time.sleep(settle_seconds) + require(read_status(client).position == 7, + "position changed before reset") + prepared = True + finally: + if not prepared: + cleanup_preserving_primary_error( + lambda: restore_ab_configuration(client, snapshot), + "persistence preparation restore", + ) + if announce: + print("PREPARED: release COM, reset/power-cycle the MCU, then run verify phase") def persistence_verify(client, cleanup): status = read_status(client) require(status.state == STATUS_IDLE, "post-reset state must be IDLE") require(status.position == 7, "post-reset position expected 7") + require(client.read_holding(OUTPUT_MODE, 1) == [OUTPUT_AB], + "AB output mode was not restored after reset") segment = client.read_holding(SEGMENT_1_BASE, SEGMENT_WORDS) require(join_u32(segment[0], segment[1]) == 500, "frequency was not restored") require(join_i32(segment[2], segment[3]) == 7, "pulse target was not restored") @@ -1031,6 +2330,8 @@ def defaults_verify(client): status = read_status(client) require(status.state == STATUS_IDLE, "default state must be IDLE") require(status.position == 0, "default position must be zero") + require(client.read_holding(OUTPUT_MODE, 1) == [OUTPUT_PULSE_DIR], + "default output mode must be PULSE/DIR") common = client.read_holding(CONFIG_BASE, COMMON_WORDS) require(common[0x05] == 10, "default direction delay expected 10 ms") require(join_u32(common[0x0B], common[0x0C]) == 1000, @@ -1049,7 +2350,78 @@ def defaults_verify(client): "default segment %d pulse count mismatch" % (index + 1)) +class _PersistenceSelfTestClient: + def __init__(self, complete_on_start): + self.complete_on_start = complete_on_start + self.output_mode = OUTPUT_PULSE_DIR + self.common = make_common(default_hz=1234) + self.segment = make_segment(2345, -17) + self.state = STATUS_IDLE + self.position = 41 + self.calls = [] + + def read_holding(self, address, quantity): + self.calls.append(("read", address, quantity)) + if address == OUTPUT_MODE and quantity == 1: + return [self.output_mode] + if address == CONFIG_BASE and quantity == COMMON_WORDS: + return list(self.common) + if address == SEGMENT_1_BASE and quantity == SEGMENT_WORDS: + return list(self.segment) + if address == STATUS_BASE and quantity == STATUS_WORDS: + return ( + split_i32(self.position) + + split_u32(500) + + [self.state, 1 if self.state in ACTIVE_STATES else 0, ERROR_NONE] + ) + if address == DIAGNOSTIC_BASE and quantity == DIAGNOSTIC_WORDS: + words = [0] * DIAGNOSTIC_WORDS + words[24:26] = [0xFFFF, 0xFFFF] + return words + raise AssertionError("unexpected self-test read 0x%04X/%d" + % (address, quantity)) + + def write_single(self, address, value): + self.calls.append(("single", address, value)) + if address == OUTPUT_MODE: + self.output_mode = value + elif address == DIAGNOSTIC_CONTROL: + require(value == DIAGNOSTIC_CLEAR, + "self-test diagnostic command mismatch") + elif address == CONTROL: + if value == COMMAND_CLEAR: + self.state = STATUS_IDLE + self.position = 0 + elif value == COMMAND_START: + if self.complete_on_start: + self.state = STATUS_COMPLETED + self.position = 7 + else: + self.state = STATUS_RUNNING + self.position = 1 + elif value == COMMAND_STOP: + self.state = STATUS_STOPPED + else: + raise AssertionError("unexpected self-test control command") + else: + raise AssertionError("unexpected self-test single write 0x%04X" + % address) + + def write_multiple(self, address, values): + self.calls.append(("multiple", address, list(values))) + if address == CONFIG_BASE: + self.common = list(values) + elif address == SEGMENT_1_BASE: + self.segment = list(values) + else: + raise AssertionError("unexpected self-test multiple write 0x%04X" + % address) + + def self_test(): + def raise_error(error): + raise error + payload = bytes.fromhex("01 01 00 00 00 01") require(crc16(payload) == 0xCAFD, "CRC reference vector failed") require(append_crc(payload) == bytes.fromhex("01 01 00 00 00 01 FD CA"), @@ -1060,9 +2432,298 @@ def self_test(): require(frequency_matches(1199, 1200), "frequency tolerance rejected 1 Hz") require(not frequency_matches(1198, 1200), "frequency tolerance accepted excessive error") - sample = "\n0x42408214 : 00000001 \n" + sample = ( + "\n0x42408214 : 00000001 00000002 00000003 00000004 \n" + "0x42408224 : 00000005 \n" + ) require(parse_stlink_word(sample, X4_INPUT_BIT) == 1, "ST-LINK read parser failed") + require(parse_stlink_words(sample, X4_INPUT_BIT, 5) + == [1, 2, 3, 4, 5], + "ST-LINK multi-word parser failed") + map_sample = ( + "PlsrIrqCount 0x2000'4d80 0x10 Data Gb object.o\n" + "PlsrProfileProducerItemCount\n" + " 0x2000'61c0 0x4 Data Gb object.o\n" + ) + require(parse_iar_map_symbol_address(map_sample, "PlsrIrqCount") + == 0x20004D80, + "IAR map symbol parser failed") + require(parse_iar_map_symbol_address( + map_sample, "PlsrProfileProducerItemCount") == 0x200061C0, + "IAR wrapped map symbol parser failed") + passing_irq_stats = IrqCycleStats( + count=(1, 2, 3, 4), + last_cycles=(100, 200, 300, 400), + maximum_cycles=(1679, 1200, 900, 800), + ) + require_irq_cycle_budget( + passing_irq_stats, range(4), "timing self-test pass") + expect_test_failure( + lambda: require_irq_cycle_budget( + dataclasses.replace( + passing_irq_stats, + maximum_cycles=(IRQ_CYCLE_BUDGET_100KHZ, 1200, 900, 800), + ), + (0,), + "timing self-test reject", + ), + "IRQ cycle budget equality", + ) + passing_final_arm_stats = FinalArmCycleStats( + queue_count=(2, 0, 2, 0), + job_last_cycles=(700, 0, 800, 0), + job_maximum_cycles=(900, 0, 950, 0), + queue_to_stop_last_cycles=(1000, 0, 1100, 0), + queue_to_stop_maximum_cycles=(1200, 0, 1300, 0), + ) + require_final_arm_cycle_budget( + passing_final_arm_stats, (0, 2), "final-arm timing self-test pass") + for invalid_stats, label in ( + (dataclasses.replace( + passing_final_arm_stats, + job_maximum_cycles=(IRQ_CYCLE_BUDGET_100KHZ, 0, 950, 0)), + "final-arm job budget equality"), + (dataclasses.replace( + passing_final_arm_stats, + queue_to_stop_maximum_cycles=(1200, 0, + IRQ_CYCLE_BUDGET_100KHZ, 0)), + "final-arm latency budget equality"), + (dataclasses.replace( + passing_final_arm_stats, queue_count=(0, 0, 2, 0)), + "final-arm missing job"), + ): + expect_test_failure( + lambda item=invalid_stats: require_final_arm_cycle_budget( + item, (0, 2), "final-arm timing self-test reject"), + label, + ) + passing_producer_stats = ProducerCycleStats( + item_count=4, + total_cycles=6719, + maximum_item_cycles=1679, + ) + require_producer_cycle_budget( + passing_producer_stats, "producer timing self-test pass") + expect_test_failure( + lambda: require_producer_cycle_budget( + dataclasses.replace( + passing_producer_stats, + total_cycles=IRQ_CYCLE_BUDGET_100KHZ * 4, + maximum_item_cycles=IRQ_CYCLE_BUDGET_100KHZ, + ), + "producer timing self-test reject", + ), + "producer cycle budget equality", + ) + no_producer_stats = ProducerCycleStats( + item_count=0, + total_cycles=0, + maximum_item_cycles=0, + ) + require_no_producer_activity( + no_producer_stats, "long-ramp producer self-test pass") + for invalid_stats, label in ( + (dataclasses.replace(no_producer_stats, item_count=1), + "long-ramp producer item count"), + (dataclasses.replace(no_producer_stats, total_cycles=1), + "long-ramp producer total cycles"), + (dataclasses.replace(no_producer_stats, maximum_item_cycles=1), + "long-ramp producer maximum cycles"), + ): + expect_test_failure( + lambda item=invalid_stats: require_no_producer_activity( + item, "long-ramp producer self-test reject"), + label, + ) + diagnostic_words = [ + DIAG_COMPLETE_PASS, 0, 3, 0x0101, + 0x5678, 0x1234, 0x5678, 0x1234, + 0, 0, 0x86A0, 1, 0x869F, 1, 0x869F, 1, + 0xFFFF, 0xFFFF, 0x4321, 0x0002, 0, 0, 0, 0, + 0xFFFF, 0xFFFF, + ] + diagnostic = parse_diagnostic(diagnostic_words) + require(DIAGNOSTIC_BASE == 0x2100 and DIAGNOSTIC_WORDS == 26, + "diagnostic address or length changed") + require(OUTPUT_MODE == 0x1200 and DIAGNOSTIC_CONTROL == 0x3100, + "enhanced configuration/control address changed") + require(diagnostic.output_mode == OUTPUT_AB, + "diagnostic mode parser failed") + require(diagnostic.direction_positive, + "diagnostic direction parser failed") + require(diagnostic.expected_pulses == 0x12345678, + "diagnostic expected count parser failed") + require(diagnostic.actual_pulses == 0x12345678, + "diagnostic actual count parser failed") + require(diagnostic.requested_hz == 100000, + "diagnostic requested frequency parser failed") + require(diagnostic.request_error_hz == -1, + "diagnostic signed frequency error parser failed") + require(diagnostic.sample_count == 0x00024321, + "diagnostic sample count parser failed") + require(diagnostic.first_mismatch_sample == 0xFFFFFFFF, + "diagnostic sentinel parser failed") + require((DIAG_COMPLETE_PASS & DIAG_FAULT_LATCHED) == 0, + "diagnostic pass mask includes fault bit") + + for expected_error in ( + ModbusException(0x03, EX_DEVICE_BUSY), + serial.SerialException("self-test serial failure"), + ): + class ReadFailureClient: + def read_holding(self, address, quantity): + raise expected_error + + try: + safe_stop(ReadFailureClient()) + except Exception as actual_error: + require(actual_error is expected_error, + "safe_stop replaced the original communication error") + else: + raise TestFailure("safe_stop swallowed a communication error") + + primary_error = TestFailure("primary board-test failure") + cleanup_error = ModbusException(0x06, EX_DEVICE_BUSY) + cleanup_warning = io.StringIO() + caught_error = None + try: + try: + raise primary_error + finally: + cleanup_preserving_primary_error( + lambda: raise_error(cleanup_error), + "self-test configuration restore", + cleanup_warning, + ) + except TestFailure as error: + caught_error = error + require(caught_error is primary_error, + "cleanup failure replaced the primary board-test failure") + require("self-test configuration restore failed during error cleanup" + in cleanup_warning.getvalue(), + "cleanup failure warning omitted its operation context") + if hasattr(primary_error, "add_note"): + require(any("self-test configuration restore" in note + for note in getattr(primary_error, "__notes__", ())), + "cleanup failure was not attached to the primary exception") + + cleanup_error = serial.SerialException("standalone cleanup failure") + try: + cleanup_preserving_primary_error( + lambda: raise_error(cleanup_error), + "self-test standalone cleanup", + io.StringIO(), + ) + except serial.SerialException as error: + require(error is cleanup_error, + "standalone cleanup failure was replaced") + else: + raise TestFailure("standalone cleanup failure was swallowed") + + validate_persistence_live_parameters( + PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + PERSISTENCE_LIVE_MAX_INTERVAL_SECONDS, + ) + invalid_live_parameters = ( + (PERSISTENCE_LIVE_MIN_DURATION_SECONDS - 0.001, 0.05, + "short persistence-live duration"), + (float("nan"), 0.05, "NaN persistence-live duration"), + (float("inf"), 0.05, "infinite persistence-live duration"), + (PERSISTENCE_LIVE_MIN_DURATION_SECONDS, 0.0, + "zero persistence-live interval"), + (PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + PERSISTENCE_LIVE_MAX_INTERVAL_SECONDS + 0.001, + "long persistence-live interval"), + (PERSISTENCE_LIVE_MIN_DURATION_SECONDS, float("nan"), + "NaN persistence-live interval"), + ) + for duration_seconds, interval_seconds, label in invalid_live_parameters: + expect_test_failure( + lambda duration=duration_seconds, interval=interval_seconds: + validate_persistence_live_parameters(duration, interval), + label, + ) + + passing_live_stats = PersistenceLiveStats( + attempts=50, + successful=50, + timeouts=0, + maximum_attempt_seconds=0.012, + elapsed_seconds=PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + ) + require_persistence_live_stats( + passing_live_stats, + PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + "persistence-live self-test pass", + ) + failing_live_stats = ( + (dataclasses.replace(passing_live_stats, successful=49, timeouts=1), + "persistence-live timeout stats"), + (dataclasses.replace(passing_live_stats, successful=49), + "persistence-live inconsistent stats"), + (dataclasses.replace(passing_live_stats, attempts=0, successful=0), + "persistence-live empty stats"), + (dataclasses.replace(passing_live_stats, elapsed_seconds=2.499), + "persistence-live short elapsed stats"), + (dataclasses.replace(passing_live_stats, + maximum_attempt_seconds=float("nan")), + "persistence-live invalid latency stats"), + ) + for stats, label in failing_live_stats: + expect_test_failure( + lambda item=stats: require_persistence_live_stats( + item, + PERSISTENCE_LIVE_MIN_DURATION_SECONDS, + "persistence-live self-test reject", + ), + label, + ) + + failed_prepare = _PersistenceSelfTestClient(complete_on_start=False) + original_common = list(failed_prepare.common) + original_segment = list(failed_prepare.segment) + try: + persistence_prepare( + failed_prepare, + motion_timeout=0.0, + settle_seconds=0.0, + announce=False, + ) + except TestFailure: + pass + else: + raise TestFailure("failed persistence prepare unexpectedly succeeded") + controls = [call[2] for call in failed_prepare.calls + if call[:2] == ("single", CONTROL)] + require(COMMAND_STOP in controls, + "failed persistence prepare did not issue STOP") + require(failed_prepare.output_mode == OUTPUT_PULSE_DIR, + "failed persistence prepare did not restore output mode") + require(failed_prepare.common == original_common, + "failed persistence prepare did not restore common config") + require(failed_prepare.segment == original_segment, + "failed persistence prepare did not restore segment config") + + successful_prepare = _PersistenceSelfTestClient(complete_on_start=True) + persistence_prepare( + successful_prepare, + motion_timeout=0.1, + settle_seconds=0.0, + announce=False, + ) + controls = [call[2] for call in successful_prepare.calls + if call[:2] == ("single", CONTROL)] + require(COMMAND_STOP not in controls, + "successful persistence prepare issued STOP") + require(successful_prepare.output_mode == OUTPUT_AB, + "successful persistence prepare did not retain AB mode") + require(join_u32(successful_prepare.segment[0], + successful_prepare.segment[1]) == 500, + "successful persistence prepare did not retain frequency") + require(join_i32(successful_prepare.segment[2], + successful_prepare.segment[3]) == 7, + "successful persistence prepare did not retain pulse target") print("Self-test passed; no serial port was opened") @@ -1071,7 +2732,10 @@ def print_preflight(args): print(" - Firmware containing the PLSR 0x1000/0x2000/0x3000 map is flashed.") print(" - RS-485 is %d baud, 8E1, slave %d on %s." % (args.baud, args.slave, args.port)) - print(" - Y0 pulse and Y12 direction outputs are safe to toggle.") + if args.phase == "ab": + print(" - Y0/Y1 and Y2/Y3 AB output pairs are safe to toggle.") + else: + print(" - Configured pulse, direction, and AB-pair outputs are safe to toggle.") print(" - No other program has the COM port open.") print("Run smoke only:") print(" py -B HostComputer\\plsr_modbus_product_test.py --run --phase smoke") @@ -1079,6 +2743,12 @@ def print_preflight(args): print(" py -B HostComputer\\plsr_modbus_product_test.py --run --allow-motion") print("Run X4/X5 loopback tests:") print(" py -B HostComputer\\plsr_modbus_product_test.py --run --phase x45 --allow-motion") + print("Run AB output and diagnostic matrix:") + print(" py -B HostComputer\\plsr_modbus_product_test.py --run --phase ab --allow-motion") + print("Run DWT ISR/producer timing acceptance:") + print(" py -B HostComputer\\plsr_modbus_product_test.py --run --phase timing --allow-motion") + print("Run persistence communication-window test:") + print(" py -B HostComputer\\plsr_modbus_product_test.py --run --phase persistence-live") print("Run offline checks:") print(" py -B HostComputer\\plsr_modbus_product_test.py --self-test") @@ -1092,20 +2762,34 @@ def parse_arguments(): parser.add_argument("--stlink-cli", default=DEFAULT_STLINK_CLI) parser.add_argument("--stlink-id", type=int, default=0) parser.add_argument("--stlink-timeout", type=float, default=20.0) + parser.add_argument("--iar-map", default=DEFAULT_IAR_MAP) parser.add_argument( "--phase", - choices=("smoke", "all", "x45", "persistence-prepare", - "persistence-verify", "defaults-verify"), + choices=("smoke", "all", "ab", "x45", "timing", "persistence-prepare", + "persistence-verify", "persistence-live", + "defaults-verify"), default="all", ) parser.add_argument("--run", action="store_true", help="open the serial port and execute the selected phase") parser.add_argument("--allow-motion", action="store_true", - help="confirm that pulse and direction outputs may toggle") + help="confirm that configured motion outputs may toggle") parser.add_argument("--keep-config", action="store_true", - help="do not restore the three modified config blocks") + help="retain matrix config; AB phase always restores each case") parser.add_argument("--cleanup", action="store_true", help="CLEAR position after persistence verification") + parser.add_argument( + "--persistence-duration", + type=float, + default=PERSISTENCE_LIVE_DEFAULT_DURATION_SECONDS, + help="seconds to probe each persistence-live window (minimum 2.5)", + ) + parser.add_argument( + "--persistence-interval", + type=float, + default=PERSISTENCE_LIVE_DEFAULT_INTERVAL_SECONDS, + help="seconds between persistence-live FC03 requests (maximum 0.1)", + ) parser.add_argument("--self-test", action="store_true", help="run offline CRC/word tests without opening a port") return parser.parse_args() @@ -1126,7 +2810,8 @@ def main(): print_preflight(args) return 0 - motion_phase = args.phase in ("all", "x45", "persistence-prepare") + motion_phase = args.phase in ( + "all", "ab", "x45", "timing", "persistence-prepare") if motion_phase and not args.allow_motion: raise TestFailure("motion phase requires --allow-motion") @@ -1137,6 +2822,8 @@ def main(): run_smoke(client) elif args.phase == "all": run_all(client, args.keep_config) + elif args.phase == "ab": + run_ab(client) elif args.phase == "x45": fixture = X45Fixture( args.stlink_cli, @@ -1144,10 +2831,24 @@ def main(): args.stlink_timeout, ) run_x45(client, fixture, args.keep_config) + elif args.phase == "timing": + probe = X45Fixture( + args.stlink_cli, + args.stlink_id, + args.stlink_timeout, + ) + timing = TimingFixture(probe, args.iar_map) + run_timing(client, timing, args.keep_config) elif args.phase == "persistence-prepare": persistence_prepare(client) elif args.phase == "persistence-verify": persistence_verify(client, args.cleanup) + elif args.phase == "persistence-live": + persistence_live( + client, + args.persistence_duration, + args.persistence_interval, + ) else: defaults_verify(client) print("PASS phase=%s" % args.phase) diff --git a/Middlewares/Third_Party/Micrium/Config/app_cfg.h b/Middlewares/Third_Party/Micrium/Config/app_cfg.h index 7059bcf..9d31e9b 100644 --- a/Middlewares/Third_Party/Micrium/Config/app_cfg.h +++ b/Middlewares/Third_Party/Micrium/Config/app_cfg.h @@ -9,13 +9,12 @@ #define APP_TASK_TEST_PRIO 6u /* - * 任务栈大小的单位是OS_STK元素。当前OS_STK为32位， - * 所以每个256元素的任务栈实际占用1024字节RAM。 + * 任务栈大小的单位是OS_STK元素。当前OS_STK为32位。 */ -#define APP_TASK_START_STK_SIZE 256u +#define APP_TASK_START_STK_SIZE 512u #define APP_TASK_TEST_STK_SIZE 256u /* The short-profile pulse IRQ needs more than the port's 128-word default. */ -#define OS_CPU_EXCEPT_STK_SIZE 256u +#define OS_CPU_EXCEPT_STK_SIZE 512u #endif diff --git a/Modbus/Inc/modbus_rtu_slave.h b/Modbus/Inc/modbus_rtu_slave.h index 7c38bad..0e68a8b 100644 --- a/Modbus/Inc/modbus_rtu_slave.h +++ b/Modbus/Inc/modbus_rtu_slave.h @@ -13,6 +13,7 @@ extern "C" { HAL_StatusTypeDef ModbusSlaveInit(UART_HandleTypeDef *huart, uint8_t slaveAddress); void ModbusSlavePoll(void); +uint8_t ModbusSlaveIsIdle(void); void ModbusSlaveOnRxEvent(UART_HandleTypeDef *huart, uint16_t size); void ModbusSlaveOnTxComplete(UART_HandleTypeDef *huart); void ModbusSlaveOnUartError(UART_HandleTypeDef *huart); diff --git a/Modbus/Src/modbus_rtu_slave.c b/Modbus/Src/modbus_rtu_slave.c index e08adb0..8a536cf 100644 --- a/Modbus/Src/modbus_rtu_slave.c +++ b/Modbus/Src/modbus_rtu_slave.c @@ -39,6 +39,7 @@ static volatile uint32_t ModbusRxLastByteCycle; static volatile uint16_t ModbusRxFrameLength; static volatile uint8_t ModbusRxFrameReady; static volatile uint8_t ModbusTxBusy; +static volatile uint32_t ModbusLastActivityCycle; static uint32_t ModbusRtuCharCycles; static uint32_t ModbusRtuT15Cycles; @@ -451,6 +452,7 @@ HAL_StatusTypeDef ModbusSlaveInit(UART_HandleTypeDef *huart, ModbusRxFrameReady = 0U; ModbusTxBusy = 0U; ModbusRtuTimingInit(huart->Init.BaudRate); + ModbusLastActivityCycle = DWT->CYCCNT; return ModbusStartReceive(); } @@ -496,6 +498,42 @@ void ModbusSlavePoll(void) } } +uint8_t ModbusSlaveIsIdle(void) +{ + uint32_t primask; + uint32_t now; + uint8_t isIdle = 0U; + + if ((ModbusUart == NULL) || (ModbusUart->hdmarx == NULL)) + { + return 0U; + } + + primask = ModbusEnterCritical(); + if ((ModbusRxAssemblyLength == 0U) + && (ModbusRxAssemblyInvalid == 0U) + && (ModbusRxFrameReady == 0U) + && (ModbusTxBusy == 0U) + && (ModbusUart->RxState == HAL_UART_STATE_BUSY_RX) + && ((ModbusUart->Instance->CR3 & USART_CR3_DMAR) != 0U) + && ((ModbusUart->hdmarx->Instance->CR & DMA_SxCR_EN) != 0U) + && (__HAL_DMA_GET_COUNTER(ModbusUart->hdmarx) + == MODBUS_RTU_ADU_SIZE_MAX) + && ((ModbusUart->Instance->SR + & (USART_SR_PE | USART_SR_FE | USART_SR_NE | USART_SR_ORE + | USART_SR_IDLE | USART_SR_RXNE)) == 0U)) + { + now = DWT->CYCCNT; + if ((uint32_t)(now - ModbusLastActivityCycle) + >= ModbusRtuT35Cycles) + { + isIdle = 1U; + } + } + ModbusExitCritical(primask); + return isIdle; +} + void ModbusSlaveOnRxEvent(UART_HandleTypeDef *huart, uint16_t size) { HAL_UART_RxEventTypeTypeDef eventType; @@ -510,6 +548,8 @@ void ModbusSlaveOnRxEvent(UART_HandleTypeDef *huart, uint16_t size) return; } + now = DWT->CYCCNT; + ModbusLastActivityCycle = now; eventType = HAL_UARTEx_GetRxEventType(huart); if (eventType == HAL_UART_RXEVENT_HT) { @@ -524,7 +564,6 @@ void ModbusSlaveOnRxEvent(UART_HandleTypeDef *huart, uint16_t size) return; } - now = DWT->CYCCNT; lastByteCycle = now; if (eventType == HAL_UART_RXEVENT_IDLE) { @@ -571,6 +610,7 @@ void ModbusSlaveOnTxComplete(UART_HandleTypeDef *huart) return; } + ModbusLastActivityCycle = DWT->CYCCNT; ModbusTxBusy = 0U; (void)ModbusStartReceive(); } @@ -582,6 +622,7 @@ void ModbusSlaveOnUartError(UART_HandleTypeDef *huart) return; } + ModbusLastActivityCycle = DWT->CYCCNT; ModbusTxBusy = 0U; ModbusRxAssemblyLength = 0U; ModbusRxAssemblyInvalid = 0U; diff --git a/PLSR/Inc/plsr.h b/PLSR/Inc/plsr.h index 12f5cf2..47474e5 100644 --- a/PLSR/Inc/plsr.h +++ b/PLSR/Inc/plsr.h @@ -13,6 +13,11 @@ extern "C" { #define PLSR_STATUS_LAST_ADDRESS (0x2006U) #define PLSR_CONTROL_ADDRESS (0x3000U) +#define PLSR_OUTPUT_MODE_ADDRESS (0x1200U) +#define PLSR_DIAGNOSTIC_FIRST_ADDRESS (0x2100U) +#define PLSR_DIAGNOSTIC_LAST_ADDRESS (0x2119U) +#define PLSR_DIAGNOSTIC_CONTROL_ADDRESS (0x3100U) + typedef enum { PLSR_MB_NOT_HANDLED = 0, @@ -53,6 +58,7 @@ typedef enum uint8_t PlsrInit(void); void PlsrPoll1ms(void); +void PlsrServicePersistence(void); PLSR_MB_RESULT PlsrModbusReadHolding(uint16_t startAddress, uint16_t quantity, @@ -63,6 +69,7 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, /* Called by the selected output timer update interrupt once per pulse. */ void PlsrPulseTimerIrq(uint8_t pulseOutput); +void PlsrFinalArmJobIrq(uint8_t pulseOutput); #ifdef PLSR_HOST_TEST uint64_t PlsrTestDivideU64ByU32(uint64_t dividend, @@ -74,19 +81,52 @@ void PlsrTestEmitPulseOnCriticalEntry(void); void PlsrTestEmitPulseAfterCriticalEntries(uint8_t entriesToSkip); void PlsrTestEmitPulseOnCriticalExit(void); void PlsrTestLatchPulseOnCriticalEntry(void); +void PlsrTestLatchAbFinalQuarterOnNextStopArm(void); +void PlsrTestCompleteAbCycleOnNextQueueCommit(void); void PlsrTestServicePendingPulse(void); +void PlsrTestServiceFinalArmJob(void); +void PlsrTestDeferFinalArmJob(uint8_t defer); void PlsrTestFailNextStart(void); +void PlsrTestStaleNextFrequencyAtUpdate(void); void PlsrTestFailNextFrequencyAtUpdate(void); +void PlsrTestFailNextStopRequest(void); +void PlsrTestEmitAbQuarters(uint32_t quarterCount); uint8_t PlsrTestPulseIsActive(void); uint32_t PlsrTestOutputFrequency(void); uint32_t PlsrTestQueuedFrequency(void); uint8_t PlsrTestDirectionLevel(void); +uint8_t PlsrTestDirectionPinLevel(uint8_t directionOutput); +uint32_t PlsrTestDirectionWriteCount(uint8_t directionOutput); +uint32_t PlsrTestDirectionTransitionCount(uint8_t directionOutput); +uint8_t PlsrTestAbPhase(void); +uint32_t PlsrTestAbTransitionCount(void); +uint32_t PlsrTestAbFastGateCount(void); +uint32_t PlsrTestAbCleanupCount(void); +void PlsrTestInjectCountOffset(int32_t offset); +void PlsrTestInjectActiveFrequencyOffset(int32_t offsetHz); +void PlsrTestInjectCurveMismatch(void); +void PlsrTestForceProfileQueueEmpty(void); +uint16_t PlsrTestProfileQueueCount(void); +uint32_t PlsrTestProfileQueueGeneration(void); +uint32_t PlsrTestProfileQueueReadIndex(void); +uint32_t PlsrTestProfileQueueWriteIndex(void); +uint32_t PlsrTestProfileQueueHeadFrequency(void); +uint16_t PlsrTestProfileProducerNextPeriod(void); +uint16_t PlsrTestActiveProfileNextPeriod(void); +uint32_t PlsrTestLastGateEvent(void); +uint32_t PlsrTestLastDiagnosticFinishEvent(void); void PlsrTestSetPosition(int32_t position, uint8_t positionValid); void PlsrTestClearPersistentStorage(void); void PlsrTestResetSaveCount(void); uint32_t PlsrTestSaveCount(void); #endif +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) +extern volatile uint32_t PlsrProfileProducerItemCount; +extern volatile uint32_t PlsrProfileProducerTotalCycles; +extern volatile uint32_t PlsrProfileProducerMaxItemCycles; +#endif + #ifdef __cplusplus } #endif diff --git a/PLSR/Src/plsr.c b/PLSR/Src/plsr.c index 9445eb3..a26bc9c 100644 --- a/PLSR/Src/plsr.c +++ b/PLSR/Src/plsr.c @@ -29,9 +29,27 @@ #define PLSR_COMMAND_STOP (0x0002U) #define PLSR_COMMAND_CLEAR (0x0004U) +#define PLSR_DIAG_FLAG_MONITORING (0x0001U) +#define PLSR_DIAG_FLAG_COUNT_CHECKED (0x0002U) +#define PLSR_DIAG_FLAG_COUNT_PASS (0x0004U) +#define PLSR_DIAG_FLAG_FREQUENCY_CHECKED (0x0008U) +#define PLSR_DIAG_FLAG_FREQUENCY_PASS (0x0010U) +#define PLSR_DIAG_FLAG_CURVE_CHECKED (0x0020U) +#define PLSR_DIAG_FLAG_CURVE_PASS (0x0040U) +#define PLSR_DIAG_FLAG_FAULT_LATCHED (0x0080U) + +#define PLSR_DIAG_REASON_NONE (0U) +#define PLSR_DIAG_REASON_COUNT (1U) +#define PLSR_DIAG_REASON_FREQUENCY (2U) +#define PLSR_DIAG_REASON_CURVE (3U) +#define PLSR_DIAG_REASON_INVALID_SAMPLE (4U) + #define PLSR_CONFIG_SAVE_DELAY_MS (1000U) #define PLSR_POSITION_CHECKPOINT_MS (10U) -#define PLSR_SHORT_PROFILE_MAX_PULSES (65535UL) +#define PLSR_PROFILE_QUEUE_CAPACITY (256U) +#define PLSR_PROFILE_QUEUE_MASK (PLSR_PROFILE_QUEUE_CAPACITY - 1U) +#define PLSR_SHORT_PROFILE_MAX_PULSES \ + ((uint32_t)PLSR_PROFILE_QUEUE_CAPACITY + 2UL) #define PLSR_Q32_ONE (4294967296ULL) typedef struct @@ -68,10 +86,35 @@ typedef struct volatile uint8_t active; } PLSR_SHORT_PROFILE; +typedef struct +{ + PLSR_PLATFORM_TIMER_SETTING setting; + uint32_t requestedFrequencyHz; +} PLSR_PROFILE_ENTRY; + +typedef struct +{ + PLSR_PROFILE_ENTRY entries[PLSR_PROFILE_QUEUE_CAPACITY]; + PLSR_SHORT_PROFILE producerProfile; + volatile uint32_t readIndex; + volatile uint32_t writeIndex; + volatile uint32_t generation; + uint32_t producerEpoch; + uint8_t producerSegment; + uint8_t preparedHandoffBank; + volatile uint8_t active; + volatile uint8_t generatorComplete; +} PLSR_PROFILE_QUEUE; + typedef struct { uint64_t magnitude; uint32_t firstFrequencyHz; + uint32_t secondFrequencyHz; + uint32_t firstRequestedFrequencyHz; + uint32_t secondRequestedFrequencyHz; + PLSR_PLATFORM_TIMER_SETTING firstSetting; + PLSR_PLATFORM_TIMER_SETTING secondSetting; PLSR_SHORT_PROFILE profile; uint8_t nextSegment; uint8_t positive; @@ -99,6 +142,25 @@ typedef struct volatile uint8_t state; } PLSR_COMMAND_MAILBOX; +typedef struct +{ + uint16_t flags; + uint16_t reason; + uint16_t lastSegment; + uint16_t modeDirection; + uint32_t expectedCycles; + uint32_t observedCycles; + int32_t countError; + uint32_t requestedHz; + uint32_t expectedTimerHz; + uint32_t activeTimerHz; + int32_t requestErrorHz; + uint32_t curveSampleCount; + uint32_t curveMismatchCount; + uint32_t curveMaxAbsErrorHz; + uint32_t firstMismatchSample; +} PLSR_DIAGNOSTIC; + static const uint16_t PlsrSineProgressQ16[65] = { 0U, 39U, 158U, 355U, 630U, 982U, 1411U, 1915U, @@ -171,10 +233,16 @@ static volatile PLSR_STATUS PlsrRunStatus = PLSR_STATUS_UNINITIALIZED; static PLSR_ERROR PlsrError = PLSR_ERROR_NONE; static PLSR_RAMP PlsrRamp; static PLSR_SHORT_PROFILE PlsrShortProfile; +static PLSR_PROFILE_QUEUE PlsrProfileQueue; static PLSR_HANDOFF_PLAN PlsrHandoffPlan; static PLSR_HANDOFF_PLAN PlsrPreparedHandoffPlans[2][PLSR_SEGMENT_COUNT_MAX]; static volatile uint8_t PlsrPreparedHandoffBank; +#ifdef PLSR_HOST_TEST +static uint32_t PlsrHostTestEventSequence; +static uint32_t PlsrHostTestLastGateEvent; +static uint32_t PlsrHostTestLastDiagnosticFinishEvent; +#endif static uint8_t PlsrInitialized; static volatile uint8_t PlsrCurrentSegment; static uint8_t PlsrDirectionDelayActive; @@ -186,6 +254,7 @@ static volatile uint8_t PlsrExtPreviousLevel; static volatile uint8_t PlsrExtEdgePending; static volatile uint8_t PlsrStopRequested; static volatile uint8_t PlsrStopPulsesRemaining; +static volatile uint8_t PlsrAbStopArmed; static volatile uint8_t PlsrBoundaryRampStarted; static uint8_t PlsrLastDirectionValid; static uint8_t PlsrLastDirectionOutput; @@ -194,6 +263,16 @@ static uint8_t PlsrPersistenceDirty; static uint16_t PlsrPersistenceDelayMs; static uint8_t PlsrPositionCheckpointElapsedMs; static PLSR_COMMAND_MAILBOX PlsrCommandMailbox; +static volatile PLSR_DIAGNOSTIC PlsrDiagnostic; +static volatile uint64_t PlsrDiagnosticSegmentCounterBase; +static volatile uint32_t PlsrDiagnosticQueuedExpectedHz; +static volatile uint16_t PlsrDiagnosticFailedChecks; + +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) +volatile uint32_t PlsrProfileProducerItemCount; +volatile uint32_t PlsrProfileProducerTotalCycles; +volatile uint32_t PlsrProfileProducerMaxItemCycles; +#endif static uint8_t PlsrIsBusy(void); static void PlsrSetDefaults(PLSR_CONFIG *config); @@ -223,24 +302,50 @@ static void PlsrEnterError(PLSR_ERROR error); static void PlsrMarkPersistenceDirty(uint16_t delayMs); static void PlsrCheckpointPosition(uint8_t wasBusy); static void PlsrPollPositionCheckpoint(void); -static uint8_t PlsrTrySubsequentHandoff(void); +static PLSR_PLATFORM_QUEUE_RESULT PlsrTrySubsequentHandoff(void); static uint8_t PlsrPrepareShortProfile(PLSR_SHORT_PROFILE *profile, uint8_t segmentNumber, uint32_t startFrequencyHz, uint32_t targetFrequencyHz, uint64_t pulseCount); static uint32_t PlsrShortProfileTakeFrequency(PLSR_SHORT_PROFILE *profile); -static uint8_t PlsrAdvanceShortProfile(uint8_t pulseOutput); +static void PlsrProfileQueueReset(void); +static uint8_t PlsrProfileQueueBegin( + const PLSR_SHORT_PROFILE *producerProfile, + uint32_t producerEpoch, + uint8_t producerSegment, + uint8_t preparedHandoffBank); +static uint8_t PlsrProfileQueueFill(void); +static PLSR_PLATFORM_QUEUE_RESULT PlsrProfileQueueCommitNext( + uint8_t pulseOutput); +static uint8_t PlsrPrepareFutureHandoffQueue(void); static void PlsrCopyShortProfile(PLSR_SHORT_PROFILE *destination, const PLSR_SHORT_PROFILE *source); static void PlsrInvalidateHandoffPlans(void); static uint8_t PlsrBuildHandoffPlanBank( const PLSR_CONFIG *frequencyConfig); static uint8_t PlsrSelectPreparedHandoffPlan(PLSR_HANDOFF_PLAN *plan); -static uint8_t PlsrPrimeHandoff(void); +static PLSR_PLATFORM_QUEUE_RESULT PlsrPrimeHandoff(void); static uint8_t PlsrBuildHandoffPlan(uint8_t sourceSegment, const PLSR_CONFIG *frequencyConfig, PLSR_HANDOFF_PLAN *plan); +static void PlsrDiagnosticReset(void); +static void PlsrDiagnosticBeginSegment(uint8_t segmentNumber, + uint64_t expectedCycles, + uint8_t directionPositive); +static void PlsrDiagnosticFinishSegment(uint8_t completedNormally); +static uint8_t PlsrDiagnosticStartPulse(uint8_t pulseOutput, + uint32_t requestedFirstHz, + uint32_t requestedQueuedHz, + uint32_t *actualFirstHz, + uint32_t *actualQueuedHz); +static PLSR_PLATFORM_QUEUE_RESULT PlsrDiagnosticQueueFrequency( + uint8_t pulseOutput, + uint32_t requestedHz, + uint32_t *actualHz); +static void PlsrDiagnosticCheckActiveFrequency(uint32_t activeHz); +static uint8_t PlsrArmFinalAbBoundaryLocked(void); +static uint8_t PlsrQueueFinalAbBoundaryFromIrq(void); static uint8_t PlsrIsBusy(void) { @@ -266,6 +371,417 @@ static uint16_t PlsrHighWord(uint32_t value) return (uint16_t)(value >> 16U); } +static uint8_t PlsrFinalAbBoundaryRequired(void) +{ + uint8_t finalBoundary; + + if (PlsrActiveConfig.outputMode != PLSR_OUTPUT_AB) + { + return 0U; + } + + finalBoundary = ((PlsrCutRequested != 0U) + || ((PlsrStopRequested != 0U) + && (PlsrStopPulsesRemaining == 1U)) + || ((PlsrRemainingPulses == 1UL) + && (PlsrHandoffPlan.valid == 0U))) ? 1U : 0U; + return ((PlsrPulseActive != 0U) && (finalBoundary != 0U)) ? 1U : 0U; +} + +static uint8_t PlsrCompleteFinalAbArmLocked(void) +{ + PLSR_PLATFORM_STOP_RESULT result; + uint8_t pulseOutput = (uint8_t)PlsrActiveConfig.pulseOutput; + + result = PlsrPlatformRequestStopLocked(pulseOutput, 1U); + if (result == PLSR_PLATFORM_STOP_PENDING) + { + PlsrQueuedFrequencyHz = PlsrCurrentFrequencyHz; + PlsrDiagnosticQueuedExpectedHz = PlsrCurrentFrequencyHz; + PlsrDeferredFrequencyHz = PlsrCurrentFrequencyHz; + PlsrDeferredFrequencyPending = 0U; + PlsrFrequencyUpdatePending = 0U; + PlsrShortProfile.active = 0U; + PlsrHandoffPlan.valid = 0U; + PlsrRamp.active = 0U; + return 1U; + } + PlsrTimerErrorPending = 1U; + PlsrPlatformStopPulse(pulseOutput); + PlsrAbStopArmed = 0U; + PlsrPulseActive = 0U; + PlsrBoundaryFrequencyHz = PlsrCurrentFrequencyHz; + PlsrBoundaryWasCut = (PlsrCutRequested != 0U) ? 1U : 0U; + PlsrCutRequested = 0U; + PlsrCurrentFrequencyHz = 0UL; + PlsrQueuedFrequencyHz = 0UL; + PlsrBoundaryPending = 1U; + return 0U; +} + +static uint8_t PlsrArmFinalAbBoundaryLocked(void) +{ + if (PlsrFinalAbBoundaryRequired() == 0U) + { + return 1U; + } + if (PlsrAbStopArmed != 0U) + { + return 1U; + } + PlsrAbStopArmed = 1U; + return PlsrCompleteFinalAbArmLocked(); +} + +static uint8_t PlsrQueueFinalAbBoundaryFromIrq(void) +{ + uint32_t criticalState; + + if ((PlsrFinalAbBoundaryRequired() == 0U) + || (PlsrAbStopArmed != 0U)) + { + return 1U; + } + PlsrAbStopArmed = 1U; + if (PlsrPlatformQueueFinalArmFromIrq( + (uint8_t)PlsrActiveConfig.pulseOutput) != 0U) + { + return 1U; + } + criticalState = PlsrPlatformEnterCritical(); + if ((PlsrAbStopArmed == 0U) + || (PlsrFinalAbBoundaryRequired() == 0U)) + { + PlsrPlatformExitCritical(criticalState); + return 1U; + } + { + uint8_t result = PlsrCompleteFinalAbArmLocked(); + + PlsrPlatformExitCritical(criticalState); + return result; + } +} + +void PlsrFinalArmJobIrq(uint8_t pulseOutput) +{ + uint32_t criticalState = PlsrPlatformEnterCritical(); + + if ((PlsrAbStopArmed == 0U) || (PlsrPulseActive == 0U) + || (pulseOutput != (uint8_t)PlsrActiveConfig.pulseOutput) + || (PlsrFinalAbBoundaryRequired() == 0U)) + { + if ((PlsrPulseActive != 0U) + && (pulseOutput == (uint8_t)PlsrActiveConfig.pulseOutput)) + { + PlsrAbStopArmed = 0U; + } + PlsrPlatformExitCritical(criticalState); + return; + } + (void)PlsrCompleteFinalAbArmLocked(); + PlsrPlatformExitCritical(criticalState); +} + +static uint32_t PlsrAbsDifferenceU32(uint32_t first, uint32_t second) +{ + return (first >= second) ? (first - second) : (second - first); +} + +static int32_t PlsrDifferenceI32(uint32_t first, uint32_t second) +{ + int64_t difference = (int64_t)first - (int64_t)second; + + if (difference > INT32_MAX) + { + return INT32_MAX; + } + if (difference < INT32_MIN) + { + return INT32_MIN; + } + return (int32_t)difference; +} + +static void PlsrDiagnosticLatch(uint16_t reason) +{ + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_FAULT_LATCHED; + if (PlsrDiagnostic.reason == PLSR_DIAG_REASON_NONE) + { + PlsrDiagnostic.reason = reason; + } +} + +static void PlsrDiagnosticReset(void) +{ + (void)memset((void *)&PlsrDiagnostic, 0, sizeof(PlsrDiagnostic)); + PlsrDiagnostic.firstMismatchSample = 0xFFFFFFFFUL; + PlsrDiagnosticSegmentCounterBase = 0UL; + PlsrDiagnosticQueuedExpectedHz = 0UL; + PlsrDiagnosticFailedChecks = 0U; +} + +static void PlsrDiagnosticBeginSegment(uint8_t segmentNumber, + uint64_t expectedCycles, + uint8_t directionPositive) +{ + if (expectedCycles > 0xFFFFFFFFUL) + { + PlsrDiagnostic.expectedCycles = 0xFFFFFFFFUL; + PlsrDiagnosticLatch(PLSR_DIAG_REASON_INVALID_SAMPLE); + } + else + { + PlsrDiagnostic.expectedCycles = (uint32_t)expectedCycles; + } + PlsrDiagnostic.flags &= (uint16_t)~(PLSR_DIAG_FLAG_COUNT_CHECKED + | PLSR_DIAG_FLAG_COUNT_PASS); + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_MONITORING; + PlsrDiagnostic.lastSegment = segmentNumber; + PlsrDiagnostic.modeDirection = + (uint16_t)(PlsrActiveConfig.outputMode + | ((uint16_t)directionPositive << 8U)); + PlsrDiagnostic.observedCycles = 0UL; + PlsrDiagnostic.countError = 0L; + PlsrDiagnosticSegmentCounterBase = PlsrPlatformObservedPulses( + (uint8_t)PlsrActiveConfig.pulseOutput); +} + +static void PlsrDiagnosticFinishSegment(uint8_t completedNormally) +{ + uint64_t now; + uint64_t observed; + uint32_t observedCycles; + uint32_t expectedCycles; + + if ((PlsrDiagnostic.flags & PLSR_DIAG_FLAG_MONITORING) == 0U) + { + return; + } +#ifdef PLSR_HOST_TEST + PlsrHostTestEventSequence++; + PlsrHostTestLastDiagnosticFinishEvent = PlsrHostTestEventSequence; +#endif + now = PlsrPlatformObservedPulses( + (uint8_t)PlsrActiveConfig.pulseOutput); + observed = (now >= PlsrDiagnosticSegmentCounterBase) + ? (now - PlsrDiagnosticSegmentCounterBase) : 0UL; + if (observed > 0xFFFFFFFFUL) + { + PlsrDiagnostic.observedCycles = 0xFFFFFFFFUL; + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_COUNT_PASS; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_COUNT_PASS; + PlsrDiagnosticLatch(PLSR_DIAG_REASON_INVALID_SAMPLE); + } + else + { + PlsrDiagnostic.observedCycles = (uint32_t)observed; + } + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_MONITORING; + if (completedNormally == 0U) + { + PlsrDiagnostic.countError = 0L; + PlsrDiagnostic.flags &= (uint16_t)~(PLSR_DIAG_FLAG_COUNT_CHECKED + | PLSR_DIAG_FLAG_COUNT_PASS); + return; + } + + observedCycles = PlsrDiagnostic.observedCycles; + expectedCycles = PlsrDiagnostic.expectedCycles; + PlsrDiagnostic.countError = + PlsrDifferenceI32(observedCycles, expectedCycles); + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_COUNT_CHECKED; + if (PlsrDiagnostic.countError != 0L) + { + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_COUNT_PASS; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_COUNT_PASS; + PlsrDiagnosticLatch(PLSR_DIAG_REASON_COUNT); + } + else if ((PlsrDiagnosticFailedChecks & PLSR_DIAG_FLAG_COUNT_PASS) == 0U) + { + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_COUNT_PASS; + } +} + +static void PlsrDiagnosticRecordFrequency(uint32_t requestedHz, + uint32_t expectedHz, + uint32_t actualHz) +{ + uint32_t error = PlsrAbsDifferenceU32(actualHz, expectedHz); + + PlsrDiagnostic.requestedHz = requestedHz; + PlsrDiagnostic.expectedTimerHz = expectedHz; + PlsrDiagnostic.activeTimerHz = actualHz; + /* Request error is divider quantization, not a diagnostic deviation. */ + PlsrDiagnostic.requestErrorHz = PlsrDifferenceI32(expectedHz, requestedHz); + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_FREQUENCY_CHECKED; + if (actualHz != expectedHz) + { + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_FREQUENCY_PASS; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_FREQUENCY_PASS; + PlsrDiagnosticLatch(PLSR_DIAG_REASON_FREQUENCY); + } + else if ((PlsrDiagnosticFailedChecks + & PLSR_DIAG_FLAG_FREQUENCY_PASS) == 0U) + { + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_FREQUENCY_PASS; + } + if (error > PlsrDiagnostic.curveMaxAbsErrorHz) + { + PlsrDiagnostic.curveMaxAbsErrorHz = error; + } +} + +static void PlsrDiagnosticRecordCurveSample(uint32_t expectedHz, + uint32_t actualHz) +{ + uint32_t error = PlsrAbsDifferenceU32(expectedHz, actualHz); + + if (PlsrDiagnostic.curveSampleCount != 0xFFFFFFFFUL) + { + PlsrDiagnostic.curveSampleCount++; + } + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_CURVE_CHECKED; + if (error == 0UL) + { + if ((PlsrDiagnosticFailedChecks & PLSR_DIAG_FLAG_CURVE_PASS) == 0U) + { + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_CURVE_PASS; + } + } + else + { + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_CURVE_PASS; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_CURVE_PASS; + if (PlsrDiagnostic.curveMismatchCount != 0xFFFFFFFFUL) + { + PlsrDiagnostic.curveMismatchCount++; + } + if (PlsrDiagnostic.firstMismatchSample == 0xFFFFFFFFUL) + { + PlsrDiagnostic.firstMismatchSample = + PlsrDiagnostic.curveSampleCount; + } + if (error > PlsrDiagnostic.curveMaxAbsErrorHz) + { + PlsrDiagnostic.curveMaxAbsErrorHz = error; + } + PlsrDiagnosticLatch(PLSR_DIAG_REASON_CURVE); + } +} + +static uint8_t PlsrDiagnosticStartPulse(uint8_t pulseOutput, + uint32_t requestedFirstHz, + uint32_t requestedQueuedHz, + uint32_t *actualFirstHz, + uint32_t *actualQueuedHz) +{ + PLSR_PLATFORM_TIMER_SETTING firstSetting; + PLSR_PLATFORM_TIMER_SETTING queuedSetting; + + if ((PlsrPlatformBuildTimerSetting( + pulseOutput, (uint8_t)PlsrActiveConfig.outputMode, + requestedFirstHz, &firstSetting) == 0U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, (uint8_t)PlsrActiveConfig.outputMode, + requestedQueuedHz, &queuedSetting) == 0U) + || (PlsrPlatformStartPrepared(pulseOutput, &firstSetting, + &queuedSetting, actualFirstHz, + actualQueuedHz) == 0U)) + { + PlsrDiagnosticFinishSegment(0U); + return 0U; + } + PlsrDiagnosticRecordFrequency(requestedFirstHz, + firstSetting.actualFrequencyHz, + *actualFirstHz); + PlsrDiagnosticRecordCurveSample(firstSetting.actualFrequencyHz, + *actualFirstHz); + PlsrDiagnosticQueuedExpectedHz = queuedSetting.actualFrequencyHz; + return 1U; +} + +static PLSR_PLATFORM_QUEUE_RESULT PlsrDiagnosticQueueFrequency( + uint8_t pulseOutput, + uint32_t requestedHz, + uint32_t *actualHz) +{ + uint32_t expectedHz; + PLSR_PLATFORM_QUEUE_RESULT result; + + if (PlsrPlatformExpectedFrequency( + pulseOutput, (uint8_t)PlsrActiveConfig.outputMode, + requestedHz, &expectedHz) == 0U) + { + PlsrDiagnosticFinishSegment(0U); + return PLSR_PLATFORM_QUEUE_FAILED; + } + result = PlsrPlatformQueueFrequency(pulseOutput, requestedHz, actualHz); + if (result == PLSR_PLATFORM_QUEUE_FAILED) + { + PlsrDiagnosticFinishSegment(0U); + return result; + } + if (result == PLSR_PLATFORM_QUEUE_STALE) + { + return result; + } + + PlsrDiagnosticRecordFrequency(requestedHz, expectedHz, *actualHz); + PlsrDiagnosticQueuedExpectedHz = expectedHz; + return PLSR_PLATFORM_QUEUE_APPLIED; +} + +static void PlsrDiagnosticCheckActiveFrequency(uint32_t activeHz) +{ + uint16_t platformFault = PlsrPlatformDiagnosticFault(); + uint32_t observedHz = activeHz; + + if (platformFault == PLSR_DIAG_REASON_FREQUENCY) + { + observedHz = PlsrPlatformActiveFrequency( + (uint8_t)PlsrActiveConfig.pulseOutput); + if (observedHz == 0UL) + { + observedHz = activeHz; + } + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_FREQUENCY_PASS; + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_FREQUENCY_CHECKED; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_FREQUENCY_PASS; + PlsrDiagnosticLatch(PLSR_DIAG_REASON_FREQUENCY); + } + if ((platformFault != PLSR_DIAG_REASON_NONE) + && (PlsrDiagnosticQueuedExpectedHz != 0UL)) + { + PlsrDiagnostic.activeTimerHz = observedHz; + if (platformFault == PLSR_DIAG_REASON_CURVE) + { + if (PlsrDiagnostic.curveSampleCount != 0xFFFFFFFFUL) + { + PlsrDiagnostic.curveSampleCount++; + } + PlsrDiagnostic.flags |= PLSR_DIAG_FLAG_CURVE_CHECKED; + PlsrDiagnostic.flags &= (uint16_t)~PLSR_DIAG_FLAG_CURVE_PASS; + PlsrDiagnosticFailedChecks |= PLSR_DIAG_FLAG_CURVE_PASS; + if (PlsrDiagnostic.curveMismatchCount != 0xFFFFFFFFUL) + { + PlsrDiagnostic.curveMismatchCount++; + } + if (PlsrDiagnostic.firstMismatchSample == 0xFFFFFFFFUL) + { + PlsrDiagnostic.firstMismatchSample = + PlsrDiagnostic.curveSampleCount; + } + PlsrDiagnosticLatch(PLSR_DIAG_REASON_CURVE); + } + else if (platformFault == PLSR_DIAG_REASON_FREQUENCY) + { + PlsrDiagnosticRecordCurveSample(PlsrDiagnosticQueuedExpectedHz, + observedHz); + } + } +} + static void PlsrSetDefaults(PLSR_CONFIG *config) { uint8_t index; @@ -287,6 +803,7 @@ static void PlsrSetDefaults(PLSR_CONFIG *config) config->stopSpeedHz = 100UL; config->accelerationTimeMs = 100U; config->decelerationTimeMs = 100U; + config->outputMode = PLSR_OUTPUT_PULSE_DIR; for (index = 0U; index < PLSR_SEGMENT_COUNT_MAX; index++) { @@ -310,6 +827,9 @@ static uint8_t PlsrConfigIsValid(const PLSR_CONFIG *config, || (config->directionNegativeLogic > 1U) || (config->curveMode > 2U) || (config->positionMode > PLSR_POSITION_ABSOLUTE) + || (config->outputMode > PLSR_OUTPUT_AB) + || ((config->outputMode == PLSR_OUTPUT_AB) + && ((config->pulseOutput & 1U) != 0U)) || (config->segmentCount == 0U) || (config->segmentCount > PLSR_SEGMENT_COUNT_MAX) || (config->startSegment == 0U) @@ -549,9 +1069,13 @@ static uint8_t PlsrAddressIsProduct(uint16_t address) { return (((address >= PLSR_CONFIG_FIRST_ADDRESS) && (address <= PLSR_CONFIG_LAST_ADDRESS)) + || (address == PLSR_OUTPUT_MODE_ADDRESS) || ((address >= PLSR_STATUS_FIRST_ADDRESS) && (address <= PLSR_STATUS_LAST_ADDRESS)) - || (address == PLSR_CONTROL_ADDRESS)) ? 1U : 0U; + || ((address >= PLSR_DIAGNOSTIC_FIRST_ADDRESS) + && (address <= PLSR_DIAGNOSTIC_LAST_ADDRESS)) + || (address == PLSR_CONTROL_ADDRESS) + || (address == PLSR_DIAGNOSTIC_CONTROL_ADDRESS)) ? 1U : 0U; } static PLSR_MB_RESULT PlsrClassifyRange(uint16_t startAddress, @@ -718,6 +1242,11 @@ static uint8_t PlsrApplyFrequencyPair(uint32_t requestedFirstFrequencyHz, if (PlsrPulseActive != 0U) { + if (PlsrAbStopArmed != 0U) + { + PlsrPlatformExitCritical(criticalState); + return 1U; + } if (PlsrHandoffPlan.valid != 0U) { PlsrPlatformExitCritical(criticalState); @@ -735,11 +1264,10 @@ static uint8_t PlsrApplyFrequencyPair(uint32_t requestedFirstFrequencyHz, hardwareQueuedFrequencyHz = candidatePlan.firstFrequencyHz; haveCandidatePlan = 1U; } - if (PlsrPlatformStartPulse((uint8_t)PlsrActiveConfig.pulseOutput, - hardwareFirstFrequencyHz, - hardwareQueuedFrequencyHz, - &actualFirstFrequencyHz, - &actualQueuedFrequencyHz) == 0U) + if (PlsrDiagnosticStartPulse( + (uint8_t)PlsrActiveConfig.pulseOutput, + hardwareFirstFrequencyHz, hardwareQueuedFrequencyHz, + &actualFirstFrequencyHz, &actualQueuedFrequencyHz) == 0U) { PlsrPlatformExitCritical(criticalState); return 0U; @@ -751,6 +1279,14 @@ static uint8_t PlsrApplyFrequencyPair(uint32_t requestedFirstFrequencyHz, { PlsrHandoffPlan.magnitude = candidatePlan.magnitude; PlsrHandoffPlan.firstFrequencyHz = actualQueuedFrequencyHz; + PlsrHandoffPlan.secondFrequencyHz = + candidatePlan.secondFrequencyHz; + PlsrHandoffPlan.firstRequestedFrequencyHz = + candidatePlan.firstRequestedFrequencyHz; + PlsrHandoffPlan.secondRequestedFrequencyHz = + candidatePlan.secondRequestedFrequencyHz; + PlsrHandoffPlan.firstSetting = candidatePlan.firstSetting; + PlsrHandoffPlan.secondSetting = candidatePlan.secondSetting; PlsrCopyShortProfile(&PlsrHandoffPlan.profile, &candidatePlan.profile); PlsrHandoffPlan.nextSegment = candidatePlan.nextSegment; @@ -760,6 +1296,11 @@ static uint8_t PlsrApplyFrequencyPair(uint32_t requestedFirstFrequencyHz, } PlsrQueuedFrequencyHz = actualQueuedFrequencyHz; + if (PlsrArmFinalAbBoundaryLocked() == 0U) + { + PlsrPlatformExitCritical(criticalState); + return 0U; + } PlsrPlatformExitCritical(criticalState); return 1U; } @@ -788,24 +1329,31 @@ static uint8_t PlsrStopDrainPulseCount(void) return (currentFrequencyHz == queuedFrequencyHz) ? 1U : 2U; } -static uint8_t PlsrCommitDeferredFrequency(uint8_t pulseOutput) +static PLSR_PLATFORM_QUEUE_RESULT PlsrCommitDeferredFrequency( + uint8_t pulseOutput) { uint32_t requestedFrequencyHz; uint32_t actualFrequencyHz; + PLSR_PLATFORM_QUEUE_RESULT result; if (PlsrDeferredFrequencyPending == 0U) { - return 1U; + return PLSR_PLATFORM_QUEUE_APPLIED; } requestedFrequencyHz = PlsrDeferredFrequencyHz; - PlsrDeferredFrequencyPending = 0U; - if (PlsrPlatformQueueFrequency(pulseOutput, requestedFrequencyHz, - &actualFrequencyHz) == 0U) + result = PlsrDiagnosticQueueFrequency(pulseOutput, requestedFrequencyHz, + &actualFrequencyHz); + if (result != PLSR_PLATFORM_QUEUE_APPLIED) { - return 0U; + return result; + } + if ((PlsrDeferredFrequencyPending != 0U) + && (PlsrDeferredFrequencyHz == requestedFrequencyHz)) + { + PlsrDeferredFrequencyPending = 0U; } PlsrQueuedFrequencyHz = actualFrequencyHz; - return 1U; + return PLSR_PLATFORM_QUEUE_APPLIED; } static uint8_t PlsrRampAdvance(uint32_t expectedEpoch) @@ -869,6 +1417,7 @@ static uint8_t PlsrRampAdvance(uint32_t expectedEpoch) else { PlsrStopPulsesRemaining = PlsrStopDrainPulseCount(); + (void)PlsrArmFinalAbBoundaryLocked(); } } PlsrPlatformExitCritical(criticalState); @@ -948,12 +1497,26 @@ static uint64_t PlsrRemainingSnapshot(void) return remaining; } -static uint64_t PlsrRampPulseEstimate(uint32_t fromHz, uint32_t toHz) +static uint64_t PlsrRampPulseEstimate(uint32_t fromHz, + uint32_t toHz, + uint32_t rateBoundHz) { uint32_t duration = PlsrRampDurationMs(fromHz, toHz); uint64_t sum = (uint64_t)fromHz + toHz; + uint64_t estimate = (sum * duration + 1999UL) / 2000UL + 2UL; + uint64_t reserve = ((uint64_t)rateBoundHz + 999UL) / 1000UL; + + if ((duration != 0UL) && (fromHz > toHz)) + { + /* A 1 ms held deceleration step can exceed the ideal ramp area. */ + reserve += ((uint64_t)(fromHz - toHz) + 999UL) / 1000UL; + } + if (UINT64_MAX - estimate < reserve) + { + return UINT64_MAX; + } - return (sum * duration + 1999UL) / 2000UL + 2UL; + return estimate + reserve; } static uint16_t PlsrShortProfileRampTime(uint32_t fromHz, uint32_t toHz) @@ -1829,44 +2392,207 @@ static void PlsrCopyShortProfile(PLSR_SHORT_PROFILE *destination, destination->active = source->active; } -static void PlsrInvalidateHandoffPlans(void) +static uint16_t PlsrProfileQueueCount(void) +{ + uint32_t writeIndex = PlsrProfileQueue.writeIndex; + uint32_t readIndex = PlsrProfileQueue.readIndex; + + return (uint16_t)(writeIndex - readIndex); +} + +static void PlsrProfileQueueReset(void) { - uint8_t bank; - uint8_t index; uint32_t criticalState = PlsrPlatformEnterCritical(); - PlsrHandoffPlan.valid = 0U; - for (bank = 0U; bank < 2U; bank++) - { - for (index = 0U; index < PLSR_SEGMENT_COUNT_MAX; index++) - { - PlsrPreparedHandoffPlans[bank][index].valid = 0U; - } + PlsrProfileQueue.generation++; + PlsrProfileQueue.readIndex = 0U; + PlsrProfileQueue.writeIndex = 0U; + PlsrProfileQueue.active = 0U; + PlsrProfileQueue.generatorComplete = 0U; + PlsrProfileQueue.producerEpoch = 0UL; + PlsrProfileQueue.producerSegment = 0U; + PlsrProfileQueue.preparedHandoffBank = 0U; + PlsrProfileQueue.producerProfile.active = 0U; + PlsrPlatformExitCritical(criticalState); +} + +static uint8_t PlsrProfileQueueBegin( + const PLSR_SHORT_PROFILE *producerProfile, + uint32_t producerEpoch, + uint8_t producerSegment, + uint8_t preparedHandoffBank) +{ + uint32_t criticalState = PlsrPlatformEnterCritical(); + + PlsrProfileQueue.generation++; + PlsrProfileQueue.readIndex = 0U; + PlsrProfileQueue.writeIndex = 0U; + PlsrProfileQueue.producerEpoch = producerEpoch; + PlsrProfileQueue.producerSegment = producerSegment; + PlsrProfileQueue.preparedHandoffBank = preparedHandoffBank; + PlsrProfileQueue.generatorComplete = 0U; + PlsrCopyShortProfile(&PlsrProfileQueue.producerProfile, + producerProfile); + PlsrProfileQueue.active = + ((producerProfile->active != 0U) + && (producerProfile->nextPeriod < producerProfile->pulseCount)) + ? 1U : 0U; + if (PlsrProfileQueue.active == 0U) + { + PlsrProfileQueue.generatorComplete = 1U; } PlsrPlatformExitCritical(criticalState); + return 1U; } -static uint8_t PlsrAdvanceShortProfile(uint8_t pulseOutput) +static void PlsrProfileQueueInvalidateGeneration(void) { - uint32_t requestedFrequencyHz; - uint32_t actualFrequencyHz; + uint32_t criticalState = PlsrPlatformEnterCritical(); - if ((PlsrShortProfile.active == 0U) - || (PlsrShortProfile.nextPeriod >= PlsrShortProfile.pulseCount)) + PlsrProfileQueue.generation++; + PlsrProfileQueue.active = 0U; + PlsrProfileQueue.generatorComplete = 0U; + PlsrProfileQueue.readIndex = 0U; + PlsrProfileQueue.writeIndex = 0U; + PlsrPlatformExitCritical(criticalState); +} + +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) \ + && !defined(PLSR_HOST_TEST) +static uint32_t PlsrProfileTimingNow(void) +{ + return *((volatile uint32_t *)0xE0001004UL); +} + +static void PlsrProfileRecordProducerCycles(uint32_t startCycles) +{ + uint32_t elapsed = PlsrProfileTimingNow() - startCycles; + uint32_t total = PlsrProfileProducerTotalCycles; + + if (PlsrProfileProducerItemCount != 0xFFFFFFFFUL) { - return 1U; + PlsrProfileProducerItemCount++; } + PlsrProfileProducerTotalCycles = + (elapsed > (0xFFFFFFFFUL - total)) ? 0xFFFFFFFFUL + : total + elapsed; + if (elapsed > PlsrProfileProducerMaxItemCycles) + { + PlsrProfileProducerMaxItemCycles = elapsed; + } +} +#endif - requestedFrequencyHz = - PlsrShortProfileTakeFrequency(&PlsrShortProfile); - PlsrDeferredFrequencyPending = 0U; - if (PlsrPlatformQueueFrequency(pulseOutput, - requestedFrequencyHz, - &actualFrequencyHz) == 0U) +static uint8_t PlsrProfileQueueFill(void) +{ + PLSR_SHORT_PROFILE candidate; + PLSR_PROFILE_ENTRY entry; + uint32_t generation; + uint32_t producerEpoch; + uint32_t criticalState; + uint32_t writeIndex; +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) \ + && !defined(PLSR_HOST_TEST) + uint32_t startCycles; +#endif + + while (1) { - return 0U; + criticalState = PlsrPlatformEnterCritical(); + if ((PlsrProfileQueue.active == 0U) + || (PlsrProfileQueue.generatorComplete != 0U) + || (PlsrProfileQueueCount() >= PLSR_PROFILE_QUEUE_CAPACITY)) + { + PlsrPlatformExitCritical(criticalState); + return 1U; + } + generation = PlsrProfileQueue.generation; + producerEpoch = PlsrProfileQueue.producerEpoch; + PlsrCopyShortProfile(&candidate, + &PlsrProfileQueue.producerProfile); + PlsrPlatformExitCritical(criticalState); + +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) \ + && !defined(PLSR_HOST_TEST) + startCycles = PlsrProfileTimingNow(); +#endif + entry.requestedFrequencyHz = + PlsrShortProfileTakeFrequency(&candidate); + if (PlsrPlatformBuildTimerSetting( + (uint8_t)PlsrActiveConfig.pulseOutput, + (uint8_t)PlsrActiveConfig.outputMode, + entry.requestedFrequencyHz, &entry.setting) == 0U) + { + return 0U; + } + + criticalState = PlsrPlatformEnterCritical(); + if ((PlsrProfileQueue.active == 0U) + || (PlsrProfileQueue.generation != generation) + || (PlsrProfileQueue.producerEpoch != producerEpoch) + || (PlsrProfileQueueCount() >= PLSR_PROFILE_QUEUE_CAPACITY)) + { + PlsrPlatformExitCritical(criticalState); + continue; + } + writeIndex = PlsrProfileQueue.writeIndex; + PlsrProfileQueue.entries[writeIndex & PLSR_PROFILE_QUEUE_MASK] = entry; + PlsrCopyShortProfile(&PlsrProfileQueue.producerProfile, &candidate); + PlsrProfileQueue.writeIndex = writeIndex + 1UL; + if ((candidate.active == 0U) + || (candidate.nextPeriod >= candidate.pulseCount)) + { + PlsrProfileQueue.generatorComplete = 1U; + } + PlsrPlatformExitCritical(criticalState); +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) \ + && !defined(PLSR_HOST_TEST) + PlsrProfileRecordProducerCycles(startCycles); +#endif } +} + +static PLSR_PLATFORM_QUEUE_RESULT PlsrProfileQueueCommitNext( + uint8_t pulseOutput) +{ + const PLSR_PROFILE_ENTRY *entry; + uint32_t readIndex; + uint32_t nextReadIndex; + uint32_t writeIndex; + uint32_t actualFrequencyHz; + PLSR_PLATFORM_QUEUE_RESULT result; + + if (PlsrProfileQueue.active == 0U) + { + return PLSR_PLATFORM_QUEUE_APPLIED; + } + readIndex = PlsrProfileQueue.readIndex; + if (readIndex == PlsrProfileQueue.writeIndex) + { + if (PlsrProfileQueue.generatorComplete != 0U) + { + PlsrProfileQueue.active = 0U; + PlsrShortProfile.active = 0U; + return PLSR_PLATFORM_QUEUE_APPLIED; + } + return PLSR_PLATFORM_QUEUE_FAILED; + } + + entry = &PlsrProfileQueue.entries[readIndex & PLSR_PROFILE_QUEUE_MASK]; + result = PlsrPlatformLoadPreparedFromIrq(pulseOutput, &entry->setting, + &actualFrequencyHz); + if (result != PLSR_PLATFORM_QUEUE_APPLIED) + { + return result; + } + nextReadIndex = readIndex + 1UL; + PlsrProfileQueue.readIndex = nextReadIndex; + PlsrDeferredFrequencyPending = 0U; PlsrQueuedFrequencyHz = actualFrequencyHz; + PlsrDiagnosticRecordFrequency(entry->requestedFrequencyHz, + entry->setting.actualFrequencyHz, + actualFrequencyHz); + PlsrDiagnosticQueuedExpectedHz = entry->setting.actualFrequencyHz; if (actualFrequencyHz > PlsrCurrentFrequencyHz) { PlsrRunStatus = PLSR_STATUS_ACCELERATING; @@ -1879,7 +2605,30 @@ static uint8_t PlsrAdvanceShortProfile(uint8_t pulseOutput) { PlsrRunStatus = PLSR_STATUS_RUNNING; } - return 1U; + writeIndex = PlsrProfileQueue.writeIndex; + if ((nextReadIndex == writeIndex) + && (PlsrProfileQueue.generatorComplete != 0U)) + { + PlsrProfileQueue.active = 0U; + } + return PLSR_PLATFORM_QUEUE_APPLIED; +} + +static void PlsrInvalidateHandoffPlans(void) +{ + uint8_t bank; + uint8_t index; + uint32_t criticalState = PlsrPlatformEnterCritical(); + + PlsrHandoffPlan.valid = 0U; + for (bank = 0U; bank < 2U; bank++) + { + for (index = 0U; index < PLSR_SEGMENT_COUNT_MAX; index++) + { + PlsrPreparedHandoffPlans[bank][index].valid = 0U; + } + } + PlsrPlatformExitCritical(criticalState); } static void PlsrMaybePlanBoundaryRamp(uint32_t expectedEpoch) @@ -1890,7 +2639,13 @@ static void PlsrMaybePlanBoundaryRamp(uint32_t expectedEpoch) uint8_t hasNext; uint32_t targetHz; uint32_t criticalState; + uint32_t currentHz; + uint32_t queuedHz; + uint32_t deferredHz; + uint32_t rateBoundHz; + uint8_t deferredPending; uint64_t estimate; + uint64_t candidateEstimate; uint64_t remaining; if ((PlsrPulseActive == 0U) || (PlsrBoundaryRampStarted != 0U) @@ -1916,7 +2671,47 @@ static void PlsrMaybePlanBoundaryRamp(uint32_t expectedEpoch) } } - estimate = PlsrRampPulseEstimate(PlsrCurrentFrequencyHz, targetHz); + criticalState = PlsrPlatformEnterCritical(); + currentHz = PlsrCurrentFrequencyHz; + queuedHz = PlsrQueuedFrequencyHz; + deferredHz = PlsrDeferredFrequencyHz; + deferredPending = PlsrDeferredFrequencyPending; + if ((PlsrSegmentEpoch != expectedEpoch) + || (PlsrBoundaryPending != 0U) + || (PlsrPulseActive == 0U) + || (PlsrBoundaryRampStarted != 0U) + || (PlsrShortProfile.active != 0U) + || (PlsrHandoffPlan.valid != 0U) + || (PlsrStopRequested != 0U) + || (PlsrAbStopArmed != 0U)) + { + PlsrPlatformExitCritical(criticalState); + return; + } + PlsrPlatformExitCritical(criticalState); + + rateBoundHz = (currentHz > queuedHz) ? currentHz : queuedHz; + if ((deferredPending != 0U) && (deferredHz > rateBoundHz)) + { + rateBoundHz = deferredHz; + } + estimate = PlsrRampPulseEstimate(currentHz, targetHz, rateBoundHz); + candidateEstimate = PlsrRampPulseEstimate(queuedHz, targetHz, + rateBoundHz); + if (candidateEstimate > estimate) + { + estimate = candidateEstimate; + } + if (deferredPending != 0U) + { + candidateEstimate = PlsrRampPulseEstimate(deferredHz, targetHz, + rateBoundHz); + if (candidateEstimate > estimate) + { + estimate = candidateEstimate; + } + } + criticalState = PlsrPlatformEnterCritical(); remaining = PlsrRemainingPulses; if ((PlsrSegmentEpoch != expectedEpoch) @@ -1925,7 +2720,8 @@ static void PlsrMaybePlanBoundaryRamp(uint32_t expectedEpoch) || (PlsrBoundaryRampStarted != 0U) || (PlsrShortProfile.active != 0U) || (PlsrHandoffPlan.valid != 0U) - || (PlsrStopRequested != 0U)) + || (PlsrStopRequested != 0U) + || (PlsrAbStopArmed != 0U)) { PlsrPlatformExitCritical(criticalState); return; @@ -1951,6 +2747,9 @@ static uint8_t PlsrBeginSegmentOutput(uint32_t startFrequencyHz) PlsrActiveConfig.segments[PlsrCurrentSegment - 1U].frequencyHz; uint32_t firstFrequencyHz; uint32_t secondFrequencyHz; + uint32_t profileEpoch; + uint8_t profileSegment; + uint8_t profileHandoffBank; PlsrSegmentClockStarted = 1U; PlsrSegmentElapsedMs = 0UL; @@ -1966,6 +2765,19 @@ static uint8_t PlsrBeginSegmentOutput(uint32_t startFrequencyHz) (PlsrShortProfile.nextPeriod < PlsrShortProfile.pulseCount) ? PlsrShortProfileTakeFrequency(&PlsrShortProfile) : firstFrequencyHz; + profileEpoch = PlsrSegmentEpoch; + profileSegment = PlsrCurrentSegment; + profileHandoffBank = PlsrPreparedHandoffBank; + (void)PlsrProfileQueueBegin(&PlsrShortProfile, + profileEpoch, + profileSegment, + profileHandoffBank); + if (PlsrProfileQueueFill() == 0U) + { + PlsrProfileQueueReset(); + PlsrShortProfile.active = 0U; + return 0U; + } if (secondFrequencyHz > firstFrequencyHz) { PlsrRunStatus = PLSR_STATUS_ACCELERATING; @@ -1982,12 +2794,15 @@ static uint8_t PlsrBeginSegmentOutput(uint32_t startFrequencyHz) secondFrequencyHz, PlsrSegmentEpoch) == 0U) { + PlsrProfileQueueReset(); PlsrShortProfile.active = 0U; return 0U; } return 1U; } + PlsrProfileQueueReset(); + PlsrRampStart(startFrequencyHz, targetFrequencyHz); if (PlsrRamp.active == 0U) @@ -2004,6 +2819,10 @@ static uint8_t PlsrBeginSegmentOutput(uint32_t startFrequencyHz) { return 0U; } + if (PlsrPrepareFutureHandoffQueue() == 0U) + { + return 0U; + } return 1U; } @@ -2044,6 +2863,7 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, PlsrBoundaryWasCut = 0U; PlsrCutRequested = 0U; PlsrStopPulsesRemaining = 0U; + PlsrAbStopArmed = 0U; PlsrFrequencyUpdatePending = 0U; PlsrDeferredFrequencyPending = 0U; PlsrCurrentFrequencyHz = 0UL; @@ -2051,6 +2871,12 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, PlsrHandoffPlan.valid = 0U; PlsrShortProfile.active = 0U; PlsrShortProfile.nextPeriod = 0U; + if ((allowCarry == 0U) || (PlsrProfileQueue.active == 0U) + || (PlsrProfileQueue.producerEpoch != PlsrSegmentEpoch) + || (PlsrProfileQueue.producerSegment != segmentNumber)) + { + PlsrProfileQueueReset(); + } PlsrDirectionDelayActive = 0U; PlsrDirectionDelayRemainingMs = 0U; PlsrExtEdgePending = 0U; @@ -2071,6 +2897,8 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, PlsrBoundaryFrequencyHz = (allowCarry != 0U) ? carryFrequencyHz : 0UL; PlsrBoundaryWasCut = 1U; PlsrBoundaryPending = 1U; + PlsrDiagnosticBeginSegment(segmentNumber, 0UL, positive); + PlsrDiagnosticFinishSegment(1U); return 1U; } @@ -2080,11 +2908,14 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, PlsrRunStatus = PLSR_STATUS_RUNNING; PlsrBoundaryFrequencyHz = 0UL; PlsrBoundaryPending = 1U; + PlsrDiagnosticBeginSegment(segmentNumber, 0UL, positive); + PlsrDiagnosticFinishSegment(1U); return 1U; } directionLevel = positive; - if (PlsrActiveConfig.directionNegativeLogic != 0U) + if ((PlsrActiveConfig.outputMode == PLSR_OUTPUT_PULSE_DIR) + && (PlsrActiveConfig.directionNegativeLogic != 0U)) { directionLevel ^= 1U; } @@ -2095,10 +2926,13 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, if (PlsrPlatformPrepare((uint8_t)PlsrActiveConfig.pulseOutput, (uint8_t)PlsrActiveConfig.directionOutput, - directionLevel) == 0U) + directionLevel, + (uint8_t)PlsrActiveConfig.outputMode, + positive) == 0U) { return 0U; } + PlsrDiagnosticBeginSegment(segmentNumber, magnitude, positive); PlsrLastDirectionValid = 1U; PlsrLastDirectionOutput = (uint8_t)PlsrActiveConfig.directionOutput; PlsrLastDirectionLevel = directionLevel; @@ -2113,7 +2947,8 @@ static uint8_t PlsrStartSegment(uint8_t segmentNumber, startFrequencyHz = PlsrActiveConfig.startSpeedHz; } - if ((directionChanged != 0U) + if ((PlsrActiveConfig.outputMode == PLSR_OUTPUT_PULSE_DIR) + && (directionChanged != 0U) && (PlsrActiveConfig.directionDelayMs != 0U)) { PlsrDirectionDelayActive = 1U; @@ -2181,9 +3016,11 @@ static void PlsrFinishCompleted(void) PlsrExtEdgePending = 0U; PlsrStopRequested = 0U; PlsrStopPulsesRemaining = 0U; + PlsrAbStopArmed = 0U; PlsrSeamlessHandoffPending = 0U; PlsrDeferredFrequencyPending = 0U; PlsrShortProfile.active = 0U; + PlsrProfileQueueReset(); PlsrHandoffPlan.valid = 0U; PlsrTimerErrorPending = 0U; PlsrRamp.active = 0U; @@ -2196,6 +3033,7 @@ static void PlsrFinishCompleted(void) static void PlsrFinishStopped(void) { + PlsrDiagnosticFinishSegment(0U); PlsrPlatformStopPulse((uint8_t)PlsrActiveConfig.pulseOutput); PlsrRemainingPulses = 0UL; PlsrPulseActive = 0U; @@ -2211,9 +3049,11 @@ static void PlsrFinishStopped(void) PlsrExtEdgePending = 0U; PlsrStopRequested = 0U; PlsrStopPulsesRemaining = 0U; + PlsrAbStopArmed = 0U; PlsrSeamlessHandoffPending = 0U; PlsrDeferredFrequencyPending = 0U; PlsrShortProfile.active = 0U; + PlsrProfileQueueReset(); PlsrHandoffPlan.valid = 0U; PlsrTimerErrorPending = 0U; PlsrRamp.active = 0U; @@ -2226,6 +3066,7 @@ static void PlsrFinishStopped(void) static void PlsrEnterError(PLSR_ERROR error) { + PlsrDiagnosticFinishSegment(0U); PlsrPlatformStopPulse((uint8_t)PlsrActiveConfig.pulseOutput); PlsrRemainingPulses = 0UL; PlsrPulseActive = 0U; @@ -2241,9 +3082,11 @@ static void PlsrEnterError(PLSR_ERROR error) PlsrExtEdgePending = 0U; PlsrStopRequested = 0U; PlsrStopPulsesRemaining = 0U; + PlsrAbStopArmed = 0U; PlsrSeamlessHandoffPending = 0U; PlsrDeferredFrequencyPending = 0U; PlsrShortProfile.active = 0U; + PlsrProfileQueueReset(); PlsrHandoffPlan.valid = 0U; PlsrTimerErrorPending = 0U; PlsrRamp.active = 0U; @@ -2333,6 +3176,28 @@ static uint8_t PlsrBuildHandoffPlan(uint8_t sourceSegment, plan->firstFrequencyHz = PlsrShortProfileTakeFrequency(&plan->profile); } + plan->secondFrequencyHz = plan->firstFrequencyHz; + if ((plan->profile.active != 0U) + && (plan->profile.nextPeriod < plan->profile.pulseCount)) + { + plan->secondFrequencyHz = + PlsrShortProfileTakeFrequency(&plan->profile); + } + plan->firstRequestedFrequencyHz = plan->firstFrequencyHz; + plan->secondRequestedFrequencyHz = plan->secondFrequencyHz; + if ((PlsrPlatformBuildTimerSetting( + (uint8_t)PlsrActiveConfig.pulseOutput, + (uint8_t)PlsrActiveConfig.outputMode, + plan->firstFrequencyHz, &plan->firstSetting) == 0U) + || (PlsrPlatformBuildTimerSetting( + (uint8_t)PlsrActiveConfig.pulseOutput, + (uint8_t)PlsrActiveConfig.outputMode, + plan->secondFrequencyHz, &plan->secondSetting) == 0U)) + { + return 0U; + } + plan->firstFrequencyHz = plan->firstSetting.actualFrequencyHz; + plan->secondFrequencyHz = plan->secondSetting.actualFrequencyHz; plan->nextSegment = nextSegment; plan->positive = positive; plan->valid = 1U; @@ -2377,6 +3242,7 @@ static uint8_t PlsrSelectPreparedHandoffPlan(PLSR_HANDOFF_PLAN *plan) || (PlsrStopRequested != 0U) || (PlsrCountOverflowPending != 0U) || (PlsrCutRequested != 0U) + || (PlsrAbStopArmed != 0U) || (currentSegment == 0U) || (currentSegment > PlsrActiveConfig.segmentCount)) { @@ -2392,6 +3258,11 @@ static uint8_t PlsrSelectPreparedHandoffPlan(PLSR_HANDOFF_PLAN *plan) plan->magnitude = prepared->magnitude; plan->firstFrequencyHz = prepared->firstFrequencyHz; + plan->secondFrequencyHz = prepared->secondFrequencyHz; + plan->firstRequestedFrequencyHz = prepared->firstRequestedFrequencyHz; + plan->secondRequestedFrequencyHz = prepared->secondRequestedFrequencyHz; + plan->firstSetting = prepared->firstSetting; + plan->secondSetting = prepared->secondSetting; PlsrCopyShortProfile(&plan->profile, &prepared->profile); plan->nextSegment = prepared->nextSegment; plan->positive = prepared->positive; @@ -2399,79 +3270,147 @@ static uint8_t PlsrSelectPreparedHandoffPlan(PLSR_HANDOFF_PLAN *plan) return 1U; } -static uint8_t PlsrPrimeHandoff(void) +static uint8_t PlsrPrepareFutureHandoffQueue(void) +{ + const PLSR_HANDOFF_PLAN *prepared; + uint8_t currentSegment = PlsrCurrentSegment; + uint8_t preparedBank = PlsrPreparedHandoffBank; + + PlsrProfileQueueReset(); + if ((currentSegment == 0U) + || (currentSegment > PlsrActiveConfig.segmentCount) + || (PlsrActiveConfig.sendMode != PLSR_SEND_SUBSEQUENT)) + { + return 1U; + } + prepared = &PlsrPreparedHandoffPlans[preparedBank][currentSegment - 1U]; + if ((prepared->valid == 0U) || (prepared->profile.active == 0U) + || (prepared->profile.nextPeriod >= prepared->profile.pulseCount)) + { + return 1U; + } + (void)PlsrProfileQueueBegin(&prepared->profile, + PlsrSegmentEpoch + 1UL, + prepared->nextSegment, + preparedBank); + if (PlsrProfileQueueFill() == 0U) + { + PlsrProfileQueueReset(); + return 0U; + } + return 1U; +} + +static PLSR_PLATFORM_QUEUE_RESULT PlsrPrimeHandoff(void) { PLSR_HANDOFF_PLAN candidatePlan; uint32_t actualFrequencyHz; + PLSR_PLATFORM_QUEUE_RESULT result; PlsrHandoffPlan.valid = 0U; + if (PlsrAbStopArmed != 0U) + { + return PLSR_PLATFORM_QUEUE_FAILED; + } if (PlsrSelectPreparedHandoffPlan(&candidatePlan) == 0U) { - return 0U; + return PLSR_PLATFORM_QUEUE_FAILED; } PlsrDeferredFrequencyPending = 0U; - if (PlsrPlatformQueueFrequency( - (uint8_t)PlsrActiveConfig.pulseOutput, - candidatePlan.firstFrequencyHz, &actualFrequencyHz) == 0U) + result = PlsrPlatformLoadPreparedFromIrq( + (uint8_t)PlsrActiveConfig.pulseOutput, + &candidatePlan.firstSetting, &actualFrequencyHz); + if (result != PLSR_PLATFORM_QUEUE_APPLIED) { - PlsrTimerErrorPending = 1U; - return 0U; + if (result == PLSR_PLATFORM_QUEUE_FAILED) + { + PlsrTimerErrorPending = 1U; + } + return result; } + PlsrDiagnosticRecordFrequency(candidatePlan.firstRequestedFrequencyHz, + candidatePlan.firstSetting.actualFrequencyHz, + actualFrequencyHz); + PlsrDiagnosticQueuedExpectedHz = + candidatePlan.firstSetting.actualFrequencyHz; PlsrQueuedFrequencyHz = actualFrequencyHz; PlsrHandoffPlan.magnitude = candidatePlan.magnitude; PlsrHandoffPlan.firstFrequencyHz = actualFrequencyHz; + PlsrHandoffPlan.secondFrequencyHz = candidatePlan.secondFrequencyHz; + PlsrHandoffPlan.firstRequestedFrequencyHz = + candidatePlan.firstRequestedFrequencyHz; + PlsrHandoffPlan.secondRequestedFrequencyHz = + candidatePlan.secondRequestedFrequencyHz; + PlsrHandoffPlan.firstSetting = candidatePlan.firstSetting; + PlsrHandoffPlan.secondSetting = candidatePlan.secondSetting; PlsrCopyShortProfile(&PlsrHandoffPlan.profile, &candidatePlan.profile); PlsrHandoffPlan.nextSegment = candidatePlan.nextSegment; PlsrHandoffPlan.positive = candidatePlan.positive; PlsrHandoffPlan.valid = 1U; - return 1U; + return PLSR_PLATFORM_QUEUE_APPLIED; } -static uint8_t PlsrTrySubsequentHandoff(void) +static PLSR_PLATFORM_QUEUE_RESULT PlsrTrySubsequentHandoff(void) { - uint32_t requestedQueuedFrequencyHz; uint32_t actualQueuedFrequencyHz; uint32_t currentFrequencyHz; uint32_t queuedFrequencyHz; uint8_t nextSegment = PlsrHandoffPlan.nextSegment; uint64_t magnitude = PlsrHandoffPlan.magnitude; uint8_t positive = PlsrHandoffPlan.positive; + PLSR_PLATFORM_QUEUE_RESULT result; if ((PlsrHandoffPlan.valid == 0U) || (PlsrActiveConfig.sendMode != PLSR_SEND_SUBSEQUENT) || (PlsrStopRequested != 0U) || (PlsrCountOverflowPending != 0U) || (PlsrCutRequested != 0U) + || (PlsrAbStopArmed != 0U) || (PlsrCurrentFrequencyHz != PlsrHandoffPlan.firstFrequencyHz) || (nextSegment == 0U) || (nextSegment > PlsrActiveConfig.segmentCount)) { - return 0U; + return PLSR_PLATFORM_QUEUE_FAILED; } - - PlsrCopyShortProfile(&PlsrShortProfile, - &PlsrHandoffPlan.profile); - requestedQueuedFrequencyHz = PlsrCurrentFrequencyHz; - if ((PlsrShortProfile.active != 0U) - && (PlsrShortProfile.nextPeriod < PlsrShortProfile.pulseCount)) + if ((PlsrHandoffPlan.profile.active != 0U) + && ((PlsrProfileQueue.active == 0U) + || (PlsrProfileQueue.producerEpoch != PlsrSegmentEpoch + 1UL) + || (PlsrProfileQueue.producerSegment != nextSegment) + || (PlsrProfileQueue.preparedHandoffBank + != PlsrPreparedHandoffBank))) { - requestedQueuedFrequencyHz = - PlsrShortProfileTakeFrequency(&PlsrShortProfile); + PlsrTimerErrorPending = 1U; + return PLSR_PLATFORM_QUEUE_FAILED; } + PlsrDeferredFrequencyPending = 0U; - if (PlsrPlatformQueueFrequency( - (uint8_t)PlsrActiveConfig.pulseOutput, - requestedQueuedFrequencyHz, &actualQueuedFrequencyHz) == 0U) + result = PlsrPlatformLoadPreparedFromIrq( + (uint8_t)PlsrActiveConfig.pulseOutput, + &PlsrHandoffPlan.secondSetting, &actualQueuedFrequencyHz); + if (result == PLSR_PLATFORM_QUEUE_STALE) + { + return result; + } + if (result == PLSR_PLATFORM_QUEUE_FAILED) { PlsrShortProfile.active = 0U; PlsrHandoffPlan.valid = 0U; PlsrTimerErrorPending = 1U; - return 0U; + return result; } + PlsrCopyShortProfile(&PlsrShortProfile, + &PlsrHandoffPlan.profile); + PlsrDiagnosticRecordFrequency( + PlsrHandoffPlan.secondRequestedFrequencyHz, + PlsrHandoffPlan.secondSetting.actualFrequencyHz, + actualQueuedFrequencyHz); + PlsrDiagnosticQueuedExpectedHz = + PlsrHandoffPlan.secondSetting.actualFrequencyHz; PlsrQueuedFrequencyHz = actualQueuedFrequencyHz; + PlsrDiagnosticFinishSegment(1U); PlsrSegmentEpoch++; PlsrCurrentSegment = nextSegment; PlsrRemainingPulses = magnitude; @@ -2489,12 +3428,18 @@ static uint8_t PlsrTrySubsequentHandoff(void) PlsrExtEdgePending = 0U; PlsrExtPreviousLevel = PlsrPlatformReadInput((uint8_t)PlsrActiveConfig.extInput); + PlsrDiagnosticBeginSegment(nextSegment, magnitude, positive); PlsrSeamlessHandoffPending = 1U; PlsrHandoffPlan.valid = 0U; if (PlsrRemainingPulses == 1UL) { - (void)PlsrPrimeHandoff(); + result = PlsrPrimeHandoff(); + if (result == PLSR_PLATFORM_QUEUE_STALE) + { + return result; + } } + (void)PlsrQueueFinalAbBoundaryFromIrq(); queuedFrequencyHz = PlsrQueuedFrequencyHz; currentFrequencyHz = PlsrCurrentFrequencyHz; if (PlsrShortProfile.active != 0U) @@ -2516,7 +3461,7 @@ static uint8_t PlsrTrySubsequentHandoff(void) { PlsrRunStatus = PLSR_STATUS_RUNNING; } - return 1U; + return PLSR_PLATFORM_QUEUE_APPLIED; } static void PlsrHandleBoundary(uint8_t extEdge) @@ -2524,14 +3469,17 @@ static void PlsrHandleBoundary(uint8_t extEdge) const PLSR_SEGMENT_CONFIG *segment; uint8_t wasCut = PlsrBoundaryWasCut; + PlsrPlatformStopPulse((uint8_t)PlsrActiveConfig.pulseOutput); PlsrBoundaryPending = 0U; PlsrBoundaryWasCut = 0U; PlsrPulseActive = 0U; PlsrCurrentFrequencyHz = 0UL; PlsrQueuedFrequencyHz = 0UL; PlsrShortProfile.active = 0U; + PlsrProfileQueueReset(); PlsrHandoffPlan.valid = 0U; PlsrDeferredFrequencyPending = 0U; + PlsrAbStopArmed = 0U; PlsrCheckpointPosition(1U); if (PlsrTimerErrorPending != 0U) @@ -2634,6 +3582,7 @@ static void PlsrRequestCut(uint32_t expectedEpoch) else if (PlsrPulseActive != 0U) { PlsrCutRequested = 1U; + (void)PlsrArmFinalAbBoundaryLocked(); } else { @@ -2682,18 +3631,40 @@ static void PlsrPollWaiting(uint8_t extEdge) } } -static void PlsrPollPersistence(void) +static void PlsrPollPersistenceDelay(void) +{ + if ((PlsrPersistenceDirty != 0U) + && (PlsrIsBusy() == 0U) + && (PlsrPersistenceDelayMs != 0U)) + { + PlsrPersistenceDelayMs--; + } +} + +void PlsrServicePersistence(void) { PLSR_PERSIST_PAYLOAD payload; + PLSR_PLATFORM_SERVICE_RESULT serviceResult; uint32_t criticalState; - if ((PlsrPersistenceDirty == 0U) || (PlsrIsBusy() != 0U)) + if (PlsrIsBusy() != 0U) + { + return; + } + serviceResult = PlsrPlatformServicePersistence(); + if (serviceResult == PLSR_PLATFORM_SERVICE_FAILED) + { + PlsrRunStatus = PLSR_STATUS_ERROR; + PlsrError = PLSR_ERROR_INTERNAL; + return; + } + if ((serviceResult == PLSR_PLATFORM_SERVICE_DEFERRED) + || (PlsrPersistenceDirty == 0U)) { return; } if (PlsrPersistenceDelayMs != 0U) { - PlsrPersistenceDelayMs--; return; } @@ -2750,6 +3721,7 @@ uint8_t PlsrInit(void) (void)memset(&PlsrActiveConfig, 0, sizeof(PlsrActiveConfig)); (void)memset(&PlsrRamp, 0, sizeof(PlsrRamp)); (void)memset(&PlsrShortProfile, 0, sizeof(PlsrShortProfile)); + (void)memset(&PlsrProfileQueue, 0, sizeof(PlsrProfileQueue)); (void)memset(&PlsrHandoffPlan, 0, sizeof(PlsrHandoffPlan)); (void)memset(PlsrPreparedHandoffPlans, 0, sizeof(PlsrPreparedHandoffPlans)); @@ -2780,10 +3752,22 @@ uint8_t PlsrInit(void) PlsrExtEdgePending = 0U; PlsrStopRequested = 0U; PlsrStopPulsesRemaining = 0U; + PlsrAbStopArmed = 0U; PlsrLastDirectionValid = 0U; PlsrPositionCheckpointElapsedMs = 0U; PlsrCommandMailbox.command = 0U; PlsrCommandMailbox.state = PLSR_COMMAND_MAILBOX_EMPTY; + PlsrDiagnosticReset(); +#ifdef PLSR_HOST_TEST + PlsrHostTestEventSequence = 0UL; + PlsrHostTestLastGateEvent = 0UL; + PlsrHostTestLastDiagnosticFinishEvent = 0UL; +#endif +#if defined(PLSR_DEBUG_TIMING) && (PLSR_DEBUG_TIMING != 0) + PlsrProfileProducerItemCount = 0UL; + PlsrProfileProducerTotalCycles = 0UL; + PlsrProfileProducerMaxItemCycles = 0UL; +#endif PlsrError = PLSR_ERROR_NONE; PlsrRunStatus = PLSR_STATUS_IDLE; PlsrInitialized = 1U; @@ -2869,7 +3853,9 @@ static void PlsrExecuteStart(void) if (PlsrStartSegment((uint8_t)PlsrActiveConfig.startSegment, 0U, 0UL) == 0U) { - PlsrEnterError(PLSR_ERROR_INVALID_RESOURCE); + PlsrEnterError((PlsrTimerErrorPending != 0U) + ? PLSR_ERROR_TIMER + : PLSR_ERROR_INVALID_RESOURCE); } } @@ -2892,6 +3878,7 @@ static uint8_t PlsrExecuteStop(void) PlsrStopRequested = 1U; PlsrStopPulsesRemaining = 0U; PlsrShortProfile.active = 0U; + PlsrProfileQueueInvalidateGeneration(); PlsrHandoffPlan.valid = 0U; PlsrInvalidateHandoffPlans(); if (PlsrBoundaryPending != 0U) @@ -2922,6 +3909,7 @@ static uint8_t PlsrExecuteStop(void) return 1U; } PlsrStopPulsesRemaining = PlsrStopDrainPulseCount(); + (void)PlsrArmFinalAbBoundaryLocked(); } PlsrPlatformExitCritical(criticalState); return 1U; @@ -2950,6 +3938,7 @@ static void PlsrExecuteClear(void) PlsrDirectionDelayRemainingMs = 0U; PlsrExtEdgePending = 0U; PlsrShortProfile.active = 0U; + PlsrProfileQueueReset(); PlsrHandoffPlan.valid = 0U; PlsrInvalidateHandoffPlans(); PlsrDeferredFrequencyPending = 0U; @@ -3040,14 +4029,14 @@ void PlsrPoll1ms(void) { PlsrExtEdgePending = 0U; PlsrHandleBoundary(extEdge); - PlsrPollPersistence(); + PlsrPollPersistenceDelay(); return; } if (PlsrIsBusy() == 0U) { PlsrExtEdgePending = 0U; - PlsrPollPersistence(); + PlsrPollPersistenceDelay(); return; } @@ -3118,11 +4107,13 @@ void PlsrPoll1ms(void) newTargetHz = PlsrFrequencyUpdateTargetHz; if ((PlsrStopRequested == 0U) && (PlsrFrequencyUpdatePending != 0U) + && (PlsrAbStopArmed == 0U) && (PlsrFrequencyUpdateSegment == activeSegmentNumber)) { PlsrFrequencyUpdatePending = 0U; activeSegment->frequencyHz = newTargetHz; PlsrShortProfile.active = 0U; + PlsrProfileQueueInvalidateGeneration(); PlsrBoundaryRampStarted = 0U; PlsrRampStart(PlsrCurrentFrequencyHz, newTargetHz); if (PlsrRamp.active == 0U) @@ -3167,6 +4158,7 @@ void PlsrPoll1ms(void) { PlsrStopPulsesRemaining = PlsrStopDrainPulseCount(); } + (void)PlsrArmFinalAbBoundaryLocked(); PlsrPlatformExitCritical(criticalState); return; } @@ -3193,7 +4185,8 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) { uint32_t positionBits; uint32_t completedFrequencyHz; - uint32_t activeFrequencyHz; + uint64_t remainingPulses; + PLSR_PLATFORM_QUEUE_RESULT queueResult; if ((PlsrPulseActive == 0U) || (pulseOutput != (uint8_t)PlsrActiveConfig.pulseOutput)) @@ -3202,13 +4195,12 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) } completedFrequencyHz = PlsrCurrentFrequencyHz; - activeFrequencyHz = PlsrPlatformActiveFrequency(pulseOutput); - if (activeFrequencyHz == 0UL) + PlsrDiagnosticCheckActiveFrequency(completedFrequencyHz); + PlsrCurrentFrequencyHz = PlsrPlatformActiveFrequency(pulseOutput); + if (PlsrCurrentFrequencyHz == 0UL) { - PlsrTimerErrorPending = 1U; - return; + PlsrCurrentFrequencyHz = PlsrQueuedFrequencyHz; } - PlsrCurrentFrequencyHz = activeFrequencyHz; if ((PlsrStopRequested != 0U) && (PlsrRamp.active == 0U) && (PlsrStopPulsesRemaining != 0U)) { @@ -3221,7 +4213,7 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) positionBits = (uint32_t)PlsrPosition; if (PlsrCountPositive != 0U) { - if (PlsrPosition == INT32_MAX) + if (positionBits == (uint32_t)INT32_MAX) { PlsrPositionValid = 0U; PlsrCountOverflowPending = 1U; @@ -3230,7 +4222,7 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) } else { - if (PlsrPosition == INT32_MIN) + if (positionBits == (uint32_t)INT32_MIN) { PlsrPositionValid = 0U; PlsrCountOverflowPending = 1U; @@ -3240,25 +4232,39 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) PlsrPosition = (int32_t)positionBits; PlsrPositionCheckpointDirty = 1U; - if (PlsrRemainingPulses != 0UL) + remainingPulses = PlsrRemainingPulses; + if (remainingPulses != 0UL) { - PlsrRemainingPulses--; + remainingPulses--; + PlsrRemainingPulses = remainingPulses; } - if ((PlsrRemainingPulses == 0UL) || (PlsrCutRequested != 0U) + if ((remainingPulses == 0UL) || (PlsrCutRequested != 0U) || (PlsrCountOverflowPending != 0U)) { - if ((PlsrRemainingPulses == 0UL) - && (PlsrTrySubsequentHandoff() != 0U)) + if (remainingPulses == 0UL) { - return; + queueResult = PlsrTrySubsequentHandoff(); + if (queueResult != PLSR_PLATFORM_QUEUE_FAILED) + { + return; + } } + PlsrPlatformGateFromIrq(pulseOutput); +#ifdef PLSR_HOST_TEST + PlsrHostTestEventSequence++; + PlsrHostTestLastGateEvent = PlsrHostTestEventSequence; +#endif + PlsrDiagnosticFinishSegment( + ((remainingPulses == 0UL) + && (PlsrCutRequested == 0U) + && (PlsrCountOverflowPending == 0U)) ? 1U : 0U); PlsrShortProfile.active = 0U; PlsrHandoffPlan.valid = 0U; PlsrBoundaryFrequencyHz = completedFrequencyHz; PlsrBoundaryWasCut = (PlsrCutRequested != 0U) ? 1U : 0U; PlsrCutRequested = 0U; - PlsrPlatformStopPulse(pulseOutput); + PlsrAbStopArmed = 0U; PlsrPulseActive = 0U; PlsrCurrentFrequencyHz = 0UL; PlsrQueuedFrequencyHz = 0UL; @@ -3266,42 +4272,72 @@ void PlsrPulseTimerIrq(uint8_t pulseOutput) return; } - if ((PlsrShortProfile.active != 0U) - && (PlsrAdvanceShortProfile(pulseOutput) == 0U)) + if (PlsrShortProfile.active != 0U) { - PlsrTimerErrorPending = 1U; - PlsrShortProfile.active = 0U; - PlsrHandoffPlan.valid = 0U; - PlsrBoundaryFrequencyHz = completedFrequencyHz; - PlsrBoundaryWasCut = 0U; - PlsrCutRequested = 0U; - PlsrPlatformStopPulse(pulseOutput); - PlsrPulseActive = 0U; - PlsrCurrentFrequencyHz = 0UL; - PlsrQueuedFrequencyHz = 0UL; - PlsrBoundaryPending = 1U; - return; + queueResult = PlsrProfileQueueCommitNext(pulseOutput); + if (queueResult == PLSR_PLATFORM_QUEUE_STALE) + { + return; + } + if (queueResult == PLSR_PLATFORM_QUEUE_FAILED) + { + PlsrDiagnosticFinishSegment(0U); + PlsrTimerErrorPending = 1U; + PlsrShortProfile.active = 0U; + PlsrHandoffPlan.valid = 0U; + PlsrBoundaryFrequencyHz = completedFrequencyHz; + PlsrBoundaryWasCut = 0U; + PlsrCutRequested = 0U; + PlsrPlatformGateFromIrq(pulseOutput); + PlsrAbStopArmed = 0U; + PlsrPulseActive = 0U; + PlsrCurrentFrequencyHz = 0UL; + PlsrQueuedFrequencyHz = 0UL; + PlsrBoundaryPending = 1U; + return; + } } if ((PlsrShortProfile.active == 0U) - && (PlsrRemainingPulses == 1UL)) + && (remainingPulses == 1UL) + && (PlsrActiveConfig.sendMode == PLSR_SEND_SUBSEQUENT)) { - (void)PlsrPrimeHandoff(); + if (PlsrPrimeHandoff() == PLSR_PLATFORM_QUEUE_STALE) + { + return; + } } if ((PlsrShortProfile.active == 0U) && (PlsrHandoffPlan.valid == 0U) - && (PlsrCommitDeferredFrequency(pulseOutput) == 0U)) + && (PlsrDeferredFrequencyPending != 0U)) { - PlsrTimerErrorPending = 1U; - PlsrBoundaryFrequencyHz = completedFrequencyHz; - PlsrBoundaryWasCut = 0U; - PlsrCutRequested = 0U; - PlsrPlatformStopPulse(pulseOutput); - PlsrPulseActive = 0U; - PlsrCurrentFrequencyHz = 0UL; - PlsrQueuedFrequencyHz = 0UL; - PlsrBoundaryPending = 1U; + queueResult = PlsrCommitDeferredFrequency(pulseOutput); + if (queueResult == PLSR_PLATFORM_QUEUE_STALE) + { + return; + } + if (queueResult == PLSR_PLATFORM_QUEUE_FAILED) + { + PlsrDiagnosticFinishSegment(0U); + PlsrTimerErrorPending = 1U; + PlsrBoundaryFrequencyHz = completedFrequencyHz; + PlsrBoundaryWasCut = 0U; + PlsrCutRequested = 0U; + PlsrPlatformGateFromIrq(pulseOutput); + PlsrAbStopArmed = 0U; + PlsrPulseActive = 0U; + PlsrCurrentFrequencyHz = 0UL; + PlsrQueuedFrequencyHz = 0UL; + PlsrBoundaryPending = 1U; + return; + } + } + if ((PlsrActiveConfig.outputMode == PLSR_OUTPUT_AB) + && (PlsrQueueFinalAbBoundaryFromIrq() == 0U)) + { + return; } + } PLSR_MB_RESULT PlsrModbusReadHolding(uint16_t startAddress, @@ -3314,6 +4350,7 @@ PLSR_MB_RESULT PlsrModbusReadHolding(uint16_t startAddress, int32_t position; uint32_t frequency; uint16_t statusWords[7]; + uint16_t diagnosticWords[26]; if (values == NULL) { @@ -3335,6 +4372,34 @@ PLSR_MB_RESULT PlsrModbusReadHolding(uint16_t startAddress, statusWords[4] = (uint16_t)PlsrRunStatus; statusWords[5] = PlsrCurrentSegment; statusWords[6] = (uint16_t)PlsrError; + diagnosticWords[0] = PlsrDiagnostic.flags; + diagnosticWords[1] = PlsrDiagnostic.reason; + diagnosticWords[2] = PlsrDiagnostic.lastSegment; + diagnosticWords[3] = PlsrDiagnostic.modeDirection; + diagnosticWords[4] = PlsrLowWord(PlsrDiagnostic.expectedCycles); + diagnosticWords[5] = PlsrHighWord(PlsrDiagnostic.expectedCycles); + diagnosticWords[6] = PlsrLowWord(PlsrDiagnostic.observedCycles); + diagnosticWords[7] = PlsrHighWord(PlsrDiagnostic.observedCycles); + diagnosticWords[8] = PlsrLowWord((uint32_t)PlsrDiagnostic.countError); + diagnosticWords[9] = PlsrHighWord((uint32_t)PlsrDiagnostic.countError); + diagnosticWords[10] = PlsrLowWord(PlsrDiagnostic.requestedHz); + diagnosticWords[11] = PlsrHighWord(PlsrDiagnostic.requestedHz); + diagnosticWords[12] = PlsrLowWord(PlsrDiagnostic.expectedTimerHz); + diagnosticWords[13] = PlsrHighWord(PlsrDiagnostic.expectedTimerHz); + diagnosticWords[14] = PlsrLowWord(PlsrDiagnostic.activeTimerHz); + diagnosticWords[15] = PlsrHighWord(PlsrDiagnostic.activeTimerHz); + diagnosticWords[16] = + PlsrLowWord((uint32_t)PlsrDiagnostic.requestErrorHz); + diagnosticWords[17] = + PlsrHighWord((uint32_t)PlsrDiagnostic.requestErrorHz); + diagnosticWords[18] = PlsrLowWord(PlsrDiagnostic.curveSampleCount); + diagnosticWords[19] = PlsrHighWord(PlsrDiagnostic.curveSampleCount); + diagnosticWords[20] = PlsrLowWord(PlsrDiagnostic.curveMismatchCount); + diagnosticWords[21] = PlsrHighWord(PlsrDiagnostic.curveMismatchCount); + diagnosticWords[22] = PlsrLowWord(PlsrDiagnostic.curveMaxAbsErrorHz); + diagnosticWords[23] = PlsrHighWord(PlsrDiagnostic.curveMaxAbsErrorHz); + diagnosticWords[24] = PlsrLowWord(PlsrDiagnostic.firstMismatchSample); + diagnosticWords[25] = PlsrHighWord(PlsrDiagnostic.firstMismatchSample); PlsrPlatformExitCritical(criticalState); for (index = 0U; index < quantity; index++) @@ -3346,15 +4411,29 @@ PLSR_MB_RESULT PlsrModbusReadHolding(uint16_t startAddress, { values[index] = PlsrReadConfigWord(&PlsrShadowConfig, address); } + else if (address == PLSR_OUTPUT_MODE_ADDRESS) + { + values[index] = PlsrShadowConfig.outputMode; + } else if ((address >= PLSR_STATUS_FIRST_ADDRESS) && (address <= PLSR_STATUS_LAST_ADDRESS)) { values[index] = statusWords[address - PLSR_STATUS_FIRST_ADDRESS]; } + else if ((address >= PLSR_DIAGNOSTIC_FIRST_ADDRESS) + && (address <= PLSR_DIAGNOSTIC_LAST_ADDRESS)) + { + values[index] = + diagnosticWords[address - PLSR_DIAGNOSTIC_FIRST_ADDRESS]; + } else if (address == PLSR_CONTROL_ADDRESS) { values[index] = 0U; } + else if (address == PLSR_DIAGNOSTIC_CONTROL_ADDRESS) + { + values[index] = 0U; + } else { return PLSR_MB_ILLEGAL_ADDRESS; @@ -3378,6 +4457,7 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, uint8_t drainedToDifferentSegment = 0U; uint8_t segmentBeforeDrain; uint32_t drainedSegmentTargetHz = 0UL; + PLSR_PLATFORM_QUEUE_RESULT queueResult; if (values == NULL) { @@ -3395,6 +4475,35 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, return PLSR_MB_ILLEGAL_ADDRESS; } + if ((startAddress >= PLSR_DIAGNOSTIC_FIRST_ADDRESS) + && (startAddress <= PLSR_DIAGNOSTIC_LAST_ADDRESS)) + { + return PLSR_MB_ILLEGAL_ADDRESS; + } + + if (startAddress == PLSR_DIAGNOSTIC_CONTROL_ADDRESS) + { + if (quantity != 1U) + { + return PLSR_MB_ILLEGAL_ADDRESS; + } + if ((values[0] != 0U) && (values[0] != 1U)) + { + return PLSR_MB_ILLEGAL_VALUE; + } + if ((values[0] != 0U) && (PlsrIsBusy() != 0U)) + { + return PLSR_MB_DEVICE_BUSY; + } + if (values[0] != 0U) + { + criticalState = PlsrPlatformEnterCritical(); + PlsrDiagnosticReset(); + PlsrPlatformExitCritical(criticalState); + } + return PLSR_MB_OK; + } + if (startAddress == PLSR_CONTROL_ADDRESS) { if (quantity != 1U) @@ -3412,6 +4521,30 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, } } + if (startAddress == PLSR_OUTPUT_MODE_ADDRESS) + { + if (quantity != 1U) + { + return PLSR_MB_ILLEGAL_ADDRESS; + } + if (PlsrIsBusy() != 0U) + { + return PLSR_MB_DEVICE_BUSY; + } + PlsrCandidateConfig = PlsrShadowConfig; + PlsrCandidateConfig.outputMode = values[0]; + if (PlsrConfigIsValid(&PlsrCandidateConfig, 0U) == 0U) + { + return PLSR_MB_ILLEGAL_VALUE; + } + criticalState = PlsrPlatformEnterCritical(); + PlsrShadowConfig = PlsrCandidateConfig; + PlsrPlatformExitCritical(criticalState); + PlsrPlatformCheckpointConfig(&PlsrShadowConfig); + PlsrMarkPersistenceDirty(PLSR_CONFIG_SAVE_DELAY_MS); + return PLSR_MB_OK; + } + if ((startAddress < PLSR_CONFIG_FIRST_ADDRESS) || ((uint32_t)startAddress + quantity - 1UL > PLSR_CONFIG_LAST_ADDRESS)) @@ -3507,6 +4640,7 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, if ((frequencyChanged != 0U) && (index + 1U == PlsrCurrentSegment) && (PlsrStopRequested == 0U) + && (PlsrAbStopArmed == 0U) && (PlsrRunStatus != PLSR_STATUS_WAITING)) { PlsrFrequencyUpdateTargetHz = @@ -3517,11 +4651,21 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, } PlsrPreparedHandoffBank = handoffBank; PlsrHandoffPlan.valid = 0U; + PlsrProfileQueueInvalidateGeneration(); + if ((drainedToDifferentSegment == 0U) + && (PlsrPulseActive != 0U) + && (PlsrAbStopArmed == 0U) + && (PlsrShortProfile.active == 0U) + && (PlsrRemainingPulses == 1UL)) + { + (void)PlsrPrimeHandoff(); + } if ((drainedToDifferentSegment != 0U) && (PlsrPulseActive != 0U) && (PlsrCurrentSegment != 0U) && (PlsrCurrentSegment <= PlsrActiveConfig.segmentCount) && (PlsrStopRequested == 0U) + && (PlsrAbStopArmed == 0U) && (PlsrRunStatus != PLSR_STATUS_WAITING) && (PlsrCurrentFrequencyHz != drainedSegmentTargetHz)) { @@ -3530,28 +4674,32 @@ PLSR_MB_RESULT PlsrModbusWriteHolding(uint16_t startAddress, PlsrFrequencyUpdateSegment = PlsrCurrentSegment; PlsrFrequencyUpdatePending = 1U; } - if ((PlsrPulseActive != 0U) - && (PlsrShortProfile.active == 0U) - && (PlsrRemainingPulses == 1UL)) - { - (void)PlsrPrimeHandoff(); - } } PlsrPlatformExitCritical(criticalState); + if ((updateActiveFrequencies != 0U) + && (PlsrPulseActive != 0U) + && (PlsrAbStopArmed == 0U) + && (PlsrFrequencyUpdatePending == 0U) + && (PlsrPrepareFutureHandoffQueue() == 0U)) + { + PlsrTimerErrorPending = 1U; + } if ((drainedToDifferentSegment != 0U) + && (PlsrAbStopArmed == 0U) && (PlsrFrequencyUpdatePending != 0U)) { uint32_t drainEpoch = PlsrSegmentEpoch; uint32_t actualDrainFrequencyHz; - if (PlsrPlatformQueueFrequency( - (uint8_t)PlsrActiveConfig.pulseOutput, - drainedSegmentTargetHz, &actualDrainFrequencyHz) == 0U) + queueResult = PlsrDiagnosticQueueFrequency( + (uint8_t)PlsrActiveConfig.pulseOutput, + drainedSegmentTargetHz, &actualDrainFrequencyHz); + if (queueResult == PLSR_PLATFORM_QUEUE_FAILED) { PlsrTimerErrorPending = 1U; } - else + else if (queueResult == PLSR_PLATFORM_QUEUE_APPLIED) { uint32_t currentEpoch; uint8_t updateSegment; @@ -3596,4 +4744,70 @@ void PlsrTestSetPosition(int32_t position, uint8_t positionValid) PlsrPlatformExitCritical(criticalState); PlsrPlatformCheckpointPosition(position, PlsrPositionValid, 0U); } + +void PlsrTestSetDiagnosticCurveCounts(uint32_t sampleCount, + uint32_t mismatchCount) +{ + PlsrDiagnostic.curveSampleCount = sampleCount; + PlsrDiagnostic.curveMismatchCount = mismatchCount; +} + +void PlsrTestForceProfileQueueEmpty(void) +{ + PlsrProfileQueue.readIndex = PlsrProfileQueue.writeIndex; + PlsrProfileQueue.generatorComplete = 0U; + PlsrProfileQueue.active = 1U; +} + +uint16_t PlsrTestProfileQueueCount(void) +{ + return PlsrProfileQueueCount(); +} + +uint32_t PlsrTestProfileQueueGeneration(void) +{ + return PlsrProfileQueue.generation; +} + +uint32_t PlsrTestProfileQueueReadIndex(void) +{ + return PlsrProfileQueue.readIndex; +} + +uint32_t PlsrTestProfileQueueWriteIndex(void) +{ + return PlsrProfileQueue.writeIndex; +} + +uint32_t PlsrTestProfileQueueHeadFrequency(void) +{ + uint32_t readIndex = PlsrProfileQueue.readIndex; + + if (readIndex == PlsrProfileQueue.writeIndex) + { + return 0UL; + } + return PlsrProfileQueue + .entries[readIndex & PLSR_PROFILE_QUEUE_MASK].requestedFrequencyHz; +} + +uint16_t PlsrTestProfileProducerNextPeriod(void) +{ + return PlsrProfileQueue.producerProfile.nextPeriod; +} + +uint16_t PlsrTestActiveProfileNextPeriod(void) +{ + return PlsrShortProfile.nextPeriod; +} + +uint32_t PlsrTestLastGateEvent(void) +{ + return PlsrHostTestLastGateEvent; +} + +uint32_t PlsrTestLastDiagnosticFinishEvent(void) +{ + return PlsrHostTestLastDiagnosticFinishEvent; +} #endif diff --git a/PLSR/Src/plsr_internal.h b/PLSR/Src/plsr_internal.h index 54d56c2..044ff9f 100644 --- a/PLSR/Src/plsr_internal.h +++ b/PLSR/Src/plsr_internal.h @@ -6,6 +6,9 @@ #define PLSR_SEGMENT_COUNT_MAX (10U) #define PLSR_FREQUENCY_MAX_HZ (100000UL) +#define PLSR_OUTPUT_PULSE_DIR (0U) +#define PLSR_OUTPUT_AB (1U) + typedef struct { uint32_t frequencyHz; @@ -35,6 +38,8 @@ typedef struct uint16_t accelerationTimeMs; uint16_t decelerationTimeMs; PLSR_SEGMENT_CONFIG segments[PLSR_SEGMENT_COUNT_MAX]; + /* Kept at the end so version-2 persisted configurations remain a prefix. */ + uint16_t outputMode; } PLSR_CONFIG; typedef struct diff --git a/PLSR/Src/plsr_platform.h b/PLSR/Src/plsr_platform.h index e7b45cd..013a507 100644 --- a/PLSR/Src/plsr_platform.h +++ b/PLSR/Src/plsr_platform.h @@ -4,29 +4,92 @@ #include "plsr_internal.h" #include +typedef enum +{ + PLSR_PLATFORM_STOP_COMPLETE = 0, + PLSR_PLATFORM_STOP_PENDING, + PLSR_PLATFORM_STOP_FORCED_FAULT +} PLSR_PLATFORM_STOP_RESULT; + +typedef enum +{ + PLSR_PLATFORM_QUEUE_FAILED = 0, + PLSR_PLATFORM_QUEUE_APPLIED, + PLSR_PLATFORM_QUEUE_STALE +} PLSR_PLATFORM_QUEUE_RESULT; + +typedef enum +{ + PLSR_PLATFORM_SERVICE_FAILED = 0, + PLSR_PLATFORM_SERVICE_READY, + PLSR_PLATFORM_SERVICE_DEFERRED +} PLSR_PLATFORM_SERVICE_RESULT; + +typedef struct +{ + uint32_t actualFrequencyHz; + uint16_t prescaler; + uint16_t pairPrescaler; + uint16_t period; + uint16_t compare; +} PLSR_PLATFORM_TIMER_SETTING; + uint8_t PlsrPlatformInit(void); uint8_t PlsrPlatformPrepare(uint8_t pulseOutput, uint8_t directionOutput, - uint8_t directionLevel); + uint8_t directionLevel, + uint8_t outputMode, + uint8_t directionPositive); uint8_t PlsrPlatformStartPulse(uint8_t pulseOutput, uint32_t firstFrequencyHz, uint32_t queuedFrequencyHz, uint32_t *actualFirstFrequencyHz, uint32_t *actualQueuedFrequencyHz); -uint8_t PlsrPlatformQueueFrequency(uint8_t pulseOutput, - uint32_t frequencyHz, - uint32_t *actualFrequencyHz); +uint8_t PlsrPlatformBuildTimerSetting( + uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + PLSR_PLATFORM_TIMER_SETTING *setting); +uint8_t PlsrPlatformStartPrepared( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *firstSetting, + const PLSR_PLATFORM_TIMER_SETTING *queuedSetting, + uint32_t *actualFirstFrequencyHz, + uint32_t *actualQueuedFrequencyHz); +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformLoadPreparedFromIrq( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *setting, + uint32_t *actualFrequencyHz); +void PlsrPlatformGateFromIrq(uint8_t pulseOutput); +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformQueueFrequency( + uint8_t pulseOutput, + uint32_t frequencyHz, + uint32_t *actualFrequencyHz); void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput); uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput); +uint8_t PlsrPlatformExpectedFrequency(uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + uint32_t *actualFrequencyHz); +uint64_t PlsrPlatformObservedPulses(uint8_t pulseOutput); +/* Returns 0, PLSR diagnostic reason 2 (frequency), or 3 (curve/order). */ +uint16_t PlsrPlatformDiagnosticFault(void); +/* Caller must hold the platform critical section. */ +PLSR_PLATFORM_STOP_RESULT PlsrPlatformRequestStopLocked( + uint8_t pulseOutput, + uint8_t requireZeroBoundary); +uint8_t PlsrPlatformQueueFinalArmFromIrq(uint8_t pulseOutput); void PlsrPlatformStopPulse(uint8_t pulseOutput); uint8_t PlsrPlatformReadInput(uint8_t inputSelection); uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload); +PLSR_PLATFORM_SERVICE_RESULT PlsrPlatformServicePersistence(void); uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload); void PlsrPlatformCheckpointConfig(const PLSR_CONFIG *config); void PlsrPlatformCheckpointPosition(int32_t position, uint8_t positionValid, uint8_t wasBusy); +void PlsrPlatformForceSafeOutputsFromFault(void); uint32_t PlsrPlatformEnterCritical(void); void PlsrPlatformExitCritical(uint32_t state); diff --git a/PLSR/Src/plsr_platform_f407.c b/PLSR/Src/plsr_platform_f407.c index ee899dd..291d2f7 100644 --- a/PLSR/Src/plsr_platform_f407.c +++ b/PLSR/Src/plsr_platform_f407.c @@ -1,6 +1,20 @@ #include "plsr_platform.h" #include "plsr.h" +static uint8_t PlsrFlashNeedsStartupRecovery( + uint8_t haveValidRecord, + uint8_t sectorAHasProgrammedSlot, + uint32_t sectorAFirstErasedAddress, + uint8_t sectorBHasProgrammedSlot, + uint32_t sectorBFirstErasedAddress) +{ + return ((haveValidRecord == 0U) + && (sectorAHasProgrammedSlot != 0U) + && (sectorBHasProgrammedSlot != 0U) + && (sectorAFirstErasedAddress == 0UL) + && (sectorBFirstErasedAddress == 0UL)) ? 1U : 0U; +} + #ifdef PLSR_HOST_TEST #include @@ -8,27 +22,84 @@ static uint8_t PlsrHostPulseActive[4]; static uint32_t PlsrHostFrequency[4]; static uint32_t PlsrHostQueuedFrequency[4]; +static PLSR_PLATFORM_TIMER_SETTING PlsrHostActiveSetting[4]; +static PLSR_PLATFORM_TIMER_SETTING PlsrHostQueuedSetting[4]; static uint8_t PlsrHostUpdatePending[4]; +static uint8_t PlsrHostOutputMode[4]; +static uint8_t PlsrHostDirectionPositive[4]; +static uint8_t PlsrHostAbQuarter[4]; +static uint8_t PlsrHostAbPhase[4]; +static uint32_t PlsrHostAbTransitions[4]; +static uint8_t PlsrHostAbStopPending[4]; +static uint8_t PlsrHostAbFastGated[4]; +static uint32_t PlsrHostAbFastGateCount; +static uint32_t PlsrHostAbCleanupCount; +static uint64_t PlsrHostObservedPulses[4]; static uint8_t PlsrHostInputs[2]; static uint8_t PlsrHostSelectedPulse; static uint8_t PlsrHostDirectionLevel; +static uint8_t PlsrHostDirectionPinLevel[4]; +static uint32_t PlsrHostDirectionWriteCount[4]; +static uint32_t PlsrHostDirectionTransitionCount[4]; static uint8_t PlsrHostEmitPulseOnCriticalEntry; static uint8_t PlsrHostEmitPulseOnCriticalExit; static uint8_t PlsrHostLatchPulseOnCriticalEntry; static uint8_t PlsrHostCriticalEntriesToSkip; +static uint8_t PlsrHostLatchAbFinalQuarterOnStopArm; +static uint8_t PlsrHostCompleteAbCycleOnQueueCommit; +static uint32_t PlsrHostCriticalDepth; static uint8_t PlsrHostFailNextStart; +static uint8_t PlsrHostStaleNextFrequencyAtUpdate; static uint8_t PlsrHostFailNextFrequencyAtUpdate; +static uint8_t PlsrHostFailNextStopRequest; +static uint8_t PlsrHostFinalArmJobPending; +static uint8_t PlsrHostFinalArmJobOwner; +static uint8_t PlsrHostDeferFinalArmJob; +static int32_t PlsrHostCountOffset; +static int32_t PlsrHostFrequencyOffsetHz; +static uint8_t PlsrHostCurveMismatchPending; +static uint16_t PlsrHostDiagnosticFault; static PLSR_PERSIST_PAYLOAD PlsrHostPersistentPayload; static uint8_t PlsrHostPersistentValid; static uint32_t PlsrHostSaveCount; +static void PlsrHostServiceFinalArmJob(void); + +static uint32_t PlsrHostOffsetFrequency(uint32_t frequencyHz) +{ + int64_t adjusted = (int64_t)frequencyHz + + (int64_t)PlsrHostFrequencyOffsetHz; + + if (adjusted < 1) + { + adjusted = 1; + } + if (adjusted > (int64_t)PLSR_FREQUENCY_MAX_HZ) + { + adjusted = (int64_t)PLSR_FREQUENCY_MAX_HZ; + } + return (uint32_t)adjusted; +} + static void PlsrHostLatchPulse(uint8_t pulseOutput) { if ((pulseOutput <= 3U) && (PlsrHostPulseActive[pulseOutput] != 0U)) { - PlsrHostFrequency[pulseOutput] = - PlsrHostQueuedFrequency[pulseOutput]; + if (PlsrHostCurveMismatchPending != 0U) + { + PlsrHostCurveMismatchPending = 0U; + PlsrHostDiagnosticFault = 3U; + } + else if ((PlsrHostOutputMode[pulseOutput] != PLSR_OUTPUT_AB) + || (PlsrHostAbStopPending[pulseOutput] == 0U)) + { + PlsrHostFrequency[pulseOutput] = + PlsrHostQueuedFrequency[pulseOutput]; + PlsrHostActiveSetting[pulseOutput] = + PlsrHostQueuedSetting[pulseOutput]; + } + PlsrHostObservedPulses[pulseOutput]++; PlsrHostUpdatePending[pulseOutput] = 1U; } } @@ -39,42 +110,140 @@ static void PlsrHostServicePendingPulse(uint8_t pulseOutput) && (PlsrHostUpdatePending[pulseOutput] != 0U)) { PlsrHostUpdatePending[pulseOutput] = 0U; + if ((PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrHostAbStopPending[pulseOutput] != 0U) + && (PlsrHostAbFastGated[pulseOutput] == 0U)) + { + PlsrHostAbFastGated[pulseOutput] = 1U; + PlsrHostPulseActive[pulseOutput] = 0U; + PlsrHostAbFastGateCount++; + } PlsrPulseTimerIrq(pulseOutput); } + if (PlsrHostDeferFinalArmJob == 0U) + { + PlsrHostServiceFinalArmJob(); + } +} + +static void PlsrHostServiceFinalArmJob(void) +{ + uint8_t owner; + + if (PlsrHostFinalArmJobPending == 0U) + { + return; + } + owner = PlsrHostFinalArmJobOwner; + PlsrHostFinalArmJobPending = 0U; + PlsrHostFinalArmJobOwner = 0xFFU; + PlsrFinalArmJobIrq(owner); +} + +static uint8_t PlsrHostAdvanceAbQuarter(uint8_t pulseOutput) +{ + static const uint8_t positivePhase[4] = {0U, 2U, 3U, 1U}; + static const uint8_t negativePhase[4] = {0U, 1U, 3U, 2U}; + + if ((pulseOutput > 3U) + || (PlsrHostPulseActive[pulseOutput] == 0U) + || (PlsrHostOutputMode[pulseOutput] != PLSR_OUTPUT_AB)) + { + return 0U; + } + PlsrHostAbQuarter[pulseOutput] = + (uint8_t)((PlsrHostAbQuarter[pulseOutput] + 1U) & 3U); + PlsrHostAbPhase[pulseOutput] = + (PlsrHostDirectionPositive[pulseOutput] != 0U) + ? positivePhase[PlsrHostAbQuarter[pulseOutput]] + : negativePhase[PlsrHostAbQuarter[pulseOutput]]; + PlsrHostAbTransitions[pulseOutput]++; + if (PlsrHostAbQuarter[pulseOutput] != 0U) + { + return 0U; + } + PlsrHostLatchPulse(pulseOutput); + return 1U; } uint8_t PlsrPlatformInit(void) { + uint8_t index; + (void)memset(PlsrHostPulseActive, 0, sizeof(PlsrHostPulseActive)); (void)memset(PlsrHostFrequency, 0, sizeof(PlsrHostFrequency)); (void)memset(PlsrHostQueuedFrequency, 0, sizeof(PlsrHostQueuedFrequency)); + (void)memset(PlsrHostActiveSetting, 0, + sizeof(PlsrHostActiveSetting)); + (void)memset(PlsrHostQueuedSetting, 0, + sizeof(PlsrHostQueuedSetting)); (void)memset(PlsrHostUpdatePending, 0, sizeof(PlsrHostUpdatePending)); + (void)memset(PlsrHostOutputMode, 0, sizeof(PlsrHostOutputMode)); + (void)memset(PlsrHostDirectionPositive, 0, + sizeof(PlsrHostDirectionPositive)); + (void)memset(PlsrHostAbQuarter, 0, sizeof(PlsrHostAbQuarter)); + (void)memset(PlsrHostAbPhase, 0, sizeof(PlsrHostAbPhase)); + (void)memset(PlsrHostAbTransitions, 0, + sizeof(PlsrHostAbTransitions)); + (void)memset(PlsrHostAbStopPending, 0, + sizeof(PlsrHostAbStopPending)); + (void)memset(PlsrHostAbFastGated, 0, + sizeof(PlsrHostAbFastGated)); + PlsrHostAbFastGateCount = 0UL; + PlsrHostAbCleanupCount = 0UL; + (void)memset(PlsrHostObservedPulses, 0, + sizeof(PlsrHostObservedPulses)); PlsrHostSelectedPulse = 0U; PlsrHostDirectionLevel = 0U; + for (index = 0U; index < 4U; index++) + { + PlsrHostDirectionPinLevel[index] = 1U; + PlsrHostDirectionWriteCount[index] = 0UL; + PlsrHostDirectionTransitionCount[index] = 0UL; + } PlsrHostEmitPulseOnCriticalEntry = 0U; PlsrHostEmitPulseOnCriticalExit = 0U; PlsrHostLatchPulseOnCriticalEntry = 0U; PlsrHostCriticalEntriesToSkip = 0U; + PlsrHostLatchAbFinalQuarterOnStopArm = 0U; + PlsrHostCompleteAbCycleOnQueueCommit = 0U; + PlsrHostCriticalDepth = 0UL; PlsrHostFailNextStart = 0U; + PlsrHostStaleNextFrequencyAtUpdate = 0U; PlsrHostFailNextFrequencyAtUpdate = 0U; + PlsrHostFailNextStopRequest = 0U; + PlsrHostFinalArmJobPending = 0U; + PlsrHostFinalArmJobOwner = 0xFFU; + PlsrHostDeferFinalArmJob = 0U; + PlsrHostCountOffset = 0L; + PlsrHostFrequencyOffsetHz = 0L; + PlsrHostCurveMismatchPending = 0U; + PlsrHostDiagnosticFault = 0U; return 1U; } uint8_t PlsrPlatformPrepare(uint8_t pulseOutput, uint8_t directionOutput, - uint8_t directionLevel) + uint8_t directionLevel, + uint8_t outputMode, + uint8_t directionPositive) { uint8_t index; - (void)directionOutput; + uint8_t pinLevel; if (PlsrHostFailNextStart != 0U) { PlsrHostFailNextStart = 0U; return 0U; } - if ((pulseOutput > 3U) || (directionOutput > 3U)) + if ((pulseOutput > 3U) || (directionOutput > 3U) + || (outputMode > PLSR_OUTPUT_AB) + || ((outputMode == PLSR_OUTPUT_AB) + && ((pulseOutput & 1U) != 0U)) + || (PlsrHostAbStopPending[0] != 0U) + || (PlsrHostAbStopPending[2] != 0U)) { return 0U; } @@ -84,9 +253,24 @@ uint8_t PlsrPlatformPrepare(uint8_t pulseOutput, PlsrHostFrequency[index] = 0UL; PlsrHostQueuedFrequency[index] = 0UL; PlsrHostUpdatePending[index] = 0U; + pinLevel = ((outputMode == PLSR_OUTPUT_PULSE_DIR) + && (index == directionOutput) + && (directionLevel != 0U)) ? 0U : 1U; + PlsrHostDirectionWriteCount[index]++; + if (PlsrHostDirectionPinLevel[index] != pinLevel) + { + PlsrHostDirectionTransitionCount[index]++; + } + PlsrHostDirectionPinLevel[index] = pinLevel; } PlsrHostSelectedPulse = pulseOutput; PlsrHostDirectionLevel = (directionLevel != 0U) ? 1U : 0U; + PlsrHostOutputMode[pulseOutput] = outputMode; + PlsrHostDirectionPositive[pulseOutput] = + (directionPositive != 0U) ? 1U : 0U; + PlsrHostAbQuarter[pulseOutput] = 0U; + PlsrHostAbPhase[pulseOutput] = 0U; + PlsrHostAbFastGated[pulseOutput] = 0U; return 1U; } @@ -96,44 +280,180 @@ uint8_t PlsrPlatformStartPulse(uint8_t pulseOutput, uint32_t *actualFirstFrequencyHz, uint32_t *actualQueuedFrequencyHz) { - if ((pulseOutput > 3U) || (firstFrequencyHz == 0UL) - || (firstFrequencyHz > PLSR_FREQUENCY_MAX_HZ) - || (queuedFrequencyHz == 0UL) - || (queuedFrequencyHz > PLSR_FREQUENCY_MAX_HZ) - || (actualFirstFrequencyHz == NULL) - || (actualQueuedFrequencyHz == NULL)) + PLSR_PLATFORM_TIMER_SETTING firstSetting; + PLSR_PLATFORM_TIMER_SETTING queuedSetting; + + if ((pulseOutput > 3U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrHostOutputMode[pulseOutput], + firstFrequencyHz, &firstSetting) == 0U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrHostOutputMode[pulseOutput], + queuedFrequencyHz, &queuedSetting) == 0U)) + { + return 0U; + } + return PlsrPlatformStartPrepared(pulseOutput, &firstSetting, + &queuedSetting, + actualFirstFrequencyHz, + actualQueuedFrequencyHz); +} + +uint8_t PlsrPlatformBuildTimerSetting( + uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + PLSR_PLATFORM_TIMER_SETTING *setting) +{ + if ((pulseOutput > 3U) || (outputMode > PLSR_OUTPUT_AB) + || ((outputMode == PLSR_OUTPUT_AB) + && ((pulseOutput & 1U) != 0U)) + || (requestedFrequencyHz == 0UL) + || (requestedFrequencyHz > PLSR_FREQUENCY_MAX_HZ) + || (setting == NULL)) + { + return 0U; + } + setting->actualFrequencyHz = requestedFrequencyHz; + setting->prescaler = (outputMode == PLSR_OUTPUT_AB) ? 1U : 0U; + setting->pairPrescaler = 0U; + setting->period = (outputMode == PLSR_OUTPUT_AB) ? 3U : 1U; + setting->compare = (outputMode == PLSR_OUTPUT_AB) ? 2U : 1U; + return 1U; +} + +uint8_t PlsrPlatformStartPrepared( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *firstSetting, + const PLSR_PLATFORM_TIMER_SETTING *queuedSetting, + uint32_t *actualFirstFrequencyHz, + uint32_t *actualQueuedFrequencyHz) +{ + if ((pulseOutput > 3U) || (firstSetting == NULL) + || (queuedSetting == NULL) || (actualFirstFrequencyHz == NULL) + || (actualQueuedFrequencyHz == NULL) + || (firstSetting->actualFrequencyHz == 0UL) + || (firstSetting->actualFrequencyHz > PLSR_FREQUENCY_MAX_HZ) + || (queuedSetting->actualFrequencyHz == 0UL) + || (queuedSetting->actualFrequencyHz > PLSR_FREQUENCY_MAX_HZ) + || (PlsrHostAbStopPending[pulseOutput] != 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U)) { return 0U; } PlsrHostPulseActive[pulseOutput] = 1U; - PlsrHostFrequency[pulseOutput] = firstFrequencyHz; - PlsrHostQueuedFrequency[pulseOutput] = queuedFrequencyHz; + PlsrHostFrequency[pulseOutput] = firstSetting->actualFrequencyHz; + PlsrHostQueuedFrequency[pulseOutput] = queuedSetting->actualFrequencyHz; + PlsrHostActiveSetting[pulseOutput] = *firstSetting; + PlsrHostQueuedSetting[pulseOutput] = *queuedSetting; PlsrHostUpdatePending[pulseOutput] = 0U; PlsrHostSelectedPulse = pulseOutput; - *actualFirstFrequencyHz = firstFrequencyHz; - *actualQueuedFrequencyHz = queuedFrequencyHz; + *actualFirstFrequencyHz = firstSetting->actualFrequencyHz; + *actualQueuedFrequencyHz = queuedSetting->actualFrequencyHz; return 1U; } -uint8_t PlsrPlatformQueueFrequency(uint8_t pulseOutput, - uint32_t frequencyHz, - uint32_t *actualFrequencyHz) +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformLoadPreparedFromIrq( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *setting, + uint32_t *actualFrequencyHz) { if (PlsrHostFailNextFrequencyAtUpdate != 0U) { PlsrHostFailNextFrequencyAtUpdate = 0U; - return 0U; + return PLSR_PLATFORM_QUEUE_FAILED; } - if ((pulseOutput > 3U) || (frequencyHz == 0UL) - || (frequencyHz > PLSR_FREQUENCY_MAX_HZ) + if ((pulseOutput > 3U) || (setting == NULL) || (actualFrequencyHz == NULL) - || (PlsrHostPulseActive[pulseOutput] == 0U)) + || (setting->actualFrequencyHz == 0UL) + || (setting->actualFrequencyHz > PLSR_FREQUENCY_MAX_HZ)) { - return 0U; + return PLSR_PLATFORM_QUEUE_FAILED; } - PlsrHostQueuedFrequency[pulseOutput] = frequencyHz; - *actualFrequencyHz = frequencyHz; - return 1U; + if (PlsrHostStaleNextFrequencyAtUpdate != 0U) + { + PlsrHostStaleNextFrequencyAtUpdate = 0U; + return PLSR_PLATFORM_QUEUE_STALE; + } + if ((PlsrHostCompleteAbCycleOnQueueCommit != 0U) + && (PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB)) + { + PlsrHostCompleteAbCycleOnQueueCommit = 0U; + PlsrTestEmitAbQuarters(4UL); + } + if ((PlsrHostPulseActive[pulseOutput] == 0U) + || (PlsrHostAbStopPending[pulseOutput] != 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U)) + { + return PLSR_PLATFORM_QUEUE_STALE; + } + PlsrHostQueuedSetting[pulseOutput] = *setting; + PlsrHostQueuedFrequency[pulseOutput] = setting->actualFrequencyHz; + *actualFrequencyHz = setting->actualFrequencyHz; + return PLSR_PLATFORM_QUEUE_APPLIED; +} + +void PlsrPlatformGateFromIrq(uint8_t pulseOutput) +{ + if ((pulseOutput <= 3U) + && (PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrHostAbFastGated[pulseOutput] != 0U)) + { + return; + } + PlsrPlatformStopPulse(pulseOutput); +} + +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformQueueFrequency( + uint8_t pulseOutput, + uint32_t frequencyHz, + uint32_t *actualFrequencyHz) +{ + uint32_t criticalState; + PLSR_PLATFORM_TIMER_SETTING setting; + + if (PlsrHostFailNextFrequencyAtUpdate != 0U) + { + PlsrHostFailNextFrequencyAtUpdate = 0U; + return PLSR_PLATFORM_QUEUE_FAILED; + } + if ((pulseOutput > 3U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrHostOutputMode[pulseOutput], frequencyHz, + &setting) == 0U) + || (actualFrequencyHz == NULL) + || (PlsrHostPulseActive[pulseOutput] == 0U) + || (PlsrHostAbStopPending[pulseOutput] != 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U)) + { + return PLSR_PLATFORM_QUEUE_FAILED; + } + if (PlsrHostStaleNextFrequencyAtUpdate != 0U) + { + PlsrHostStaleNextFrequencyAtUpdate = 0U; + return PLSR_PLATFORM_QUEUE_STALE; + } + + if ((PlsrHostCompleteAbCycleOnQueueCommit != 0U) + && (PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB)) + { + PlsrHostCompleteAbCycleOnQueueCommit = 0U; + PlsrTestEmitAbQuarters(4UL); + } + + criticalState = PlsrPlatformEnterCritical(); + if ((PlsrHostPulseActive[pulseOutput] == 0U) + || (PlsrHostAbStopPending[pulseOutput] != 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U)) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + PlsrHostQueuedFrequency[pulseOutput] = setting.actualFrequencyHz; + PlsrHostQueuedSetting[pulseOutput] = setting; + *actualFrequencyHz = setting.actualFrequencyHz; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_APPLIED; } void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput) @@ -143,17 +463,124 @@ void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput) uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput) { - return (pulseOutput <= 3U) ? PlsrHostFrequency[pulseOutput] : 0UL; + if (pulseOutput > 3U) + { + return 0UL; + } + return (PlsrHostFrequencyOffsetHz != 0L) + ? PlsrHostOffsetFrequency(PlsrHostFrequency[pulseOutput]) + : PlsrHostFrequency[pulseOutput]; +} + +uint8_t PlsrPlatformExpectedFrequency(uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + uint32_t *actualFrequencyHz) +{ + PLSR_PLATFORM_TIMER_SETTING setting; + + if (PlsrPlatformBuildTimerSetting(pulseOutput, outputMode, + requestedFrequencyHz, + &setting) == 0U) + { + return 0U; + } + *actualFrequencyHz = setting.actualFrequencyHz; + return 1U; +} + +uint64_t PlsrPlatformObservedPulses(uint8_t pulseOutput) +{ + int64_t observed; + + if (pulseOutput > 3U) + { + return 0UL; + } + observed = (int64_t)PlsrHostObservedPulses[pulseOutput] + + (int64_t)PlsrHostCountOffset; + return (observed > 0) ? (uint64_t)observed : 0UL; +} + +uint16_t PlsrPlatformDiagnosticFault(void) +{ + uint16_t fault = PlsrHostDiagnosticFault; + + PlsrHostDiagnosticFault = 0U; + return fault; +} + +PLSR_PLATFORM_STOP_RESULT PlsrPlatformRequestStopLocked( + uint8_t pulseOutput, + uint8_t requireZeroBoundary) +{ + if (pulseOutput > 3U) + { + return PLSR_PLATFORM_STOP_FORCED_FAULT; + } + if (PlsrHostFailNextStopRequest != 0U) + { + PlsrHostFailNextStopRequest = 0U; + PlsrPlatformStopPulse(pulseOutput); + return PLSR_PLATFORM_STOP_FORCED_FAULT; + } + if ((requireZeroBoundary != 0U) + && (PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrHostPulseActive[pulseOutput] != 0U) + && (PlsrHostAbFastGated[pulseOutput] == 0U)) + { + if (PlsrHostLatchAbFinalQuarterOnStopArm != 0U) + { + PlsrHostLatchAbFinalQuarterOnStopArm = 0U; + (void)PlsrHostAdvanceAbQuarter(pulseOutput); + } + PlsrHostQueuedFrequency[pulseOutput] = + PlsrHostFrequency[pulseOutput]; + PlsrHostAbStopPending[pulseOutput] = 1U; + return PLSR_PLATFORM_STOP_PENDING; + } + PlsrPlatformStopPulse(pulseOutput); + return PLSR_PLATFORM_STOP_COMPLETE; +} + +uint8_t PlsrPlatformQueueFinalArmFromIrq(uint8_t pulseOutput) +{ + if ((pulseOutput > 2U) || ((pulseOutput & 1U) != 0U) + || (PlsrHostOutputMode[pulseOutput] != PLSR_OUTPUT_AB) + || (PlsrHostPulseActive[pulseOutput] == 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U)) + { + return 0U; + } + PlsrHostFinalArmJobOwner = pulseOutput; + PlsrHostFinalArmJobPending = 1U; + return 1U; } void PlsrPlatformStopPulse(uint8_t pulseOutput) { if (pulseOutput <= 3U) { + if ((PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && ((PlsrHostAbStopPending[pulseOutput] != 0U) + || (PlsrHostAbFastGated[pulseOutput] != 0U))) + { + PlsrHostAbCleanupCount++; + } PlsrHostPulseActive[pulseOutput] = 0U; PlsrHostFrequency[pulseOutput] = 0UL; PlsrHostQueuedFrequency[pulseOutput] = 0UL; PlsrHostUpdatePending[pulseOutput] = 0U; + PlsrHostAbQuarter[pulseOutput] = 0U; + PlsrHostAbPhase[pulseOutput] = 0U; + PlsrHostAbStopPending[pulseOutput] = 0U; + PlsrHostAbFastGated[pulseOutput] = 0U; + PlsrHostFrequencyOffsetHz = 0L; + if (PlsrHostFinalArmJobOwner == pulseOutput) + { + PlsrHostFinalArmJobPending = 0U; + PlsrHostFinalArmJobOwner = 0xFFU; + } } } @@ -172,6 +599,21 @@ uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload) return 1U; } +void PlsrPlatformForceSafeOutputsFromFault(void) +{ + uint8_t index; + + for (index = 0U; index < 4U; index++) + { + PlsrPlatformStopPulse(index); + } +} + +PLSR_PLATFORM_SERVICE_RESULT PlsrPlatformServicePersistence(void) +{ + return PLSR_PLATFORM_SERVICE_READY; +} + uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload) { if (payload == NULL) @@ -205,6 +647,8 @@ void PlsrPlatformCheckpointPosition(int32_t position, uint32_t PlsrPlatformEnterCritical(void) { + uint32_t previousDepth = PlsrHostCriticalDepth; + if (PlsrHostEmitPulseOnCriticalEntry != 0U) { if (PlsrHostCriticalEntriesToSkip != 0U) @@ -215,7 +659,10 @@ uint32_t PlsrPlatformEnterCritical(void) { PlsrHostEmitPulseOnCriticalEntry = 0U; PlsrHostLatchPulse(PlsrHostSelectedPulse); - PlsrHostServicePendingPulse(PlsrHostSelectedPulse); + if (previousDepth == 0UL) + { + PlsrHostServicePendingPulse(PlsrHostSelectedPulse); + } } } if (PlsrHostLatchPulseOnCriticalEntry != 0U) @@ -223,12 +670,21 @@ uint32_t PlsrPlatformEnterCritical(void) PlsrHostLatchPulseOnCriticalEntry = 0U; PlsrHostLatchPulse(PlsrHostSelectedPulse); } - return 0UL; + PlsrHostCriticalDepth++; + return previousDepth; } void PlsrPlatformExitCritical(uint32_t state) { (void)state; + if (PlsrHostCriticalDepth != 0UL) + { + PlsrHostCriticalDepth--; + } + if (PlsrHostCriticalDepth != 0UL) + { + return; + } if (PlsrHostEmitPulseOnCriticalExit != 0U) { PlsrHostEmitPulseOnCriticalExit = 0U; @@ -247,6 +703,16 @@ void PlsrTestSetInput(uint8_t inputSelection, uint8_t level) void PlsrTestEmitPulses(uint32_t pulseCount) { + if (PlsrHostOutputMode[PlsrHostSelectedPulse] == PLSR_OUTPUT_AB) + { + while ((pulseCount != 0UL) + && (PlsrHostPulseActive[PlsrHostSelectedPulse] != 0U)) + { + PlsrTestEmitAbQuarters(4UL); + pulseCount--; + } + return; + } while ((pulseCount != 0UL) && (PlsrHostPulseActive[PlsrHostSelectedPulse] != 0U)) { @@ -278,6 +744,16 @@ void PlsrTestLatchPulseOnCriticalEntry(void) PlsrHostLatchPulseOnCriticalEntry = 1U; } +void PlsrTestLatchAbFinalQuarterOnNextStopArm(void) +{ + PlsrHostLatchAbFinalQuarterOnStopArm = 1U; +} + +void PlsrTestCompleteAbCycleOnNextQueueCommit(void) +{ + PlsrHostCompleteAbCycleOnQueueCommit = 1U; +} + void PlsrTestServicePendingPulse(void) { PlsrHostServicePendingPulse(PlsrHostSelectedPulse); @@ -288,11 +764,51 @@ void PlsrTestFailNextStart(void) PlsrHostFailNextStart = 1U; } +void PlsrTestServiceFinalArmJob(void) +{ + PlsrHostServiceFinalArmJob(); +} + +void PlsrTestDeferFinalArmJob(uint8_t defer) +{ + PlsrHostDeferFinalArmJob = (defer != 0U) ? 1U : 0U; + if (PlsrHostDeferFinalArmJob == 0U) + { + PlsrHostServiceFinalArmJob(); + } +} + +void PlsrTestStaleNextFrequencyAtUpdate(void) +{ + PlsrHostStaleNextFrequencyAtUpdate = 1U; +} + void PlsrTestFailNextFrequencyAtUpdate(void) { PlsrHostFailNextFrequencyAtUpdate = 1U; } +void PlsrTestFailNextStopRequest(void) +{ + PlsrHostFailNextStopRequest = 1U; +} + +void PlsrTestEmitAbQuarters(uint32_t quarterCount) +{ + uint8_t pulseOutput = PlsrHostSelectedPulse; + + while ((quarterCount != 0UL) + && (PlsrHostPulseActive[pulseOutput] != 0U) + && (PlsrHostOutputMode[pulseOutput] == PLSR_OUTPUT_AB)) + { + if (PlsrHostAdvanceAbQuarter(pulseOutput) != 0U) + { + PlsrHostServicePendingPulse(pulseOutput); + } + quarterCount--; + } +} + uint8_t PlsrTestPulseIsActive(void) { return PlsrHostPulseActive[PlsrHostSelectedPulse]; @@ -313,6 +829,60 @@ uint8_t PlsrTestDirectionLevel(void) return PlsrHostDirectionLevel; } +uint8_t PlsrTestDirectionPinLevel(uint8_t directionOutput) +{ + return (directionOutput < 4U) + ? PlsrHostDirectionPinLevel[directionOutput] : 0U; +} + +uint32_t PlsrTestDirectionWriteCount(uint8_t directionOutput) +{ + return (directionOutput < 4U) + ? PlsrHostDirectionWriteCount[directionOutput] : 0UL; +} + +uint32_t PlsrTestDirectionTransitionCount(uint8_t directionOutput) +{ + return (directionOutput < 4U) + ? PlsrHostDirectionTransitionCount[directionOutput] : 0UL; +} + +uint8_t PlsrTestAbPhase(void) +{ + return PlsrHostAbPhase[PlsrHostSelectedPulse]; +} + +uint32_t PlsrTestAbTransitionCount(void) +{ + return PlsrHostAbTransitions[PlsrHostSelectedPulse]; +} + +uint32_t PlsrTestAbFastGateCount(void) +{ + return PlsrHostAbFastGateCount; +} + +uint32_t PlsrTestAbCleanupCount(void) +{ + return PlsrHostAbCleanupCount; +} + +void PlsrTestInjectCountOffset(int32_t offset) +{ + PlsrHostCountOffset = offset; +} + +void PlsrTestInjectActiveFrequencyOffset(int32_t offsetHz) +{ + PlsrHostFrequencyOffsetHz = offsetHz; + PlsrHostDiagnosticFault = 2U; +} + +void PlsrTestInjectCurveMismatch(void) +{ + PlsrHostCurveMismatchPending = 1U; +} + void PlsrTestClearPersistentStorage(void) { (void)memset(&PlsrHostPersistentPayload, 0, @@ -320,6 +890,10 @@ void PlsrTestClearPersistentStorage(void) (void)memset(PlsrHostInputs, 0, sizeof(PlsrHostInputs)); PlsrHostPersistentValid = 0U; PlsrHostSaveCount = 0UL; + PlsrHostCountOffset = 0L; + PlsrHostFrequencyOffsetHz = 0L; + PlsrHostCurveMismatchPending = 0U; + PlsrHostDiagnosticFault = 0U; } void PlsrTestResetSaveCount(void) @@ -332,22 +906,58 @@ uint32_t PlsrTestSaveCount(void) return PlsrHostSaveCount; } +uint8_t PlsrTestFlashNeedsStartupRecovery( + uint8_t haveValidRecord, + uint8_t sectorAHasProgrammedSlot, + uint32_t sectorAFirstErasedAddress, + uint8_t sectorBHasProgrammedSlot, + uint32_t sectorBFirstErasedAddress) +{ + return PlsrFlashNeedsStartupRecovery( + haveValidRecord, + sectorAHasProgrammedSlot, + sectorAFirstErasedAddress, + sectorBHasProgrammedSlot, + sectorBFirstErasedAddress); +} + #else #include "stm32f4xx_hal.h" #include #include -#define PLSR_ENABLE_IRQ_CYCLE_DIAG (0U) +#ifndef PLSR_DEBUG_TIMING +#define PLSR_DEBUG_TIMING (0U) +#endif #define PLSR_FLASH_SLOT_A_ADDRESS (0x080C0000UL) #define PLSR_FLASH_SLOT_B_ADDRESS (0x080E0000UL) +#define PLSR_FLASH_SECTOR_SIZE (0x00020000UL) #define PLSR_FLASH_MAGIC (0x50534C52UL) -#define PLSR_FLASH_VERSION (2U) +#define PLSR_FLASH_VERSION_V2 (2U) +#define PLSR_FLASH_VERSION (3U) #define PLSR_BACKUP_CONFIG_ADDRESS (BKPSRAM_BASE + 0x0100UL) #define PLSR_BACKUP_POSITION_ADDRESS (BKPSRAM_BASE + 0x0200UL) #define PLSR_BACKUP_CONFIG_MAGIC (0x50434647UL) #define PLSR_BACKUP_POSITION_MAGIC (0x50504F53UL) +#define PLSR_CONFIG_V2_SIZE (offsetof(PLSR_CONFIG, outputMode)) +#define PLSR_COUNTER_COUNT (2U) +#define PLSR_COUNTER_NONE (0xFFU) +#define PLSR_COUNTER_BLOCK_PULSES (65536UL) +#define PLSR_PLATFORM_FAULT_FREQUENCY (2U) +#define PLSR_PLATFORM_FAULT_CURVE (3U) +#define PLSR_TIMER_OC1_MODE_MASK (7UL << TIM_CCMR1_OC1M_Pos) +#define PLSR_TIMER_PWM1_MODE (6UL << TIM_CCMR1_OC1M_Pos) +#define PLSR_STRUCTURE_VERIFY_INTERVAL (64U) +#define PLSR_FREQUENCY_VERIFY_NONE (0U) +#define PLSR_FREQUENCY_VERIFY_NOW (1U) +#define PLSR_FREQUENCY_VERIFY_AB_AUX_IRQ (2U) +#define PLSR_QUEUE_WRITE_GUARD_COUNTS (64UL) +#define PLSR_FLASH_ERASE_NONE (0U) +#define PLSR_FLASH_ERASE_SECTOR_A (1U) +#define PLSR_FLASH_ERASE_SECTOR_B (2U) +#define PLSR_FLASH_ERASE_FAILED (3U) typedef struct { @@ -376,39 +986,108 @@ typedef struct typedef struct { - uint32_t magic; - uint16_t version; - uint16_t payloadSize; - uint32_t generation; - PLSR_PERSIST_PAYLOAD payload; - uint32_t crc32; -} PLSR_FLASH_RECORD; + uint32_t basePrescaler; + uint32_t pairPrescaler; + uint32_t period; + uint32_t compare; + uint32_t actualFrequencyHz; +} PLSR_AB_SETTING; typedef struct { - uint32_t magic; - PLSR_CONFIG config; - uint32_t crc32; -} PLSR_BACKUP_CONFIG_RECORD; + uint32_t cr1; + uint32_t ccmr1; + uint32_t ccer; + uint32_t psc; + uint32_t arr; + uint32_t ccr1; +} PLSR_TIMER_SNAPSHOT; typedef struct { uint32_t magic; + uint16_t version; + uint16_t payloadSize; uint32_t generation; +} PLSR_FLASH_HEADER; + +typedef struct +{ + uint8_t config[PLSR_CONFIG_V2_SIZE]; int32_t position; uint8_t positionValid; uint8_t wasBusy; uint16_t reserved; - uint32_t crc32; -} PLSR_BACKUP_POSITION_RECORD; +} PLSR_PERSIST_PAYLOAD_V2; -static const PLSR_TIMER_MAP PlsrTimerMap[4] = +typedef struct { - {TIM10, GPIOF, GPIO_PIN_6, 6U, GPIO_AF3_TIM10, - TIM1_UP_TIM10_IRQn, 168000000UL}, - {TIM13, GPIOF, GPIO_PIN_8, 8U, GPIO_AF9_TIM13, - TIM8_UP_TIM13_IRQn, 84000000UL}, - {TIM11, GPIOF, GPIO_PIN_7, 7U, GPIO_AF3_TIM11, + uint32_t magic; + uint16_t version; + uint16_t payloadSize; + uint32_t generation; + PLSR_PERSIST_PAYLOAD payload; + uint32_t crc32; +} PLSR_FLASH_RECORD; + +typedef struct +{ + uint32_t magic; + uint16_t version; + uint16_t payloadSize; + uint32_t generation; + PLSR_PERSIST_PAYLOAD_V2 payload; + uint32_t crc32; +} PLSR_FLASH_RECORD_V2; + +#define PLSR_FLASH_RECORD_STRIDE \ + ((uint32_t)sizeof(PLSR_FLASH_RECORD)) +#define PLSR_FLASH_SLOT_COUNT \ + (PLSR_FLASH_SECTOR_SIZE / PLSR_FLASH_RECORD_STRIDE) + +typedef char PLSR_FLASH_RECORD_SIZE_MUST_BE_228[ + (sizeof(PLSR_FLASH_RECORD) == 228U) ? 1 : -1]; + +typedef struct +{ + const PLSR_FLASH_HEADER *newest; + uint32_t firstErasedAddress; + uint8_t newestVersion; + uint8_t hasProgrammedSlot; +} PLSR_FLASH_SECTOR_SCAN; + +typedef struct +{ + uint32_t magic; + PLSR_CONFIG config; + uint32_t crc32; +} PLSR_BACKUP_CONFIG_RECORD; + +typedef struct +{ + uint32_t magic; + uint8_t config[PLSR_CONFIG_V2_SIZE]; + uint32_t crc32; +} PLSR_BACKUP_CONFIG_RECORD_V2; + +typedef struct +{ + uint32_t magic; + uint32_t generation; + int32_t position; + uint8_t positionValid; + uint8_t wasBusy; + uint16_t reserved; + uint32_t crc32; +} PLSR_BACKUP_POSITION_RECORD; + +static const PLSR_TIMER_MAP PlsrTimerMap[4] = +{ + {TIM10, GPIOF, GPIO_PIN_6, 6U, GPIO_AF3_TIM10, + TIM1_UP_TIM10_IRQn, 168000000UL}, + {TIM13, GPIOF, GPIO_PIN_8, 8U, GPIO_AF9_TIM13, + TIM8_UP_TIM13_IRQn, 84000000UL}, + {TIM11, GPIOF, GPIO_PIN_7, 7U, GPIO_AF3_TIM11, TIM1_TRG_COM_TIM11_IRQn, 168000000UL}, {TIM14, GPIOF, GPIO_PIN_9, 9U, GPIO_AF9_TIM14, TIM8_TRG_COM_TIM14_IRQn, 84000000UL} @@ -423,17 +1102,67 @@ static const PLSR_GPIO_MAP PlsrDirectionMap[4] = }; static PLSR_FLASH_RECORD PlsrFlashRecordBuffer; +static uint32_t PlsrFlashNewestAddress; +static uint32_t PlsrFlashNewestGeneration; +static uint32_t PlsrFlashNextErasedAddress[2]; +static uint8_t PlsrFlashJournalInitialized; +static uint8_t PlsrFlashReserveEraseState; static uint32_t PlsrBackupPositionGeneration; static uint32_t PlsrTimerActiveFrequencyHz[4]; static uint32_t PlsrTimerQueuedFrequencyHz[4]; +static PLSR_PLATFORM_TIMER_SETTING PlsrTimerActiveSetting[4]; +static PLSR_PLATFORM_TIMER_SETTING PlsrTimerQueuedSetting[4]; static uint32_t PlsrTimerQueueGeneration[4]; +static uint8_t PlsrTimerOutputMode[4]; +static uint8_t PlsrTimerDirectionPositive[4]; +static uint8_t PlsrTimerRunning[4]; +static uint8_t PlsrFrequencyVerifyPending[4]; +static uint8_t PlsrFrequencyVerifyPulseCount[4]; +static volatile uint8_t PlsrDeferredPulsePending[4]; +static volatile uint8_t PlsrAbVerifyOwner[4]; +static volatile uint8_t PlsrAbFinalArmJobOwner[4]; +static uint8_t PlsrTimerIrqActive[4]; +static PLSR_AB_SETTING PlsrAbActiveSetting[4]; +static PLSR_AB_SETTING PlsrAbPendingSetting[4]; +static uint8_t PlsrAbFrequencyPending[4]; +static uint8_t PlsrAbLagAxis[4]; +static uint8_t PlsrAbStructureVerified[4]; +static uint8_t PlsrAbCounterSourceAxis[4]; +static uint32_t PlsrAbCounterBoundary[4]; +static volatile uint8_t PlsrAbStopPending[4]; +static volatile uint8_t PlsrAbFastGated[4]; +static TIM_TypeDef * const PlsrCounters[PLSR_COUNTER_COUNT] = +{ + TIM9, TIM12 +}; +static uint8_t PlsrCounterOwner[PLSR_COUNTER_COUNT]; +static uint8_t PlsrCounterTriggerSourceAxis[PLSR_COUNTER_COUNT]; +static volatile uint64_t PlsrCounterOverflowPulses[PLSR_COUNTER_COUNT]; +static uint8_t PlsrCounterIndexByOutput[4]; +static uint64_t PlsrObservedPulseBase[4]; +static uint64_t PlsrObservedPulsePublished[4]; +static volatile uint16_t PlsrPlatformFaultPending; static void PlsrHandleTimerIrq(uint8_t pulseOutput); +static void PlsrCounterSuspend(uint8_t pulseOutput); +static void PlsrAbFastGate(uint8_t pulseOutput); -#if PLSR_ENABLE_IRQ_CYCLE_DIAG +static uint8_t PlsrFinalArmJobOutput(uint8_t pulseOutput) +{ + return (pulseOutput == 0U) ? 2U : 0U; +} + +#if PLSR_DEBUG_TIMING volatile uint32_t PlsrIrqCount[4]; volatile uint32_t PlsrIrqLastCycles[4]; volatile uint32_t PlsrIrqMaxCycles[4]; +volatile uint32_t PlsrFinalArmQueueCount[4]; +volatile uint32_t PlsrFinalArmJobLastCycles[4]; +volatile uint32_t PlsrFinalArmJobMaxCycles[4]; +volatile uint32_t PlsrFinalArmQueueToStopLastCycles[4]; +volatile uint32_t PlsrFinalArmQueueToStopMaxCycles[4]; +static volatile uint32_t PlsrFinalArmQueuedAt[4]; +static volatile uint8_t PlsrFinalArmQueueTimingPending[4]; #endif static uint32_t PlsrCrc32(const void *data, uint32_t length) @@ -460,28 +1189,294 @@ static uint8_t PlsrGenerationIsNewer(uint32_t first, uint32_t second) return ((int32_t)(first - second) > 0) ? 1U : 0U; } -static uint32_t PlsrFlashRecordCrc(const PLSR_FLASH_RECORD *record) +static uint32_t PlsrFlashRecordCrc(const void *record, + uint32_t payloadSize) { - const uint8_t *start = (const uint8_t *)&record->version; - uint32_t length = (uint32_t)(offsetof(PLSR_FLASH_RECORD, crc32) - - offsetof(PLSR_FLASH_RECORD, version)); + const PLSR_FLASH_HEADER *header = (const PLSR_FLASH_HEADER *)record; + const uint8_t *start = (const uint8_t *)&header->version; + uint32_t length = (uint32_t)(sizeof(header->version) + + sizeof(header->payloadSize) + + sizeof(header->generation)) + + payloadSize; return PlsrCrc32(start, length); } -static uint8_t PlsrFlashRecordIsValid(const PLSR_FLASH_RECORD *record) +static uint8_t PlsrFlashRecordVersion(const void *address) +{ + const PLSR_FLASH_HEADER *header = (const PLSR_FLASH_HEADER *)address; + + if (header->magic != PLSR_FLASH_MAGIC) + { + return 0U; + } + if ((header->version == PLSR_FLASH_VERSION) + && (header->payloadSize == sizeof(PLSR_PERSIST_PAYLOAD))) + { + const PLSR_FLASH_RECORD *record = + (const PLSR_FLASH_RECORD *)address; + + return (record->crc32 + == PlsrFlashRecordCrc(record, sizeof(record->payload))) + ? PLSR_FLASH_VERSION : 0U; + } + if ((header->version == PLSR_FLASH_VERSION_V2) + && (header->payloadSize == sizeof(PLSR_PERSIST_PAYLOAD_V2))) + { + const PLSR_FLASH_RECORD_V2 *record = + (const PLSR_FLASH_RECORD_V2 *)address; + + return (record->crc32 + == PlsrFlashRecordCrc(record, sizeof(record->payload))) + ? PLSR_FLASH_VERSION_V2 : 0U; + } + return 0U; +} + +static uint8_t PlsrFlashSlotIsErased(uint32_t address) +{ + const uint32_t *words = (const uint32_t *)address; + uint32_t index; + + for (index = 0UL; + index < (PLSR_FLASH_RECORD_STRIDE / sizeof(uint32_t)); + index++) + { + if (words[index] != 0xFFFFFFFFUL) + { + return 0U; + } + } + return 1U; +} + +static uint8_t PlsrFlashSectorIsErased(uint32_t address) +{ + const uint32_t *words = (const uint32_t *)address; + uint32_t index; + + for (index = 0UL; + index < (PLSR_FLASH_SECTOR_SIZE / sizeof(uint32_t)); index++) + { + if (words[index] != 0xFFFFFFFFUL) + { + return 0U; + } + } + return 1U; +} + +static void PlsrFlashScanSector(uint32_t sectorAddress, + PLSR_FLASH_SECTOR_SCAN *scan) +{ + uint32_t index; + + (void)memset(scan, 0, sizeof(*scan)); + for (index = 0UL; index < PLSR_FLASH_SLOT_COUNT; index++) + { + uint32_t slotAddress = sectorAddress + + index * PLSR_FLASH_RECORD_STRIDE; + const PLSR_FLASH_HEADER *header = + (const PLSR_FLASH_HEADER *)slotAddress; + uint8_t version = PlsrFlashRecordVersion(header); + uint8_t erased = PlsrFlashSlotIsErased(slotAddress); + + if ((version != 0U) + && ((scan->newest == NULL) + || (PlsrGenerationIsNewer(header->generation, + scan->newest->generation) != 0U))) + { + scan->newest = header; + scan->newestVersion = version; + } + if ((scan->firstErasedAddress == 0UL) && (erased != 0U)) + { + scan->firstErasedAddress = slotAddress; + } + if (erased == 0U) + { + scan->hasProgrammedSlot = 1U; + } + } + for (index = PLSR_FLASH_SLOT_COUNT * PLSR_FLASH_RECORD_STRIDE; + index < PLSR_FLASH_SECTOR_SIZE; index += sizeof(uint32_t)) + { + if (*(const uint32_t *)(sectorAddress + index) != 0xFFFFFFFFUL) + { + scan->hasProgrammedSlot = 1U; + } + } +} + +static const PLSR_FLASH_HEADER *PlsrFlashSelectNewest( + const PLSR_FLASH_SECTOR_SCAN *scanA, + const PLSR_FLASH_SECTOR_SCAN *scanB, + uint8_t *version, + uint32_t *sectorAddress) +{ + const PLSR_FLASH_SECTOR_SCAN *selectedScan; + + if (scanA->newest == NULL) + { + selectedScan = (scanB->newest != NULL) ? scanB : NULL; + } + else if ((scanB->newest != NULL) + && (PlsrGenerationIsNewer(scanB->newest->generation, + scanA->newest->generation) != 0U)) + { + selectedScan = scanB; + } + else + { + selectedScan = scanA; + } + + if (selectedScan == NULL) + { + *version = 0U; + *sectorAddress = 0UL; + return NULL; + } + *version = selectedScan->newestVersion; + *sectorAddress = (selectedScan == scanA) + ? PLSR_FLASH_SLOT_A_ADDRESS + : PLSR_FLASH_SLOT_B_ADDRESS; + return selectedScan->newest; +} + +static const PLSR_FLASH_HEADER *PlsrFlashInitializeJournal( + PLSR_FLASH_SECTOR_SCAN *scanA, + PLSR_FLASH_SECTOR_SCAN *scanB, + uint8_t *version, + uint32_t *sectorAddress) +{ + const PLSR_FLASH_HEADER *newest; + + PlsrFlashScanSector(PLSR_FLASH_SLOT_A_ADDRESS, scanA); + PlsrFlashScanSector(PLSR_FLASH_SLOT_B_ADDRESS, scanB); + newest = PlsrFlashSelectNewest(scanA, scanB, version, sectorAddress); + PlsrFlashNextErasedAddress[0] = scanA->firstErasedAddress; + PlsrFlashNextErasedAddress[1] = scanB->firstErasedAddress; + PlsrFlashNewestAddress = (uint32_t)newest; + PlsrFlashNewestGeneration = (newest != NULL) + ? newest->generation : 0UL; + PlsrFlashJournalInitialized = 1U; + return newest; +} + +static uint8_t PlsrFlashSectorIndex(uint32_t address) +{ + return (address >= PLSR_FLASH_SLOT_B_ADDRESS) ? 1U : 0U; +} + +static uint8_t PlsrFlashAddressIsJournalSlot(uint8_t sectorIndex, + uint32_t address) +{ + uint32_t sectorAddress = (sectorIndex == 0U) + ? PLSR_FLASH_SLOT_A_ADDRESS + : PLSR_FLASH_SLOT_B_ADDRESS; + uint32_t offset; + + if ((address < sectorAddress) + || (address >= sectorAddress + PLSR_FLASH_SECTOR_SIZE)) + { + return 0U; + } + offset = address - sectorAddress; + return ((offset % PLSR_FLASH_RECORD_STRIDE) == 0UL) + && ((offset / PLSR_FLASH_RECORD_STRIDE) + < PLSR_FLASH_SLOT_COUNT) ? 1U : 0U; +} + +static uint32_t PlsrFlashFindErasedAfter(uint8_t sectorIndex, + uint32_t address) +{ + uint32_t sectorAddress = (sectorIndex == 0U) + ? PLSR_FLASH_SLOT_A_ADDRESS + : PLSR_FLASH_SLOT_B_ADDRESS; + uint32_t firstIndex = ((address - sectorAddress) + / PLSR_FLASH_RECORD_STRIDE) + 1UL; + uint32_t index; + + for (index = firstIndex; index < PLSR_FLASH_SLOT_COUNT; index++) + { + uint32_t slotAddress = sectorAddress + + index * PLSR_FLASH_RECORD_STRIDE; + + if (PlsrFlashSlotIsErased(slotAddress) != 0U) + { + return slotAddress; + } + } + return 0UL; +} + +static uint8_t PlsrFlashEraseReserve(uint8_t sectorIndex) +{ + FLASH_EraseInitTypeDef erase; + uint32_t sectorError; + HAL_StatusTypeDef status; + + if (HAL_FLASH_Unlock() != HAL_OK) + { + (void)HAL_FLASH_Lock(); + return 0U; + } + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR + | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR + | FLASH_FLAG_PGSERR); + erase.TypeErase = FLASH_TYPEERASE_SECTORS; + erase.VoltageRange = FLASH_VOLTAGE_RANGE_3; + erase.Sector = (sectorIndex == 0U) ? FLASH_SECTOR_10 : FLASH_SECTOR_11; + erase.NbSectors = 1U; + status = HAL_FLASHEx_Erase(&erase, §orError); + if ((status == HAL_OK) + && (PlsrFlashSectorIsErased((sectorIndex == 0U) + ? PLSR_FLASH_SLOT_A_ADDRESS + : PLSR_FLASH_SLOT_B_ADDRESS) == 0U)) + { + status = HAL_ERROR; + } + if (HAL_FLASH_Lock() != HAL_OK) + { + (void)HAL_FLASH_Lock(); + status = HAL_ERROR; + } + return (status == HAL_OK) ? 1U : 0U; +} + +static uint8_t PlsrBackupConfigVersion(const void *address) { - return ((record->magic == PLSR_FLASH_MAGIC) - && (record->version == PLSR_FLASH_VERSION) - && (record->payloadSize == sizeof(PLSR_PERSIST_PAYLOAD)) - && (record->crc32 == PlsrFlashRecordCrc(record))) ? 1U : 0U; + const PLSR_BACKUP_CONFIG_RECORD *record = + (const PLSR_BACKUP_CONFIG_RECORD *)address; + + if (record->magic != PLSR_BACKUP_CONFIG_MAGIC) + { + return 0U; + } + if (record->crc32 == PlsrCrc32(&record->config, sizeof(record->config))) + { + return PLSR_FLASH_VERSION; + } + { + const PLSR_BACKUP_CONFIG_RECORD_V2 *oldRecord = + (const PLSR_BACKUP_CONFIG_RECORD_V2 *)address; + + return (oldRecord->crc32 + == PlsrCrc32(oldRecord->config, sizeof(oldRecord->config))) + ? PLSR_FLASH_VERSION_V2 : 0U; + } } -static uint8_t PlsrBackupConfigIsValid( - const PLSR_BACKUP_CONFIG_RECORD *record) +static void PlsrLoadV2Payload(PLSR_PERSIST_PAYLOAD *destination, + const PLSR_PERSIST_PAYLOAD_V2 *source) { - return ((record->magic == PLSR_BACKUP_CONFIG_MAGIC) - && (record->crc32 - == PlsrCrc32(&record->config, sizeof(record->config)))) ? 1U : 0U; + (void)memset(destination, 0, sizeof(*destination)); + (void)memcpy(&destination->config, source->config, + sizeof(source->config)); + destination->config.outputMode = PLSR_OUTPUT_PULSE_DIR; + destination->position = source->position; + destination->positionValid = source->positionValid; + destination->wasBusy = source->wasBusy; } static uint8_t PlsrBackupPositionIsValid( @@ -523,10 +1518,10 @@ static const PLSR_BACKUP_POSITION_RECORD *PlsrNewestBackupPosition(void) static void PlsrTimerStop(TIM_TypeDef *timer) { - timer->DIER &= ~TIM_DIER_UIE; + timer->DIER &= ~(TIM_DIER_UIE | TIM_DIER_CC1IE); timer->CR1 &= ~TIM_CR1_CEN; - timer->CCER &= ~TIM_CCER_CC1E; - timer->SR = ~TIM_SR_UIF; + timer->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + timer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); } static void PlsrTimerInitialize(TIM_TypeDef *timer) @@ -624,8 +1619,9 @@ static uint8_t PlsrTimerCalculate(uint8_t pulseOutput, setting->prescaler = prescalerDivider - 1UL; setting->period = periodCounts - 1UL; setting->compare = periodCounts / 2UL; + denominator = prescalerDivider * periodCounts; setting->actualFrequencyHz = - map->timerClockHz / (prescalerDivider * periodCounts); + (map->timerClockHz + denominator / 2UL) / denominator; return 1U; } @@ -637,96 +1633,856 @@ static void PlsrTimerWriteSetting(TIM_TypeDef *timer, timer->CCR1 = setting->compare; } -uint8_t PlsrPlatformInit(void) +static void PlsrTimerSnapshot(TIM_TypeDef *timer, + PLSR_TIMER_SNAPSHOT *snapshot) { - GPIO_InitTypeDef gpio; - uint8_t index; - const PLSR_BACKUP_POSITION_RECORD *positionRecord; - - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_TIM10_CLK_ENABLE(); - __HAL_RCC_TIM11_CLK_ENABLE(); - __HAL_RCC_TIM13_CLK_ENABLE(); - __HAL_RCC_TIM14_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWR_EnableBkUpAccess(); - __HAL_RCC_BKPSRAM_CLK_ENABLE(); - if (HAL_PWREx_EnableBkUpReg() != HAL_OK) - { - return 0U; - } - -#if PLSR_ENABLE_IRQ_CYCLE_DIAG - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - DWT->CYCCNT = 0UL; - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - (void)memset((void *)PlsrIrqCount, 0, sizeof(PlsrIrqCount)); - (void)memset((void *)PlsrIrqLastCycles, 0, sizeof(PlsrIrqLastCycles)); - (void)memset((void *)PlsrIrqMaxCycles, 0, sizeof(PlsrIrqMaxCycles)); -#endif - - HAL_GPIO_WritePin(GPIOH, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 - | GPIO_PIN_9, GPIO_PIN_SET); - gpio.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9; - gpio.Mode = GPIO_MODE_OUTPUT_PP; - gpio.Pull = GPIO_NOPULL; - gpio.Speed = GPIO_SPEED_FREQ_HIGH; - gpio.Alternate = 0U; - HAL_GPIO_Init(GPIOH, &gpio); - - gpio.Mode = GPIO_MODE_INPUT; - gpio.Pull = GPIO_NOPULL; - gpio.Speed = GPIO_SPEED_FREQ_LOW; - gpio.Alternate = 0U; - gpio.Pin = GPIO_PIN_5; - HAL_GPIO_Init(GPIOB, &gpio); - gpio.Pin = GPIO_PIN_12; - HAL_GPIO_Init(GPIOG, &gpio); - - for (index = 0U; index < 4U; index++) - { - PlsrTimerActiveFrequencyHz[index] = 0UL; - PlsrTimerQueuedFrequencyHz[index] = 0UL; - PlsrTimerQueueGeneration[index] = 0UL; - PlsrTimerInitialize(PlsrTimerMap[index].timer); - PlsrPulsePinHoldIdle(index); - HAL_NVIC_SetPriority(PlsrTimerMap[index].irq, 1U, 0U); - HAL_NVIC_EnableIRQ(PlsrTimerMap[index].irq); - } - - positionRecord = PlsrNewestBackupPosition(); - PlsrBackupPositionGeneration = - (positionRecord == NULL) ? 0UL : positionRecord->generation; - return 1U; + snapshot->cr1 = timer->CR1; + snapshot->ccmr1 = timer->CCMR1; + snapshot->ccer = timer->CCER; + snapshot->psc = timer->PSC; + snapshot->arr = timer->ARR; + snapshot->ccr1 = timer->CCR1; } -uint8_t PlsrPlatformPrepare(uint8_t pulseOutput, - uint8_t directionOutput, - uint8_t directionLevel) +static uint8_t PlsrAbCalculate(uint8_t pulseOutput, + uint32_t frequencyHz, + PLSR_AB_SETTING *setting) { - uint8_t index; + const PLSR_TIMER_MAP *baseMap; + const PLSR_TIMER_MAP *pairMap; + uint64_t ratio; + uint64_t pairDivider; + uint64_t baseDivider; + uint64_t periodCounts; - if ((pulseOutput > 3U) || (directionOutput > 3U)) + if (((pulseOutput != 0U) && (pulseOutput != 2U)) + || (frequencyHz == 0UL) + || (frequencyHz > PLSR_FREQUENCY_MAX_HZ) + || (setting == NULL)) { return 0U; } - for (index = 0U; index < 4U; index++) + baseMap = &PlsrTimerMap[pulseOutput]; + pairMap = &PlsrTimerMap[pulseOutput + 1U]; + if ((pairMap->timerClockHz == 0UL) + || ((baseMap->timerClockHz % pairMap->timerClockHz) != 0UL)) { - PlsrPulsePinHoldIdle(index); - PlsrTimerStop(PlsrTimerMap[index].timer); - HAL_GPIO_WritePin(PlsrDirectionMap[index].port, - PlsrDirectionMap[index].pin, - GPIO_PIN_SET); + return 0U; } - if (directionLevel != 0U) + ratio = baseMap->timerClockHz / pairMap->timerClockHz; + pairDivider = ((uint64_t)pairMap->timerClockHz + + (uint64_t)frequencyHz * 65536UL - 1UL) + / ((uint64_t)frequencyHz * 65536UL); + if (pairDivider == 0UL) { - HAL_GPIO_WritePin(PlsrDirectionMap[directionOutput].port, - PlsrDirectionMap[directionOutput].pin, - GPIO_PIN_RESET); + pairDivider = 1UL; } + baseDivider = pairDivider * ratio; + if ((pairDivider > 65536UL) || (baseDivider > 65536UL)) + { + return 0U; + } + periodCounts = ((uint64_t)pairMap->timerClockHz + + ((uint64_t)frequencyHz * pairDivider) / 2UL) + / ((uint64_t)frequencyHz * pairDivider); + if ((periodCounts < 4UL) || (periodCounts > 65536UL)) + { + return 0U; + } + setting->basePrescaler = (uint32_t)(baseDivider - 1UL); + setting->pairPrescaler = (uint32_t)(pairDivider - 1UL); + setting->period = (uint32_t)(periodCounts - 1UL); + setting->compare = (uint32_t)(periodCounts / 2UL); + setting->actualFrequencyHz = + (uint32_t)(((uint64_t)pairMap->timerClockHz + + (pairDivider * periodCounts) / 2UL) + / (pairDivider * periodCounts)); + return 1U; +} + +static void PlsrAbHoldPairIdle(uint8_t pulseOutput) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + GPIO_TypeDef *port = PlsrTimerMap[pulseOutput].port; + uint32_t firstShift = (uint32_t)PlsrTimerMap[pulseOutput].pinIndex * 2UL; + uint32_t secondShift = (uint32_t)PlsrTimerMap[pairOutput].pinIndex * 2UL; + uint32_t mode = port->MODER; + + port->BSRR = (uint32_t)PlsrTimerMap[pulseOutput].pin + | (uint32_t)PlsrTimerMap[pairOutput].pin; + mode &= ~((3UL << firstShift) | (3UL << secondShift)); + mode |= (1UL << firstShift) | (1UL << secondShift); + port->MODER = mode; + __DSB(); +} + +static void PlsrAbReleasePair(uint8_t pulseOutput) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + GPIO_TypeDef *port = PlsrTimerMap[pulseOutput].port; + uint32_t firstAfrIndex = + (uint32_t)PlsrTimerMap[pulseOutput].pinIndex >> 3U; + uint32_t secondAfrIndex = + (uint32_t)PlsrTimerMap[pairOutput].pinIndex >> 3U; + uint32_t firstAfrShift = + ((uint32_t)PlsrTimerMap[pulseOutput].pinIndex & 7UL) * 4UL; + uint32_t secondAfrShift = + ((uint32_t)PlsrTimerMap[pairOutput].pinIndex & 7UL) * 4UL; + uint32_t firstShift = (uint32_t)PlsrTimerMap[pulseOutput].pinIndex * 2UL; + uint32_t secondShift = (uint32_t)PlsrTimerMap[pairOutput].pinIndex * 2UL; + uint32_t alternate; + uint32_t mode = port->MODER; + + alternate = port->AFR[firstAfrIndex]; + alternate &= ~(0xFUL << firstAfrShift); + alternate |= (uint32_t)PlsrTimerMap[pulseOutput].alternate + << firstAfrShift; + port->AFR[firstAfrIndex] = alternate; + alternate = port->AFR[secondAfrIndex]; + alternate &= ~(0xFUL << secondAfrShift); + alternate |= (uint32_t)PlsrTimerMap[pairOutput].alternate + << secondAfrShift; + port->AFR[secondAfrIndex] = alternate; + mode &= ~((3UL << firstShift) | (3UL << secondShift)); + mode |= (2UL << firstShift) | (2UL << secondShift); + port->MODER = mode; + __DSB(); +} + +static uint8_t PlsrAbStructureIsRunnable( + uint8_t pulseOutput, + const PLSR_TIMER_SNAPSHOT *base, + const PLSR_TIMER_SNAPSHOT *pair) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t lagOutput = PlsrAbLagAxis[pulseOutput]; + + return ((((base->cr1 & TIM_CR1_CEN) != 0UL) + && ((pair->cr1 & TIM_CR1_CEN) != 0UL) + && ((base->ccer & TIM_CCER_CC1E) != 0UL) + && ((pair->ccer & TIM_CCER_CC1E) != 0UL) + && ((base->ccer & TIM_CCER_CC1P) != 0UL) + && ((pair->ccer & TIM_CCER_CC1P) != 0UL) + && ((base->ccmr1 & PLSR_TIMER_OC1_MODE_MASK) + == PLSR_TIMER_PWM1_MODE) + && ((pair->ccmr1 & PLSR_TIMER_OC1_MODE_MASK) + == PLSR_TIMER_PWM1_MODE) + && (base->arr == pair->arr) + && (base->ccr1 == pair->ccr1) + && (base->ccr1 == ((base->arr + 1UL) / 2UL)) + && ((base->psc + 1UL) == 2UL * (pair->psc + 1UL)) + && ((lagOutput == pulseOutput) || (lagOutput == pairOutput))) + ? 1U : 0U); +} + +static uint8_t PlsrAbTimersAreRunnable(uint8_t pulseOutput, + TIM_TypeDef *baseTimer, + TIM_TypeDef *pairTimer) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t lagOutput = PlsrAbLagAxis[pulseOutput]; + uint32_t baseCr1 = baseTimer->CR1; + uint32_t pairCr1 = pairTimer->CR1; + uint32_t baseCcer = baseTimer->CCER; + uint32_t pairCcer = pairTimer->CCER; + uint32_t baseCcmr1 = baseTimer->CCMR1; + uint32_t pairCcmr1 = pairTimer->CCMR1; + uint32_t basePsc = baseTimer->PSC; + uint32_t pairPsc = pairTimer->PSC; + uint32_t baseCcr1 = baseTimer->CCR1; + uint32_t pairCcr1 = pairTimer->CCR1; + uint32_t baseArr = baseTimer->ARR; + uint32_t pairArr = pairTimer->ARR; + + return (((((baseCr1 & TIM_CR1_CEN) != 0UL) + && ((pairCr1 & TIM_CR1_CEN) != 0UL) + && ((baseCcer & (TIM_CCER_CC1E | TIM_CCER_CC1P)) + == (TIM_CCER_CC1E | TIM_CCER_CC1P)) + && ((pairCcer & (TIM_CCER_CC1E | TIM_CCER_CC1P)) + == (TIM_CCER_CC1E | TIM_CCER_CC1P)) + && ((baseCcmr1 & PLSR_TIMER_OC1_MODE_MASK) + == PLSR_TIMER_PWM1_MODE) + && ((pairCcmr1 & PLSR_TIMER_OC1_MODE_MASK) + == PLSR_TIMER_PWM1_MODE) + && (baseArr == pairArr) + && (baseCcr1 == pairCcr1) + && (baseCcr1 == ((baseArr + 1UL) / 2UL)) + && ((basePsc + 1UL) == 2UL * (pairPsc + 1UL)) + && ((lagOutput == pulseOutput) + || (lagOutput == pairOutput))) ? 1U : 0U)); +} + +static uint8_t PlsrAbStopBoundaryIsReachable( + uint8_t pulseOutput, + TIM_TypeDef *baseTimer, + TIM_TypeDef *pairTimer) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t lagOutput = PlsrAbLagAxis[pulseOutput]; + uint32_t baseCr1 = baseTimer->CR1; + uint32_t pairCr1 = pairTimer->CR1; + uint32_t baseCcer = baseTimer->CCER; + uint32_t pairCcer = pairTimer->CCER; + uint32_t baseCcr1 = baseTimer->CCR1; + uint32_t pairCcr1 = pairTimer->CCR1; + uint32_t baseArr = baseTimer->ARR; + uint32_t pairArr = pairTimer->ARR; + + return (((((baseCr1 & TIM_CR1_CEN) != 0UL) + && ((pairCr1 & TIM_CR1_CEN) != 0UL) + && ((baseCcer & TIM_CCER_CC1E) != 0UL) + && ((pairCcer & TIM_CCER_CC1E) != 0UL) + && (baseCcr1 <= baseArr) + && (pairCcr1 <= pairArr) + && ((lagOutput == pulseOutput) + || (lagOutput == pairOutput))) ? 1U : 0U)); +} + +static void PlsrAbFastGate(uint8_t pulseOutput) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + + PlsrAbStructureVerified[pulseOutput] = 0U; + baseTimer->CR1 &= ~TIM_CR1_CEN; + pairTimer->CR1 &= ~TIM_CR1_CEN; + PlsrCounterSuspend(pulseOutput); + __DMB(); +} + +#if defined(__ICCARM__) +#pragma inline=never +#endif +static void PlsrAbEnableTimerPair(TIM_TypeDef *firstTimer, + uint32_t firstCr1, + TIM_TypeDef *secondTimer, + uint32_t secondCr1) +{ + firstTimer->CR1 = firstCr1; + secondTimer->CR1 = secondCr1; +} + +static uint8_t PlsrAbCanFastGateAtZero(uint8_t pulseOutput) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + uint32_t baseCr1 = baseTimer->CR1; + uint32_t pairCr1 = pairTimer->CR1; + uint32_t baseCcer = baseTimer->CCER; + uint32_t pairCcer = pairTimer->CCER; + uint32_t baseCcr = baseTimer->CCR1; + uint32_t pairCcr = pairTimer->CCR1; + uint32_t baseCnt = baseTimer->CNT; + uint32_t pairCnt = pairTimer->CNT; + + return ((((baseCr1 & TIM_CR1_CEN) != 0UL) + && ((pairCr1 & TIM_CR1_CEN) != 0UL) + && ((baseCcer & TIM_CCER_CC1E) != 0UL) + && ((pairCcer & TIM_CCER_CC1E) != 0UL) + && (baseCnt >= baseCcr) + && (pairCnt >= pairCcr)) ? 1U : 0U); +} + +static uint8_t PlsrCounterIndex(uint8_t pulseOutput, uint8_t outputMode) +{ + return (outputMode == PLSR_OUTPUT_AB) + ? (uint8_t)(pulseOutput >> 1U) + : (uint8_t)(pulseOutput & 1U); +} + +static uint64_t PlsrCounterCurrentRaw(uint8_t pulseOutput) +{ + uint8_t index = PlsrCounterIndexByOutput[pulseOutput]; + TIM_TypeDef *counter; + uint64_t overflowBefore; + uint64_t overflowAfter; + uint32_t statusBefore; + uint32_t statusAfter; + uint32_t count; + + if (index >= PLSR_COUNTER_COUNT) + { + return 0UL; + } + counter = PlsrCounters[index]; + for (;;) + { + overflowBefore = PlsrCounterOverflowPulses[index]; + statusBefore = counter->SR & TIM_SR_UIF; + count = (uint16_t)counter->CNT; + statusAfter = counter->SR & TIM_SR_UIF; + overflowAfter = PlsrCounterOverflowPulses[index]; + if ((overflowBefore == overflowAfter) + && (statusBefore == statusAfter)) + { + if (statusAfter != 0UL) + { + overflowAfter += PLSR_COUNTER_BLOCK_PULSES; + } + return overflowAfter + count; + } + } +} + +static uint64_t PlsrCounterSnapshot(uint8_t pulseOutput) +{ + uint64_t current = PlsrCounterCurrentRaw(pulseOutput); + uint64_t observed; + + if ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (current > 0UL)) + { + uint8_t sourceAxis = PlsrAbCounterSourceAxis[pulseOutput]; + uint8_t attempt; + + for (attempt = 0U; attempt < 2U; attempt++) + { + uint64_t verified; + + current = PlsrCounterCurrentRaw(pulseOutput); + if (sourceAxis <= 3U) + { + uint32_t sourceCount = PlsrTimerMap[sourceAxis].timer->CNT; + + verified = PlsrCounterCurrentRaw(pulseOutput); + if (current == verified) + { + if ((sourceCount + < PlsrAbCounterBoundary[pulseOutput]) + && (current > 0UL)) + { + current--; + } + break; + } + current = verified; + } + } + } + observed = PlsrObservedPulseBase[pulseOutput] + current; + if (observed < PlsrObservedPulsePublished[pulseOutput]) + { + observed = PlsrObservedPulsePublished[pulseOutput]; + } + else + { + PlsrObservedPulsePublished[pulseOutput] = observed; + } + return observed; +} + +static uint64_t PlsrCounterSnapshotStopped(uint8_t pulseOutput) +{ + uint8_t index = PlsrCounterIndexByOutput[pulseOutput]; + TIM_TypeDef *counter = PlsrCounters[index]; + uint64_t current = PlsrCounterOverflowPulses[index]; + uint64_t observed; + + current += (uint16_t)counter->CNT; + if ((counter->SR & TIM_SR_UIF) != 0UL) + { + current += PLSR_COUNTER_BLOCK_PULSES; + } + if ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (current > 0UL)) + { + uint8_t sourceAxis = PlsrAbCounterSourceAxis[pulseOutput]; + + if ((sourceAxis <= 3U) + && (PlsrTimerMap[sourceAxis].timer->CNT + < PlsrAbCounterBoundary[pulseOutput])) + { + current--; + } + } + observed = PlsrObservedPulseBase[pulseOutput] + current; + if (observed < PlsrObservedPulsePublished[pulseOutput]) + { + observed = PlsrObservedPulsePublished[pulseOutput]; + } + else + { + PlsrObservedPulsePublished[pulseOutput] = observed; + } + return observed; +} + +static void PlsrCounterStop(uint8_t pulseOutput) +{ + uint8_t index = PlsrCounterIndexByOutput[pulseOutput]; + + if (index < PLSR_COUNTER_COUNT) + { + TIM_TypeDef *counter = PlsrCounters[index]; + + if ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrAbFastGated[pulseOutput] != 0U)) + { + PlsrObservedPulseBase[pulseOutput] = + PlsrCounterSnapshotStopped(pulseOutput); + } + else + { + PlsrCounterSuspend(pulseOutput); + PlsrObservedPulseBase[pulseOutput] = + PlsrCounterSnapshot(pulseOutput); + } + PlsrObservedPulsePublished[pulseOutput] = + PlsrObservedPulseBase[pulseOutput]; + + counter->CR1 = 0UL; + counter->DIER = 0UL; + counter->SMCR = 0UL; + counter->SR = 0UL; + if (PlsrCounterOwner[index] == pulseOutput) + { + uint8_t sourceAxis = PlsrCounterTriggerSourceAxis[index]; + + if (sourceAxis <= 3U) + { + PlsrTimerMap[sourceAxis].timer->CR2 &= ~TIM_CR2_MMS; + } + PlsrCounterTriggerSourceAxis[index] = PLSR_COUNTER_NONE; + PlsrCounterOwner[index] = PLSR_COUNTER_NONE; + } + } + PlsrCounterIndexByOutput[pulseOutput] = PLSR_COUNTER_NONE; +} + +static uint8_t PlsrCounterConfigure(uint8_t pulseOutput, uint8_t outputMode) +{ + uint8_t index = PlsrCounterIndex(pulseOutput, outputMode); + uint8_t sourceAxis = (outputMode == PLSR_OUTPUT_AB) + ? ((pulseOutput == 0U) ? 0U : 3U) + : pulseOutput; + TIM_TypeDef *counter = PlsrCounters[index]; + TIM_TypeDef *sourceTimer = PlsrTimerMap[sourceAxis].timer; + uint32_t triggerSelection = ((pulseOutput & 2U) == 0U) + ? TIM_SMCR_TS_1 + : (TIM_SMCR_TS_1 | TIM_SMCR_TS_0); + + PlsrCounterStop(pulseOutput); + if ((PlsrCounterOwner[index] != PLSR_COUNTER_NONE) + && (PlsrCounterOwner[index] != pulseOutput)) + { + return 0U; + } + PlsrCounterOwner[index] = pulseOutput; + PlsrCounterTriggerSourceAxis[index] = sourceAxis; + PlsrCounterIndexByOutput[pulseOutput] = index; + PlsrCounterOverflowPulses[index] = 0UL; + counter->CR1 = 0UL; + counter->DIER = 0UL; + counter->SMCR = 0UL; + counter->PSC = 0UL; + counter->ARR = 0xFFFFUL; + counter->CNT = 0UL; + counter->EGR = TIM_EGR_UG; + counter->SR = 0UL; + sourceTimer->CR2 = (sourceTimer->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1; + counter->SMCR = triggerSelection; + counter->DIER = TIM_DIER_UIE; + return 1U; +} + +static void PlsrCounterBegin(uint8_t pulseOutput) +{ + uint8_t index = PlsrCounterIndexByOutput[pulseOutput]; + + if (index < PLSR_COUNTER_COUNT) + { + TIM_TypeDef *counter = PlsrCounters[index]; + + counter->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; + counter->CR1 |= TIM_CR1_CEN; + } +} + +static void PlsrCounterSuspend(uint8_t pulseOutput) +{ + uint8_t index = PlsrCounterIndexByOutput[pulseOutput]; + + if (index < PLSR_COUNTER_COUNT) + { + PlsrCounters[index]->CR1 &= ~TIM_CR1_CEN; + PlsrCounters[index]->SMCR &= + ~(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0); + } +} + +static void PlsrAbLoadAndStart(uint8_t pulseOutput, + const PLSR_AB_SETTING *setting) +{ + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t leadOutput = + (PlsrTimerDirectionPositive[pulseOutput] != 0U) + ? pulseOutput : pairOutput; + uint8_t lagOutput = (leadOutput == pulseOutput) + ? pairOutput : pulseOutput; + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + TIM_TypeDef *counterSourceTimer; + TIM_TypeDef *otherTimer; + uint32_t periodCounts = setting->period + 1UL; + uint32_t leadStart = (periodCounts * 3UL) / 4UL + 1UL; + uint32_t lagStart = periodCounts / 2UL + 1UL; + uint32_t counterSourceCr1; + uint32_t otherCr1; + + if (leadStart >= periodCounts) + { + leadStart = periodCounts - 1UL; + } + if (lagStart >= periodCounts) + { + lagStart = periodCounts - 1UL; + } + PlsrAbStructureVerified[pulseOutput] = 0U; + PlsrAbLagAxis[pulseOutput] = lagOutput; + PlsrAbCounterSourceAxis[pulseOutput] = + (pulseOutput == 0U) ? pulseOutput : pairOutput; + PlsrAbCounterBoundary[pulseOutput] = + (PlsrAbCounterSourceAxis[pulseOutput] == leadOutput) + ? (leadStart - 1UL) : (periodCounts / 2UL); + + PlsrCounterSuspend(pulseOutput); + baseTimer->CR1 &= ~TIM_CR1_CEN; + pairTimer->CR1 &= ~TIM_CR1_CEN; + PlsrAbHoldPairIdle(pulseOutput); + baseTimer->CCER &= ~TIM_CCER_CC1E; + pairTimer->CCER &= ~TIM_CCER_CC1E; + baseTimer->DIER = 0UL; + pairTimer->DIER = 0UL; + baseTimer->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE; + pairTimer->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE; + baseTimer->PSC = setting->basePrescaler; + pairTimer->PSC = setting->pairPrescaler; + baseTimer->ARR = setting->period; + pairTimer->ARR = setting->period; + baseTimer->CCR1 = setting->compare; + pairTimer->CCR1 = setting->compare; + baseTimer->CR1 = TIM_CR1_ARPE | TIM_CR1_URS; + pairTimer->CR1 = TIM_CR1_ARPE | TIM_CR1_URS; + baseTimer->EGR = TIM_EGR_UG; + pairTimer->EGR = TIM_EGR_UG; + baseTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + pairTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + PlsrTimerMap[leadOutput].timer->CNT = leadStart; + PlsrTimerMap[lagOutput].timer->CNT = lagStart; + baseTimer->CCER = (baseTimer->CCER + & ~(TIM_CCER_CC1P | TIM_CCER_CC1E)) + | TIM_CCER_CC1P | TIM_CCER_CC1E; + pairTimer->CCER = (pairTimer->CCER + & ~(TIM_CCER_CC1P | TIM_CCER_CC1E)) + | TIM_CCER_CC1P | TIM_CCER_CC1E; + PlsrAbReleasePair(pulseOutput); + baseTimer->CCMR1 = TIM_CCMR1_OC1PE + | (6UL << TIM_CCMR1_OC1M_Pos); + pairTimer->CCMR1 = TIM_CCMR1_OC1PE + | (6UL << TIM_CCMR1_OC1M_Pos); + PlsrCounterBegin(pulseOutput); + counterSourceTimer = + PlsrTimerMap[PlsrAbCounterSourceAxis[pulseOutput]].timer; + otherTimer = + PlsrTimerMap[(PlsrAbCounterSourceAxis[pulseOutput] == pulseOutput) + ? pairOutput : pulseOutput].timer; + counterSourceCr1 = counterSourceTimer->CR1 | TIM_CR1_CEN; + otherCr1 = otherTimer->CR1 | TIM_CR1_CEN; + PlsrAbEnableTimerPair(counterSourceTimer, counterSourceCr1, + otherTimer, otherCr1); + baseTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + pairTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + PlsrTimerMap[lagOutput].timer->DIER |= TIM_DIER_CC1IE; + __DMB(); +} + +static void PlsrAbScheduleFrequencyVerify(uint8_t pulseOutput) +{ + uint8_t verifyOutput = + (PlsrAbLagAxis[pulseOutput] == pulseOutput) + ? (uint8_t)(pulseOutput + 1U) : pulseOutput; + TIM_TypeDef *verifyTimer = PlsrTimerMap[verifyOutput].timer; + + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_AB_AUX_IRQ; + PlsrAbVerifyOwner[verifyOutput] = pulseOutput; + verifyTimer->SR = ~TIM_SR_UIF; + verifyTimer->DIER |= TIM_DIER_UIE; + if (PlsrDeferredPulsePending[pulseOutput] != 0U) + { + verifyTimer->SR = ~TIM_SR_CC1IF; + verifyTimer->DIER |= TIM_DIER_CC1IE; + } + __DMB(); +} + +static uint32_t PlsrFrequencyFromSnapshot( + uint8_t pulseOutput, + const PLSR_TIMER_SNAPSHOT *snapshot) +{ + uint64_t divider = ((uint64_t)snapshot->psc + 1UL) + * ((uint64_t)snapshot->arr + 1UL); + + if (divider == 0UL) + { + return 0UL; + } + return (uint32_t)(((uint64_t)PlsrTimerMap[pulseOutput].timerClockHz + + divider / 2UL) + / divider); +} + +static uint32_t PlsrVerifyActiveFrequency(uint8_t pulseOutput) +{ + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + PLSR_TIMER_SNAPSHOT baseSnapshot; + uint32_t activeFrequency = PlsrTimerActiveFrequencyHz[pulseOutput]; + + PlsrTimerSnapshot(baseTimer, &baseSnapshot); + + if (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + { + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + PLSR_TIMER_SNAPSHOT pairSnapshot; + uint8_t structureValid; + + PlsrTimerSnapshot(pairTimer, &pairSnapshot); + structureValid = PlsrAbStructureIsRunnable( + pulseOutput, &baseSnapshot, &pairSnapshot); + PlsrAbStructureVerified[pulseOutput] = structureValid; + + if (structureValid == 0U) + { + PlsrPlatformFaultPending = PLSR_PLATFORM_FAULT_CURVE; + } + if ((baseSnapshot.psc + != PlsrAbActiveSetting[pulseOutput].basePrescaler) + || (pairSnapshot.psc + != PlsrAbActiveSetting[pulseOutput].pairPrescaler) + || (baseSnapshot.arr + != PlsrAbActiveSetting[pulseOutput].period) + || (pairSnapshot.arr + != PlsrAbActiveSetting[pulseOutput].period) + || (baseSnapshot.ccr1 + != PlsrAbActiveSetting[pulseOutput].compare) + || (pairSnapshot.ccr1 + != PlsrAbActiveSetting[pulseOutput].compare)) + { + activeFrequency = PlsrFrequencyFromSnapshot(pairOutput, + &pairSnapshot); + if (PlsrPlatformFaultPending != PLSR_PLATFORM_FAULT_CURVE) + { + PlsrPlatformFaultPending = PLSR_PLATFORM_FAULT_FREQUENCY; + } + } + } + else + { + uint8_t structureValid = + ((((baseSnapshot.cr1 & TIM_CR1_CEN) != 0UL) + && ((baseSnapshot.ccer & TIM_CCER_CC1E) != 0UL) + && ((baseSnapshot.ccer & TIM_CCER_CC1P) == 0UL) + && ((baseSnapshot.ccmr1 & PLSR_TIMER_OC1_MODE_MASK) + == PLSR_TIMER_PWM1_MODE) + && (baseSnapshot.ccr1 + == ((baseSnapshot.arr + 1UL) / 2UL))) + ? 1U : 0U); + + if (structureValid == 0U) + { + PlsrPlatformFaultPending = PLSR_PLATFORM_FAULT_CURVE; + } + if ((baseSnapshot.psc + != PlsrTimerQueuedSetting[pulseOutput].prescaler) + || (baseSnapshot.arr + != PlsrTimerQueuedSetting[pulseOutput].period) + || (baseSnapshot.ccr1 + != PlsrTimerQueuedSetting[pulseOutput].compare)) + { + activeFrequency = PlsrFrequencyFromSnapshot(pulseOutput, + &baseSnapshot); + if (PlsrPlatformFaultPending != PLSR_PLATFORM_FAULT_CURVE) + { + PlsrPlatformFaultPending = PLSR_PLATFORM_FAULT_FREQUENCY; + } + } + } + if (activeFrequency == 0UL) + { + PlsrPlatformFaultPending = PLSR_PLATFORM_FAULT_FREQUENCY; + } + return activeFrequency; +} + +uint8_t PlsrPlatformInit(void) +{ + GPIO_InitTypeDef gpio; + uint8_t index; + const PLSR_BACKUP_POSITION_RECORD *positionRecord; + + PlsrFlashReserveEraseState = PLSR_FLASH_ERASE_NONE; + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_TIM10_CLK_ENABLE(); + __HAL_RCC_TIM11_CLK_ENABLE(); + __HAL_RCC_TIM13_CLK_ENABLE(); + __HAL_RCC_TIM14_CLK_ENABLE(); + __HAL_RCC_TIM9_CLK_ENABLE(); + __HAL_RCC_TIM12_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_BKPSRAM_CLK_ENABLE(); + if (HAL_PWREx_EnableBkUpReg() != HAL_OK) + { + return 0U; + } + +#if PLSR_DEBUG_TIMING + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CYCCNT = 0UL; + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + (void)memset((void *)PlsrIrqCount, 0, sizeof(PlsrIrqCount)); + (void)memset((void *)PlsrIrqLastCycles, 0, sizeof(PlsrIrqLastCycles)); + (void)memset((void *)PlsrIrqMaxCycles, 0, sizeof(PlsrIrqMaxCycles)); + (void)memset((void *)PlsrFinalArmQueueCount, 0, + sizeof(PlsrFinalArmQueueCount)); + (void)memset((void *)PlsrFinalArmJobLastCycles, 0, + sizeof(PlsrFinalArmJobLastCycles)); + (void)memset((void *)PlsrFinalArmJobMaxCycles, 0, + sizeof(PlsrFinalArmJobMaxCycles)); + (void)memset((void *)PlsrFinalArmQueueToStopLastCycles, 0, + sizeof(PlsrFinalArmQueueToStopLastCycles)); + (void)memset((void *)PlsrFinalArmQueueToStopMaxCycles, 0, + sizeof(PlsrFinalArmQueueToStopMaxCycles)); + (void)memset((void *)PlsrFinalArmQueuedAt, 0, + sizeof(PlsrFinalArmQueuedAt)); + (void)memset((void *)PlsrFinalArmQueueTimingPending, 0, + sizeof(PlsrFinalArmQueueTimingPending)); +#endif + + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 + | GPIO_PIN_9, GPIO_PIN_SET); + gpio.Pin = GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9; + gpio.Mode = GPIO_MODE_OUTPUT_PP; + gpio.Pull = GPIO_NOPULL; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Alternate = 0U; + HAL_GPIO_Init(GPIOH, &gpio); + + gpio.Mode = GPIO_MODE_INPUT; + gpio.Pull = GPIO_NOPULL; + gpio.Speed = GPIO_SPEED_FREQ_LOW; + gpio.Alternate = 0U; + gpio.Pin = GPIO_PIN_5; + HAL_GPIO_Init(GPIOB, &gpio); + gpio.Pin = GPIO_PIN_12; + HAL_GPIO_Init(GPIOG, &gpio); + + for (index = 0U; index < 4U; index++) + { + PlsrTimerActiveFrequencyHz[index] = 0UL; + PlsrTimerQueuedFrequencyHz[index] = 0UL; + (void)memset(&PlsrTimerActiveSetting[index], 0, + sizeof(PlsrTimerActiveSetting[index])); + (void)memset(&PlsrTimerQueuedSetting[index], 0, + sizeof(PlsrTimerQueuedSetting[index])); + PlsrTimerQueueGeneration[index] = 0UL; + PlsrTimerOutputMode[index] = PLSR_OUTPUT_PULSE_DIR; + PlsrTimerDirectionPositive[index] = 1U; + PlsrTimerRunning[index] = 0U; + PlsrFrequencyVerifyPending[index] = 0U; + PlsrFrequencyVerifyPulseCount[index] = 0U; + PlsrDeferredPulsePending[index] = 0U; + PlsrAbVerifyOwner[index] = PLSR_COUNTER_NONE; + PlsrAbFinalArmJobOwner[index] = PLSR_COUNTER_NONE; + PlsrTimerIrqActive[index] = 0U; + PlsrAbFrequencyPending[index] = 0U; + PlsrAbLagAxis[index] = PLSR_COUNTER_NONE; + PlsrAbStructureVerified[index] = 0U; + PlsrAbCounterSourceAxis[index] = PLSR_COUNTER_NONE; + PlsrAbCounterBoundary[index] = 0UL; + PlsrAbStopPending[index] = 0U; + PlsrAbFastGated[index] = 0U; + PlsrCounterIndexByOutput[index] = PLSR_COUNTER_NONE; + PlsrObservedPulseBase[index] = 0UL; + PlsrObservedPulsePublished[index] = 0UL; + PlsrTimerInitialize(PlsrTimerMap[index].timer); + PlsrPulsePinHoldIdle(index); + HAL_NVIC_SetPriority(PlsrTimerMap[index].irq, 1U, 0U); + HAL_NVIC_EnableIRQ(PlsrTimerMap[index].irq); + } + for (index = 0U; index < PLSR_COUNTER_COUNT; index++) + { + PlsrCounterOwner[index] = PLSR_COUNTER_NONE; + PlsrCounterTriggerSourceAxis[index] = PLSR_COUNTER_NONE; + PlsrCounterOverflowPulses[index] = 0UL; + PlsrCounters[index]->CR1 = 0UL; + PlsrCounters[index]->DIER = 0UL; + PlsrCounters[index]->SMCR = 0UL; + PlsrCounters[index]->SR = 0UL; + } + PlsrPlatformFaultPending = 0U; + HAL_NVIC_SetPriority(TIM1_BRK_TIM9_IRQn, 1U, 0U); + HAL_NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn); + HAL_NVIC_SetPriority(TIM8_BRK_TIM12_IRQn, 1U, 0U); + HAL_NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn); + + positionRecord = PlsrNewestBackupPosition(); + PlsrBackupPositionGeneration = + (positionRecord == NULL) ? 0UL : positionRecord->generation; + return 1U; +} + +uint8_t PlsrPlatformPrepare(uint8_t pulseOutput, + uint8_t directionOutput, + uint8_t directionLevel, + uint8_t outputMode, + uint8_t directionPositive) +{ + uint8_t index; + + if ((pulseOutput > 3U) || (directionOutput > 3U) + || (outputMode > PLSR_OUTPUT_AB) + || ((outputMode == PLSR_OUTPUT_AB) + && (pulseOutput != 0U) && (pulseOutput != 2U))) + { + return 0U; + } + if ((PlsrAbStopPending[0] != 0U) || (PlsrAbStopPending[2] != 0U)) + { + return 0U; + } + for (index = 0U; index < 4U; index++) + { + PlsrAbFinalArmJobOwner[index] = PLSR_COUNTER_NONE; + NVIC_ClearPendingIRQ(PlsrTimerMap[index].irq); + PlsrCounterStop(index); + PlsrPulsePinHoldIdle(index); + PlsrTimerStop(PlsrTimerMap[index].timer); + HAL_GPIO_WritePin(PlsrDirectionMap[index].port, + PlsrDirectionMap[index].pin, + ((outputMode == PLSR_OUTPUT_PULSE_DIR) + && (index == directionOutput) + && (directionLevel != 0U)) + ? GPIO_PIN_RESET : GPIO_PIN_SET); + PlsrTimerRunning[index] = 0U; + PlsrFrequencyVerifyPending[index] = 0U; + PlsrFrequencyVerifyPulseCount[index] = 0U; + PlsrDeferredPulsePending[index] = 0U; + PlsrAbVerifyOwner[index] = PLSR_COUNTER_NONE; + PlsrAbFrequencyPending[index] = 0U; + PlsrAbStructureVerified[index] = 0U; + PlsrAbFastGated[index] = 0U; + } + PlsrTimerOutputMode[pulseOutput] = outputMode; + PlsrTimerDirectionPositive[pulseOutput] = + (directionPositive != 0U) ? 1U : 0U; + PlsrPlatformFaultPending = 0U; return 1U; } @@ -736,167 +2492,769 @@ uint8_t PlsrPlatformStartPulse(uint8_t pulseOutput, uint32_t *actualFirstFrequencyHz, uint32_t *actualQueuedFrequencyHz) { - TIM_TypeDef *timer; - PLSR_TIMER_SETTING firstSetting; - PLSR_TIMER_SETTING queuedSetting; + PLSR_PLATFORM_TIMER_SETTING firstSetting; + PLSR_PLATFORM_TIMER_SETTING queuedSetting; - if ((actualFirstFrequencyHz == NULL) - || (actualQueuedFrequencyHz == NULL) - || (PlsrTimerCalculate(pulseOutput, firstFrequencyHz, - &firstSetting) == 0U) - || (PlsrTimerCalculate(pulseOutput, queuedFrequencyHz, - &queuedSetting) == 0U)) + if ((pulseOutput > 3U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrTimerOutputMode[pulseOutput], + firstFrequencyHz, &firstSetting) == 0U) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrTimerOutputMode[pulseOutput], + queuedFrequencyHz, &queuedSetting) == 0U)) { return 0U; } - timer = PlsrTimerMap[pulseOutput].timer; - timer->DIER &= ~TIM_DIER_UIE; - timer->CR1 &= ~TIM_CR1_CEN; - timer->CCER &= ~TIM_CCER_CC1E; - timer->CNT = 0UL; - PlsrTimerWriteSetting(timer, &firstSetting); - timer->EGR = TIM_EGR_UG; - PlsrTimerWriteSetting(timer, &queuedSetting); - timer->SR = 0UL; - timer->CCER |= TIM_CCER_CC1E; - __DSB(); - timer->DIER |= TIM_DIER_UIE; - PlsrPulsePinRelease(pulseOutput); - timer->CR1 |= TIM_CR1_CEN; + return PlsrPlatformStartPrepared(pulseOutput, &firstSetting, + &queuedSetting, + actualFirstFrequencyHz, + actualQueuedFrequencyHz); +} + +static uint8_t PlsrPreparedSettingIsValid( + uint8_t pulseOutput, + uint8_t outputMode, + const PLSR_PLATFORM_TIMER_SETTING *setting) +{ + uint32_t periodCounts; + + if ((pulseOutput > 3U) || (setting == NULL) + || (setting->actualFrequencyHz == 0UL) + || (setting->actualFrequencyHz > PLSR_FREQUENCY_MAX_HZ)) + { + return 0U; + } + periodCounts = (uint32_t)setting->period + 1UL; + if (setting->compare != (uint16_t)(periodCounts / 2UL)) + { + return 0U; + } + if (outputMode == PLSR_OUTPUT_PULSE_DIR) + { + return ((periodCounts >= 2UL) + && (setting->pairPrescaler == 0U)) ? 1U : 0U; + } + if ((outputMode != PLSR_OUTPUT_AB) || ((pulseOutput & 1U) != 0U) + || (periodCounts < 4UL)) + { + return 0U; + } + return ((((uint32_t)setting->prescaler + 1UL) + == 2UL * ((uint32_t)setting->pairPrescaler + 1UL)) + ? 1U : 0U); +} + +static void PlsrPlatformToTimerSetting( + const PLSR_PLATFORM_TIMER_SETTING *source, + PLSR_TIMER_SETTING *destination) +{ + destination->prescaler = source->prescaler; + destination->period = source->period; + destination->compare = source->compare; + destination->actualFrequencyHz = source->actualFrequencyHz; +} + +static void PlsrPlatformToAbSetting( + const PLSR_PLATFORM_TIMER_SETTING *source, + PLSR_AB_SETTING *destination) +{ + destination->basePrescaler = source->prescaler; + destination->pairPrescaler = source->pairPrescaler; + destination->period = source->period; + destination->compare = source->compare; + destination->actualFrequencyHz = source->actualFrequencyHz; +} + +static uint8_t PlsrPlatformSettingsDiffer( + const PLSR_PLATFORM_TIMER_SETTING *first, + const PLSR_PLATFORM_TIMER_SETTING *second) +{ + return (((first->actualFrequencyHz != second->actualFrequencyHz) + || (first->prescaler != second->prescaler) + || (first->pairPrescaler != second->pairPrescaler) + || (first->period != second->period) + || (first->compare != second->compare)) ? 1U : 0U); +} + +uint8_t PlsrPlatformBuildTimerSetting( + uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + PLSR_PLATFORM_TIMER_SETTING *setting) +{ + PLSR_TIMER_SETTING timerSetting; + PLSR_AB_SETTING abSetting; + + if (setting == NULL) + { + return 0U; + } + if (outputMode == PLSR_OUTPUT_AB) + { + if (PlsrAbCalculate(pulseOutput, requestedFrequencyHz, + &abSetting) == 0U) + { + return 0U; + } + setting->actualFrequencyHz = abSetting.actualFrequencyHz; + setting->prescaler = (uint16_t)abSetting.basePrescaler; + setting->pairPrescaler = (uint16_t)abSetting.pairPrescaler; + setting->period = (uint16_t)abSetting.period; + setting->compare = (uint16_t)abSetting.compare; + return 1U; + } + if ((outputMode != PLSR_OUTPUT_PULSE_DIR) + || (PlsrTimerCalculate(pulseOutput, requestedFrequencyHz, + &timerSetting) == 0U)) + { + return 0U; + } + setting->actualFrequencyHz = timerSetting.actualFrequencyHz; + setting->prescaler = (uint16_t)timerSetting.prescaler; + setting->pairPrescaler = 0U; + setting->period = (uint16_t)timerSetting.period; + setting->compare = (uint16_t)timerSetting.compare; + return 1U; +} + +uint8_t PlsrPlatformStartPrepared( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *firstSetting, + const PLSR_PLATFORM_TIMER_SETTING *queuedSetting, + uint32_t *actualFirstFrequencyHz, + uint32_t *actualQueuedFrequencyHz) +{ + uint8_t outputMode; + + if ((pulseOutput > 3U) || (actualFirstFrequencyHz == NULL) + || (actualQueuedFrequencyHz == NULL)) + { + return 0U; + } + outputMode = PlsrTimerOutputMode[pulseOutput]; + if ((PlsrPreparedSettingIsValid(pulseOutput, outputMode, + firstSetting) == 0U) + || (PlsrPreparedSettingIsValid(pulseOutput, outputMode, + queuedSetting) == 0U)) + { + return 0U; + } + if (outputMode == PLSR_OUTPUT_AB) + { + PLSR_AB_SETTING firstAbSetting; + PLSR_AB_SETTING queuedAbSetting; + + if ((PlsrAbStopPending[pulseOutput] != 0U) + || (PlsrAbFastGated[pulseOutput] != 0U) + || (PlsrCounterConfigure(pulseOutput, PLSR_OUTPUT_AB) == 0U)) + { + return 0U; + } + PlsrPlatformToAbSetting(firstSetting, &firstAbSetting); + PlsrPlatformToAbSetting(queuedSetting, &queuedAbSetting); + PlsrAbLoadAndStart(pulseOutput, &firstAbSetting); + PlsrAbActiveSetting[pulseOutput] = firstAbSetting; + PlsrAbPendingSetting[pulseOutput] = queuedAbSetting; + PlsrAbFrequencyPending[pulseOutput] = + ((firstSetting->prescaler != queuedSetting->prescaler) + || (firstSetting->pairPrescaler + != queuedSetting->pairPrescaler) + || (firstSetting->period != queuedSetting->period)) ? 1U : 0U; + } + else + { + TIM_TypeDef *timer = PlsrTimerMap[pulseOutput].timer; + PLSR_TIMER_SETTING firstTimerSetting; + PLSR_TIMER_SETTING queuedTimerSetting; + + if (PlsrCounterConfigure(pulseOutput, + PLSR_OUTPUT_PULSE_DIR) == 0U) + { + return 0U; + } + PlsrPlatformToTimerSetting(firstSetting, &firstTimerSetting); + PlsrPlatformToTimerSetting(queuedSetting, &queuedTimerSetting); + timer->DIER &= ~TIM_DIER_UIE; + timer->CR1 &= ~TIM_CR1_CEN; + timer->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + timer->CNT = 0UL; + PlsrTimerWriteSetting(timer, &firstTimerSetting); + timer->EGR = TIM_EGR_UG; + PlsrTimerWriteSetting(timer, &queuedTimerSetting); + timer->CNT = firstTimerSetting.compare; + timer->SR = 0UL; + timer->CCER = (timer->CCER + & ~(TIM_CCER_CC1E | TIM_CCER_CC1P)) + | TIM_CCER_CC1E; + __DSB(); + timer->DIER |= TIM_DIER_UIE; + PlsrPulsePinRelease(pulseOutput); + PlsrCounterBegin(pulseOutput); + timer->CR1 |= TIM_CR1_CEN; + } + PlsrTimerActiveSetting[pulseOutput] = *firstSetting; + PlsrTimerQueuedSetting[pulseOutput] = *queuedSetting; PlsrTimerActiveFrequencyHz[pulseOutput] = - firstSetting.actualFrequencyHz; + firstSetting->actualFrequencyHz; PlsrTimerQueuedFrequencyHz[pulseOutput] = - queuedSetting.actualFrequencyHz; + queuedSetting->actualFrequencyHz; PlsrTimerQueueGeneration[pulseOutput]++; - *actualFirstFrequencyHz = firstSetting.actualFrequencyHz; - *actualQueuedFrequencyHz = queuedSetting.actualFrequencyHz; + PlsrTimerRunning[pulseOutput] = 1U; + if (outputMode == PLSR_OUTPUT_AB) + { + PlsrAbScheduleFrequencyVerify(pulseOutput); + } + else + { + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_NOW; + } + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + *actualFirstFrequencyHz = firstSetting->actualFrequencyHz; + *actualQueuedFrequencyHz = queuedSetting->actualFrequencyHz; return 1U; } -uint8_t PlsrPlatformQueueFrequency(uint8_t pulseOutput, - uint32_t frequencyHz, - uint32_t *actualFrequencyHz) +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformLoadPreparedFromIrq( + uint8_t pulseOutput, + const PLSR_PLATFORM_TIMER_SETTING *setting, + uint32_t *actualFrequencyHz) +{ + uint8_t outputMode; + + if ((pulseOutput > 3U) || (actualFrequencyHz == NULL)) + { + return PLSR_PLATFORM_QUEUE_FAILED; + } + outputMode = PlsrTimerOutputMode[pulseOutput]; + if (PlsrPreparedSettingIsValid(pulseOutput, outputMode, + setting) == 0U) + { + return PLSR_PLATFORM_QUEUE_FAILED; + } + if ((PlsrTimerRunning[pulseOutput] == 0U) + || (PlsrAbStopPending[pulseOutput] != 0U) + || (PlsrAbFastGated[pulseOutput] != 0U)) + { + return PLSR_PLATFORM_QUEUE_STALE; + } + if (outputMode == PLSR_OUTPUT_AB) + { + PLSR_AB_SETTING pending; + + PlsrPlatformToAbSetting(setting, &pending); + PlsrAbPendingSetting[pulseOutput] = pending; + PlsrAbFrequencyPending[pulseOutput] = + ((setting->prescaler + != PlsrAbActiveSetting[pulseOutput].basePrescaler) + || (setting->pairPrescaler + != PlsrAbActiveSetting[pulseOutput].pairPrescaler) + || (setting->period + != PlsrAbActiveSetting[pulseOutput].period)) ? 1U : 0U; + } + else + { + TIM_TypeDef *timer = PlsrTimerMap[pulseOutput].timer; + + if ((timer->CR1 & TIM_CR1_CEN) == 0UL) + { + return PLSR_PLATFORM_QUEUE_STALE; + } + timer->PSC = setting->prescaler; + timer->ARR = setting->period; + timer->CCR1 = setting->compare; + __DMB(); + } + PlsrTimerQueuedSetting[pulseOutput] = *setting; + PlsrTimerQueuedFrequencyHz[pulseOutput] = setting->actualFrequencyHz; + PlsrTimerQueueGeneration[pulseOutput]++; + *actualFrequencyHz = setting->actualFrequencyHz; + return PLSR_PLATFORM_QUEUE_APPLIED; +} + +void PlsrPlatformGateFromIrq(uint8_t pulseOutput) +{ + if ((pulseOutput <= 3U) + && (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrAbFastGated[pulseOutput] != 0U)) + { + return; + } + PlsrPlatformStopPulse(pulseOutput); +} + +PLSR_PLATFORM_QUEUE_RESULT PlsrPlatformQueueFrequency( + uint8_t pulseOutput, + uint32_t frequencyHz, + uint32_t *actualFrequencyHz) { TIM_TypeDef *timer; - PLSR_TIMER_SETTING setting; - uint32_t counterBefore; - uint32_t counterAfter; - uint32_t counterFinal; + PLSR_PLATFORM_TIMER_SETTING setting; + uint32_t activePeriod; + uint32_t counter; uint32_t criticalState; - uint32_t generationBefore; uint32_t ownGeneration; - uint8_t wrappedWhileUpdatesDisabled; + uint8_t updatePending; if ((pulseOutput > 3U) || (actualFrequencyHz == NULL) - || (PlsrTimerCalculate(pulseOutput, frequencyHz, &setting) == 0U)) + || (PlsrPlatformBuildTimerSetting( + pulseOutput, PlsrTimerOutputMode[pulseOutput], frequencyHz, + &setting) == 0U)) { - return 0U; + return PLSR_PLATFORM_QUEUE_FAILED; + } + if (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + { + PLSR_AB_SETTING pending; + uint32_t criticalState; + + if ((PlsrTimerRunning[pulseOutput] == 0U) + || (PlsrAbStopPending[pulseOutput] != 0U) + || (PlsrAbFastGated[pulseOutput] != 0U)) + { + return PLSR_PLATFORM_QUEUE_STALE; + } + criticalState = PlsrPlatformEnterCritical(); + if ((PlsrTimerRunning[pulseOutput] == 0U) + || (PlsrAbStopPending[pulseOutput] != 0U) + || (PlsrAbFastGated[pulseOutput] != 0U)) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + PlsrPlatformToAbSetting(&setting, &pending); + PlsrAbPendingSetting[pulseOutput] = pending; + PlsrAbFrequencyPending[pulseOutput] = + ((pending.basePrescaler + != PlsrAbActiveSetting[pulseOutput].basePrescaler) + || (pending.pairPrescaler + != PlsrAbActiveSetting[pulseOutput].pairPrescaler) + || (pending.period + != PlsrAbActiveSetting[pulseOutput].period)) ? 1U : 0U; + PlsrTimerQueuedSetting[pulseOutput] = setting; + PlsrTimerQueuedFrequencyHz[pulseOutput] = setting.actualFrequencyHz; + PlsrTimerQueueGeneration[pulseOutput]++; + *actualFrequencyHz = setting.actualFrequencyHz; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_APPLIED; } + timer = PlsrTimerMap[pulseOutput].timer; if ((timer->CR1 & TIM_CR1_CEN) == 0UL) { - return 0U; + return PLSR_PLATFORM_QUEUE_STALE; + } + + criticalState = PlsrPlatformEnterCritical(); + if ((timer->SR & TIM_SR_UIF) != 0UL) + { + *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput]; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + activePeriod = PlsrTimerActiveSetting[pulseOutput].period; + counter = timer->CNT; + if ((counter > activePeriod) + || ((activePeriod - counter) < PLSR_QUEUE_WRITE_GUARD_COUNTS)) + { + *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput]; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + + /* Preserve real update events and their TRGO pulse while replacing the + three preload registers. The near-wrap guard bounds the write window. */ + timer->PSC = setting.prescaler; + timer->ARR = setting.period; + timer->CCR1 = setting.compare; + __DMB(); + updatePending = ((timer->SR & TIM_SR_UIF) != 0UL) ? 1U : 0U; + PlsrTimerQueuedFrequencyHz[pulseOutput] = setting.actualFrequencyHz; + PlsrTimerQueuedSetting[pulseOutput] = setting; + PlsrTimerQueueGeneration[pulseOutput]++; + ownGeneration = PlsrTimerQueueGeneration[pulseOutput]; + if (updatePending != 0U) + { + *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput]; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + *actualFrequencyHz = + (PlsrTimerQueueGeneration[pulseOutput] == ownGeneration) + ? setting.actualFrequencyHz + : PlsrTimerQueuedFrequencyHz[pulseOutput]; + if (PlsrTimerQueueGeneration[pulseOutput] != ownGeneration) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_STALE; + } + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_QUEUE_APPLIED; +} + +void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput) +{ + if (pulseOutput <= 3U) + { + if ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrDeferredPulsePending[pulseOutput] != 0U)) + { + uint8_t verifyOutput = + (PlsrAbLagAxis[pulseOutput] == pulseOutput) + ? (uint8_t)(pulseOutput + 1U) : pulseOutput; + TIM_TypeDef *verifyTimer = PlsrTimerMap[verifyOutput].timer; + + verifyTimer->DIER &= ~(TIM_DIER_UIE | TIM_DIER_CC1IE); + verifyTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + PlsrAbVerifyOwner[verifyOutput] = PLSR_COUNTER_NONE; + if (PlsrFrequencyVerifyPending[pulseOutput] + == PLSR_FREQUENCY_VERIFY_AB_AUX_IRQ) + { + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + (void)PlsrVerifyActiveFrequency(pulseOutput); + } + PlsrDeferredPulsePending[pulseOutput] = 0U; + PlsrPulseTimerIrq(pulseOutput); + return; + } + PlsrHandleTimerIrq(pulseOutput); + } +} + +uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput) +{ + if (pulseOutput > 3U) + { + return 0UL; + } + if ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrAbFastGated[pulseOutput] != 0U)) + { + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + return PlsrTimerActiveFrequencyHz[pulseOutput]; + } + if (PlsrFrequencyVerifyPending[pulseOutput] + == PLSR_FREQUENCY_VERIFY_AB_AUX_IRQ) + { + return PlsrTimerActiveFrequencyHz[pulseOutput]; + } + if (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + { + PlsrFrequencyVerifyPulseCount[pulseOutput]++; + if (PlsrFrequencyVerifyPulseCount[pulseOutput] + >= PLSR_STRUCTURE_VERIFY_INTERVAL) + { + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + PlsrAbScheduleFrequencyVerify(pulseOutput); + } + return PlsrTimerActiveFrequencyHz[pulseOutput]; + } + if (PlsrFrequencyVerifyPending[pulseOutput] + == PLSR_FREQUENCY_VERIFY_NOW) + { + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + return PlsrVerifyActiveFrequency(pulseOutput); + } + PlsrFrequencyVerifyPulseCount[pulseOutput]++; + if (PlsrFrequencyVerifyPulseCount[pulseOutput] + >= PLSR_STRUCTURE_VERIFY_INTERVAL) + { + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + return PlsrVerifyActiveFrequency(pulseOutput); + } + return PlsrTimerActiveFrequencyHz[pulseOutput]; +} + +uint8_t PlsrPlatformExpectedFrequency(uint8_t pulseOutput, + uint8_t outputMode, + uint32_t requestedFrequencyHz, + uint32_t *actualFrequencyHz) +{ + PLSR_PLATFORM_TIMER_SETTING setting; + + if (actualFrequencyHz == NULL) + { + return 0U; + } + if (PlsrPlatformBuildTimerSetting(pulseOutput, outputMode, + requestedFrequencyHz, + &setting) == 0U) + { + return 0U; + } + *actualFrequencyHz = setting.actualFrequencyHz; + return 1U; +} + +uint64_t PlsrPlatformObservedPulses(uint8_t pulseOutput) +{ + uint32_t criticalState; + uint64_t observed; + + if (pulseOutput > 3U) + { + return 0UL; + } + criticalState = PlsrPlatformEnterCritical(); + if (PlsrCounterIndexByOutput[pulseOutput] < PLSR_COUNTER_COUNT) + { + observed = ((PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrAbFastGated[pulseOutput] != 0U)) + ? PlsrCounterSnapshotStopped(pulseOutput) + : PlsrCounterSnapshot(pulseOutput); + } + else + { + observed = PlsrObservedPulseBase[pulseOutput]; + } + PlsrPlatformExitCritical(criticalState); + return observed; +} + +uint16_t PlsrPlatformDiagnosticFault(void) +{ + uint16_t fault = PlsrPlatformFaultPending; + + PlsrPlatformFaultPending = 0U; + return fault; +} + +PLSR_PLATFORM_STOP_RESULT PlsrPlatformRequestStopLocked( + uint8_t pulseOutput, + uint8_t requireZeroBoundary) +{ + if (pulseOutput > 3U) + { + return PLSR_PLATFORM_STOP_FORCED_FAULT; } - - criticalState = PlsrPlatformEnterCritical(); - generationBefore = PlsrTimerQueueGeneration[pulseOutput]; - if ((timer->SR & TIM_SR_UIF) != 0UL) + if ((requireZeroBoundary != 0U) + && (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + && (PlsrTimerRunning[pulseOutput] != 0U) + && (PlsrAbFastGated[pulseOutput] == 0U)) { - PlsrHandleTimerIrq(pulseOutput); - if (PlsrTimerQueueGeneration[pulseOutput] != generationBefore) + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t lagOutput = PlsrAbLagAxis[pulseOutput]; + uint32_t activeFrequencyHz; + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + uint8_t structureRunnable = + ((PlsrAbStructureVerified[pulseOutput] != 0U) + && (PlsrFrequencyVerifyPending[pulseOutput] + == PLSR_FREQUENCY_VERIFY_NONE)) + ? PlsrAbStopBoundaryIsReachable(pulseOutput, baseTimer, + pairTimer) + : PlsrAbTimersAreRunnable(pulseOutput, baseTimer, + pairTimer); + + if (structureRunnable == 0U) { - *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput]; - PlsrPlatformExitCritical(criticalState); - return 1U; + PlsrCounterSuspend(pulseOutput); + PlsrAbHoldPairIdle(pulseOutput); + baseTimer->CR1 &= ~TIM_CR1_CEN; + pairTimer->CR1 &= ~TIM_CR1_CEN; + __DMB(); + PlsrPlatformStopPulse(pulseOutput); + return PLSR_PLATFORM_STOP_FORCED_FAULT; } - if ((timer->CR1 & TIM_CR1_CEN) == 0UL) + if (PlsrAbStopPending[pulseOutput] != 0U) { - PlsrPlatformExitCritical(criticalState); - return 0U; + return PLSR_PLATFORM_STOP_PENDING; } - } - /* UDIS blocks shadow transfers while the three preload registers are - replaced. The counter and PWM output continue without interruption. */ - counterBefore = timer->CNT; - timer->CR1 |= TIM_CR1_UDIS; - __DMB(); - if ((timer->SR & TIM_SR_UIF) != 0UL) - { - timer->CR1 &= ~TIM_CR1_UDIS; - PlsrHandleTimerIrq(pulseOutput); - if ((PlsrTimerQueueGeneration[pulseOutput] != generationBefore) - || ((timer->CR1 & TIM_CR1_CEN) == 0UL)) + PlsrAbFrequencyPending[pulseOutput] = 0U; + baseTimer->DIER &= ~TIM_DIER_UIE; + pairTimer->DIER &= ~TIM_DIER_UIE; + PlsrFrequencyVerifyPending[pulseOutput] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrFrequencyVerifyPulseCount[pulseOutput] = 0U; + PlsrAbVerifyOwner[pulseOutput] = PLSR_COUNTER_NONE; + PlsrAbVerifyOwner[pairOutput] = PLSR_COUNTER_NONE; + activeFrequencyHz = PlsrTimerActiveFrequencyHz[pulseOutput]; + PlsrTimerQueuedFrequencyHz[pulseOutput] = activeFrequencyHz; + PlsrTimerQueueGeneration[pulseOutput]++; + PlsrAbStopPending[pulseOutput] = 1U; +#if PLSR_DEBUG_TIMING + if (PlsrFinalArmQueueTimingPending[pulseOutput] != 0U) { - uint8_t stillRunning = - ((timer->CR1 & TIM_CR1_CEN) != 0UL) ? 1U : 0U; + uint32_t queuedAt = PlsrFinalArmQueuedAt[pulseOutput]; + uint32_t stoppedAt = DWT->CYCCNT; + uint32_t latency = stoppedAt - queuedAt; - *actualFrequencyHz = PlsrTimerQueuedFrequencyHz[pulseOutput]; - PlsrPlatformExitCritical(criticalState); - return stillRunning; + PlsrFinalArmQueueTimingPending[pulseOutput] = 0U; + PlsrFinalArmQueueToStopLastCycles[pulseOutput] = latency; + if (latency > PlsrFinalArmQueueToStopMaxCycles[pulseOutput]) + { + PlsrFinalArmQueueToStopMaxCycles[pulseOutput] = latency; + } + } +#endif + if (lagOutput == pulseOutput) + { + pairTimer->SR = ~TIM_SR_CC1IF; + } + else + { + baseTimer->SR = ~TIM_SR_CC1IF; } - counterBefore = timer->CNT; - timer->CR1 |= TIM_CR1_UDIS; + baseTimer->DIER |= TIM_DIER_CC1IE; + pairTimer->DIER |= TIM_DIER_CC1IE; __DMB(); + return PLSR_PLATFORM_STOP_PENDING; } - PlsrTimerWriteSetting(timer, &setting); - __DMB(); - PlsrTimerQueuedFrequencyHz[pulseOutput] = setting.actualFrequencyHz; - PlsrTimerQueueGeneration[pulseOutput]++; - ownGeneration = PlsrTimerQueueGeneration[pulseOutput]; - counterAfter = timer->CNT; - timer->CR1 &= ~TIM_CR1_UDIS; - __DMB(); - counterFinal = timer->CNT; + PlsrPlatformStopPulse(pulseOutput); + return PLSR_PLATFORM_STOP_COMPLETE; +} + +uint8_t PlsrPlatformQueueFinalArmFromIrq(uint8_t pulseOutput) +{ + uint8_t jobOutput; - /* With UDIS set an overflow does not set UIF. A wrapped counter proves - that its real output edge occurred, so account for that edge once. */ - wrappedWhileUpdatesDisabled = - ((counterAfter < counterBefore) - || ((counterFinal < counterAfter) - && ((timer->SR & TIM_SR_UIF) == 0UL))) ? 1U : 0U; - if (wrappedWhileUpdatesDisabled != 0U) + if ((pulseOutput > 2U) || ((pulseOutput & 1U) != 0U) + || (PlsrTimerOutputMode[pulseOutput] != PLSR_OUTPUT_AB) + || (PlsrTimerRunning[pulseOutput] == 0U) + || (PlsrAbFastGated[pulseOutput] != 0U)) { - PlsrPulseTimerIrq(pulseOutput); + return 0U; } - else if ((timer->SR & TIM_SR_UIF) != 0UL) + jobOutput = PlsrFinalArmJobOutput(pulseOutput); + if (PlsrAbFinalArmJobOwner[jobOutput] != PLSR_COUNTER_NONE) { - PlsrHandleTimerIrq(pulseOutput); + return 0U; } - *actualFrequencyHz = - (PlsrTimerQueueGeneration[pulseOutput] == ownGeneration) - ? setting.actualFrequencyHz - : PlsrTimerQueuedFrequencyHz[pulseOutput]; - PlsrPlatformExitCritical(criticalState); + PlsrAbFinalArmJobOwner[jobOutput] = pulseOutput; +#if PLSR_DEBUG_TIMING + PlsrFinalArmQueuedAt[pulseOutput] = DWT->CYCCNT; + PlsrFinalArmQueueTimingPending[pulseOutput] = 1U; + PlsrFinalArmQueueCount[pulseOutput]++; +#endif + __DMB(); + NVIC_SetPendingIRQ(PlsrTimerMap[jobOutput].irq); return 1U; } -void PlsrPlatformDrainPendingPulse(uint8_t pulseOutput) -{ - if (pulseOutput <= 3U) - { - PlsrHandleTimerIrq(pulseOutput); - } -} - -uint32_t PlsrPlatformActiveFrequency(uint8_t pulseOutput) -{ - return (pulseOutput <= 3U) - ? PlsrTimerActiveFrequencyHz[pulseOutput] : 0UL; -} - void PlsrPlatformStopPulse(uint8_t pulseOutput) { if (pulseOutput <= 3U) { - PlsrPulsePinCaptureIdle(pulseOutput); - PlsrTimerStop(PlsrTimerMap[pulseOutput].timer); + if (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + { + uint8_t pairOutput = (uint8_t)(pulseOutput + 1U); + uint8_t jobOutput = PlsrFinalArmJobOutput(pulseOutput); + TIM_TypeDef *baseTimer = PlsrTimerMap[pulseOutput].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + + PlsrAbStructureVerified[pulseOutput] = 0U; + PlsrAbFinalArmJobOwner[jobOutput] = PLSR_COUNTER_NONE; +#if PLSR_DEBUG_TIMING + PlsrFinalArmQueueTimingPending[pulseOutput] = 0U; +#endif + NVIC_ClearPendingIRQ(PlsrTimerMap[jobOutput].irq); + if (PlsrAbFastGated[pulseOutput] != 0U) + { + PlsrAbHoldPairIdle(pulseOutput); + baseTimer->DIER = 0UL; + pairTimer->DIER = 0UL; + baseTimer->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + pairTimer->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + baseTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + pairTimer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + } + else + { + PlsrCounterSuspend(pulseOutput); + PlsrAbHoldPairIdle(pulseOutput); + PlsrTimerStop(baseTimer); + PlsrTimerStop(pairTimer); + } + } + else + { + PlsrPulsePinCaptureIdle(pulseOutput); + PlsrTimerStop(PlsrTimerMap[pulseOutput].timer); + } + PlsrCounterStop(pulseOutput); PlsrTimerActiveFrequencyHz[pulseOutput] = 0UL; PlsrTimerQueuedFrequencyHz[pulseOutput] = 0UL; PlsrTimerQueueGeneration[pulseOutput]++; + PlsrTimerRunning[pulseOutput] = 0U; + PlsrFrequencyVerifyPending[pulseOutput] = 0U; + PlsrDeferredPulsePending[pulseOutput] = 0U; + PlsrAbVerifyOwner[pulseOutput] = PLSR_COUNTER_NONE; + if (PlsrTimerOutputMode[pulseOutput] == PLSR_OUTPUT_AB) + { + PlsrAbVerifyOwner[pulseOutput + 1U] = PLSR_COUNTER_NONE; + } + PlsrAbFrequencyPending[pulseOutput] = 0U; + PlsrAbStopPending[pulseOutput] = 0U; + PlsrAbFastGated[pulseOutput] = 0U; } } +void PlsrPlatformForceSafeOutputsFromFault(void) +{ + uint32_t mode; + const uint32_t outputPins = GPIO_PIN_6 | GPIO_PIN_7 + | GPIO_PIN_8 | GPIO_PIN_9; + const uint32_t outputModeMask = (3UL << (6U * 2U)) + | (3UL << (7U * 2U)) + | (3UL << (8U * 2U)) + | (3UL << (9U * 2U)); + + __disable_irq(); + + TIM10->DIER = 0UL; + TIM10->CR1 &= ~TIM_CR1_CEN; + TIM10->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + TIM10->SR = 0UL; + TIM11->DIER = 0UL; + TIM11->CR1 &= ~TIM_CR1_CEN; + TIM11->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + TIM11->SR = 0UL; + TIM13->DIER = 0UL; + TIM13->CR1 &= ~TIM_CR1_CEN; + TIM13->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + TIM13->SR = 0UL; + TIM14->DIER = 0UL; + TIM14->CR1 &= ~TIM_CR1_CEN; + TIM14->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC1P); + TIM14->SR = 0UL; + + TIM9->DIER = 0UL; + TIM9->CR1 &= ~TIM_CR1_CEN; + TIM9->SMCR = 0UL; + TIM9->SR = 0UL; + TIM12->DIER = 0UL; + TIM12->CR1 &= ~TIM_CR1_CEN; + TIM12->SMCR = 0UL; + TIM12->SR = 0UL; + + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOHEN; + __DSB(); + GPIOF->BSRR = outputPins; + GPIOH->BSRR = outputPins; + GPIOF->OTYPER &= ~outputPins; + GPIOH->OTYPER &= ~outputPins; + GPIOF->PUPDR &= ~outputModeMask; + GPIOH->PUPDR &= ~outputModeMask; + mode = GPIOF->MODER; + mode &= ~outputModeMask; + mode |= (1UL << (6U * 2U)) | (1UL << (7U * 2U)) + | (1UL << (8U * 2U)) | (1UL << (9U * 2U)); + GPIOF->MODER = mode; + mode = GPIOH->MODER; + mode &= ~outputModeMask; + mode |= (1UL << (6U * 2U)) | (1UL << (7U * 2U)) + | (1UL << (8U * 2U)) | (1UL << (9U * 2U)); + GPIOH->MODER = mode; + __DSB(); +} + uint8_t PlsrPlatformReadInput(uint8_t inputSelection) { if (inputSelection == 0U) @@ -912,43 +3270,36 @@ uint8_t PlsrPlatformReadInput(uint8_t inputSelection) uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload) { - const PLSR_FLASH_RECORD *slotA = - (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_A_ADDRESS; - const PLSR_FLASH_RECORD *slotB = - (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_B_ADDRESS; - const PLSR_FLASH_RECORD *selected = NULL; - const PLSR_BACKUP_CONFIG_RECORD *backupConfig = - (const PLSR_BACKUP_CONFIG_RECORD *)PLSR_BACKUP_CONFIG_ADDRESS; + PLSR_FLASH_SECTOR_SCAN scanA; + PLSR_FLASH_SECTOR_SCAN scanB; + const PLSR_FLASH_HEADER *selected = NULL; + const void *backupConfig = (const void *)PLSR_BACKUP_CONFIG_ADDRESS; const PLSR_BACKUP_POSITION_RECORD *backupPosition; - uint8_t validA; - uint8_t validB; + uint8_t selectedVersion = 0U; + uint8_t backupVersion; uint8_t haveConfig = 0U; + uint32_t selectedSectorAddress; if (payload == NULL) { return 0U; } - validA = PlsrFlashRecordIsValid(slotA); - validB = PlsrFlashRecordIsValid(slotB); - if ((validA != 0U) && (validB != 0U)) - { - selected = (PlsrGenerationIsNewer(slotB->generation, - slotA->generation) != 0U) - ? slotB : slotA; - } - else if (validA != 0U) - { - selected = slotA; - } - else if (validB != 0U) - { - selected = slotB; - } + selected = PlsrFlashInitializeJournal(&scanA, &scanB, &selectedVersion, + &selectedSectorAddress); if (selected != NULL) { - *payload = selected->payload; + if (selectedVersion == PLSR_FLASH_VERSION) + { + *payload = ((const PLSR_FLASH_RECORD *)selected)->payload; + } + else + { + PlsrLoadV2Payload( + payload, + &((const PLSR_FLASH_RECORD_V2 *)selected)->payload); + } haveConfig = 1U; } else @@ -956,9 +3307,21 @@ uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload) (void)memset(payload, 0, sizeof(*payload)); } - if (PlsrBackupConfigIsValid(backupConfig) != 0U) + backupVersion = PlsrBackupConfigVersion(backupConfig); + if (backupVersion == PLSR_FLASH_VERSION) + { + payload->config = + ((const PLSR_BACKUP_CONFIG_RECORD *)backupConfig)->config; + haveConfig = 1U; + } + else if (backupVersion == PLSR_FLASH_VERSION_V2) { - payload->config = backupConfig->config; + const PLSR_BACKUP_CONFIG_RECORD_V2 *oldConfig = + (const PLSR_BACKUP_CONFIG_RECORD_V2 *)backupConfig; + + (void)memcpy(&payload->config, oldConfig->config, + sizeof(oldConfig->config)); + payload->config.outputMode = PLSR_OUTPUT_PULSE_DIR; haveConfig = 1U; } backupPosition = PlsrNewestBackupPosition(); @@ -968,25 +3331,93 @@ uint8_t PlsrPlatformLoad(PLSR_PERSIST_PAYLOAD *payload) payload->positionValid = backupPosition->positionValid; payload->wasBusy = backupPosition->wasBusy; } + + if (selected != NULL) + { + uint8_t reserveIndex = + (selectedSectorAddress == PLSR_FLASH_SLOT_A_ADDRESS) ? 1U : 0U; + const PLSR_FLASH_SECTOR_SCAN *reserveScan = + (reserveIndex == 0U) ? &scanA : &scanB; + + if (reserveScan->hasProgrammedSlot != 0U) + { + PlsrFlashReserveEraseState = (uint8_t)(reserveIndex + 1U); + } + } + else if (PlsrFlashNeedsStartupRecovery( + 0U, + scanA.hasProgrammedSlot, + scanA.firstErasedAddress, + scanB.hasProgrammedSlot, + scanB.firstErasedAddress) != 0U) + { + PlsrFlashReserveEraseState = PLSR_FLASH_ERASE_SECTOR_A; + } return haveConfig; } +PLSR_PLATFORM_SERVICE_RESULT PlsrPlatformServicePersistence(void) +{ + uint32_t criticalState; + uint8_t eraseState; + uint8_t sectorIndex; + uint8_t index; + + criticalState = PlsrPlatformEnterCritical(); + eraseState = PlsrFlashReserveEraseState; + if (eraseState == PLSR_FLASH_ERASE_FAILED) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_SERVICE_FAILED; + } + if (eraseState == PLSR_FLASH_ERASE_NONE) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_SERVICE_READY; + } + if ((eraseState < PLSR_FLASH_ERASE_SECTOR_A) + || (eraseState > PLSR_FLASH_ERASE_SECTOR_B)) + { + PlsrFlashReserveEraseState = PLSR_FLASH_ERASE_FAILED; + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_SERVICE_FAILED; + } + for (index = 0U; index < 4U; index++) + { + if ((PlsrTimerRunning[index] != 0U) + || (PlsrTimerIrqActive[index] != 0U)) + { + PlsrPlatformExitCritical(criticalState); + return PLSR_PLATFORM_SERVICE_DEFERRED; + } + } + sectorIndex = (uint8_t)(eraseState - PLSR_FLASH_ERASE_SECTOR_A); + PlsrPlatformExitCritical(criticalState); + + if (PlsrFlashEraseReserve(sectorIndex) == 0U) + { + PlsrFlashReserveEraseState = PLSR_FLASH_ERASE_FAILED; + return PLSR_PLATFORM_SERVICE_FAILED; + } + + PlsrFlashNextErasedAddress[sectorIndex] = + (sectorIndex == 0U) ? PLSR_FLASH_SLOT_A_ADDRESS + : PLSR_FLASH_SLOT_B_ADDRESS; + PlsrFlashReserveEraseState = PLSR_FLASH_ERASE_NONE; + return PLSR_PLATFORM_SERVICE_READY; +} + uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload) { - const PLSR_FLASH_RECORD *slotA = - (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_A_ADDRESS; - const PLSR_FLASH_RECORD *slotB = - (const PLSR_FLASH_RECORD *)PLSR_FLASH_SLOT_B_ADDRESS; - uint8_t validA; - uint8_t validB; - uint32_t newestGeneration = 0UL; + PLSR_FLASH_SECTOR_SCAN scanA; + PLSR_FLASH_SECTOR_SCAN scanB; + uint8_t newestVersion; + uint32_t newestSectorAddress; + uint8_t targetIndex; uint32_t targetAddress; - uint32_t targetSector; - uint32_t sectorError; uint32_t index; uint32_t wordCount; const uint32_t *words; - FLASH_EraseInitTypeDef erase; HAL_StatusTypeDef status = HAL_OK; if (payload == NULL) @@ -994,65 +3425,88 @@ uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload) return 0U; } - validA = PlsrFlashRecordIsValid(slotA); - validB = PlsrFlashRecordIsValid(slotB); - if ((validA != 0U) && (validB != 0U)) + if (PlsrFlashJournalInitialized == 0U) { - if (PlsrGenerationIsNewer(slotB->generation, slotA->generation) != 0U) - { - newestGeneration = slotB->generation; - targetAddress = PLSR_FLASH_SLOT_A_ADDRESS; - targetSector = FLASH_SECTOR_10; - } - else + (void)PlsrFlashInitializeJournal(&scanA, &scanB, &newestVersion, + &newestSectorAddress); + (void)newestVersion; + (void)newestSectorAddress; + } + + if (PlsrFlashNewestAddress != 0UL) + { + targetIndex = PlsrFlashSectorIndex(PlsrFlashNewestAddress); + if (PlsrFlashNextErasedAddress[targetIndex] == 0UL) { - newestGeneration = slotA->generation; - targetAddress = PLSR_FLASH_SLOT_B_ADDRESS; - targetSector = FLASH_SECTOR_11; + targetIndex ^= 1U; } } - else if (validA != 0U) + else if (PlsrFlashNextErasedAddress[0] != 0UL) + { + targetIndex = 0U; + } + else { - newestGeneration = slotA->generation; - targetAddress = PLSR_FLASH_SLOT_B_ADDRESS; - targetSector = FLASH_SECTOR_11; + targetIndex = 1U; } - else if (validB != 0U) + + targetAddress = PlsrFlashNextErasedAddress[targetIndex]; + if ((targetAddress != 0UL) + && ((PlsrFlashAddressIsJournalSlot(targetIndex, targetAddress) == 0U) + || (PlsrFlashSlotIsErased(targetAddress) == 0U))) { - newestGeneration = slotB->generation; - targetAddress = PLSR_FLASH_SLOT_A_ADDRESS; - targetSector = FLASH_SECTOR_10; + targetAddress = 0UL; + PlsrFlashNextErasedAddress[targetIndex] = 0UL; } - else + if (targetAddress == 0UL) { - targetAddress = PLSR_FLASH_SLOT_A_ADDRESS; - targetSector = FLASH_SECTOR_10; + uint8_t newestIndex = (PlsrFlashNewestAddress != 0UL) + ? PlsrFlashSectorIndex( + PlsrFlashNewestAddress) + : 0xFFU; + uint8_t alternateIndex = targetIndex ^ 1U; + + if ((targetIndex == newestIndex) + || (PlsrFlashNextErasedAddress[alternateIndex] != 0UL)) + { + targetIndex = alternateIndex; + targetAddress = PlsrFlashNextErasedAddress[targetIndex]; + if ((targetAddress != 0UL) + && ((PlsrFlashAddressIsJournalSlot(targetIndex, + targetAddress) == 0U) + || (PlsrFlashSlotIsErased(targetAddress) == 0U))) + { + targetAddress = 0UL; + PlsrFlashNextErasedAddress[targetIndex] = 0UL; + } + } + if (targetAddress == 0UL) + { + return 0U; + } } + PlsrFlashNextErasedAddress[targetIndex] = + PlsrFlashFindErasedAfter(targetIndex, targetAddress); + (void)memset(&PlsrFlashRecordBuffer, 0, sizeof(PlsrFlashRecordBuffer)); PlsrFlashRecordBuffer.magic = PLSR_FLASH_MAGIC; PlsrFlashRecordBuffer.version = PLSR_FLASH_VERSION; PlsrFlashRecordBuffer.payloadSize = sizeof(PLSR_PERSIST_PAYLOAD); - PlsrFlashRecordBuffer.generation = newestGeneration + 1UL; + PlsrFlashRecordBuffer.generation = PlsrFlashNewestGeneration + 1UL; PlsrFlashRecordBuffer.payload = *payload; - PlsrFlashRecordBuffer.crc32 = PlsrFlashRecordCrc(&PlsrFlashRecordBuffer); + PlsrFlashRecordBuffer.crc32 = + PlsrFlashRecordCrc(&PlsrFlashRecordBuffer, + sizeof(PlsrFlashRecordBuffer.payload)); if (HAL_FLASH_Unlock() != HAL_OK) { + (void)HAL_FLASH_Lock(); return 0U; } __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); - erase.TypeErase = FLASH_TYPEERASE_SECTORS; - erase.VoltageRange = FLASH_VOLTAGE_RANGE_3; - erase.Sector = targetSector; - erase.NbSectors = 1U; - if (HAL_FLASHEx_Erase(&erase, §orError) != HAL_OK) - { - status = HAL_ERROR; - } - words = (const uint32_t *)&PlsrFlashRecordBuffer; wordCount = sizeof(PlsrFlashRecordBuffer) / sizeof(uint32_t); if (status == HAL_OK) @@ -1076,14 +3530,16 @@ uint8_t PlsrPlatformSave(const PLSR_PERSIST_PAYLOAD *payload) } if (HAL_FLASH_Lock() != HAL_OK) { + (void)HAL_FLASH_Lock(); status = HAL_ERROR; } - if ((status == HAL_OK) - && (PlsrFlashRecordIsValid( - (const PLSR_FLASH_RECORD *)targetAddress) != 0U)) + if (PlsrFlashRecordVersion((const void *)targetAddress) + == PLSR_FLASH_VERSION) { - return 1U; + PlsrFlashNewestAddress = targetAddress; + PlsrFlashNewestGeneration = PlsrFlashRecordBuffer.generation; + return (status == HAL_OK) ? 1U : 0U; } return 0U; } @@ -1151,52 +3607,273 @@ void PlsrPlatformExitCritical(uint32_t state) static void PlsrHandleTimerIrq(uint8_t pulseOutput) { - TIM_TypeDef *timer = PlsrTimerMap[pulseOutput].timer; -#if PLSR_ENABLE_IRQ_CYCLE_DIAG + TIM_TypeDef *timer; +#if PLSR_DEBUG_TIMING uint32_t startedAt; uint32_t elapsedCycles; + uint8_t timingOutput = pulseOutput; + + startedAt = DWT->CYCCNT; +#endif + timer = PlsrTimerMap[pulseOutput].timer; + + if (PlsrTimerIrqActive[pulseOutput] != 0U) + { +#if PLSR_DEBUG_TIMING + goto irq_record; +#else + return; +#endif + } + PlsrTimerIrqActive[pulseOutput] = 1U; + + if (((timer->SR & TIM_SR_CC1IF) != 0UL) + && ((timer->DIER & TIM_DIER_CC1IE) != 0UL)) + { + uint8_t owner = ((pulseOutput & 2U) == 0U) ? 0U : 2U; + +#if PLSR_DEBUG_TIMING + timingOutput = owner; #endif + timer->SR = ~TIM_SR_CC1IF; + if ((owner <= 2U) + && (PlsrTimerRunning[owner] != 0U) + && (PlsrTimerOutputMode[owner] == PLSR_OUTPUT_AB)) + { + uint8_t pairOutput = (uint8_t)(owner + 1U); + TIM_TypeDef *baseTimer = PlsrTimerMap[owner].timer; + TIM_TypeDef *pairTimer = PlsrTimerMap[pairOutput].timer; + PLSR_AB_SETTING pending; + + if (PlsrAbStopPending[owner] != 0U) + { + if (PlsrAbCanFastGateAtZero(owner) == 0U) + { + goto irq_done; + } + baseTimer->DIER &= ~(TIM_DIER_CC1IE | TIM_DIER_UIE); + pairTimer->DIER &= ~(TIM_DIER_CC1IE | TIM_DIER_UIE); + baseTimer->SR = ~TIM_SR_CC1IF; + pairTimer->SR = ~TIM_SR_CC1IF; + PlsrFrequencyVerifyPending[owner] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrAbVerifyOwner[owner] = PLSR_COUNTER_NONE; + PlsrAbVerifyOwner[pairOutput] = PLSR_COUNTER_NONE; + PlsrAbFastGate(owner); + PlsrAbFastGated[owner] = 1U; + PlsrDeferredPulsePending[owner] = 0U; + PlsrPulseTimerIrq(owner); + goto irq_done; + } + if (pulseOutput != PlsrAbLagAxis[owner]) + { + if (PlsrDeferredPulsePending[owner] != 0U) + { + PlsrDeferredPulsePending[owner] = 0U; + timer->DIER &= ~TIM_DIER_CC1IE; + PlsrPulseTimerIrq(owner); + } + goto irq_done; + } + if (PlsrDeferredPulsePending[owner] != 0U) + { + goto irq_done; + } + if (PlsrAbFrequencyPending[owner] != 0U) + { + pending = PlsrAbPendingSetting[owner]; + PlsrAbFrequencyPending[owner] = 0U; + PlsrAbLoadAndStart(owner, &pending); + PlsrAbActiveSetting[owner] = pending; + PlsrTimerActiveSetting[owner] = + PlsrTimerQueuedSetting[owner]; + PlsrTimerActiveFrequencyHz[owner] = + pending.actualFrequencyHz; + PlsrDeferredPulsePending[owner] = 1U; + PlsrAbScheduleFrequencyVerify(owner); + goto irq_done; + } + PlsrPulseTimerIrq(owner); + } + goto irq_done; + } if (((timer->SR & TIM_SR_UIF) != 0UL) && ((timer->DIER & TIM_DIER_UIE) != 0UL)) { -#if PLSR_ENABLE_IRQ_CYCLE_DIAG - startedAt = DWT->CYCCNT; -#endif - timer->SR = ~TIM_SR_UIF; - PlsrTimerActiveFrequencyHz[pulseOutput] = - PlsrTimerQueuedFrequencyHz[pulseOutput]; - PlsrPulseTimerIrq(pulseOutput); -#if PLSR_ENABLE_IRQ_CYCLE_DIAG - elapsedCycles = DWT->CYCCNT - startedAt; - PlsrIrqCount[pulseOutput]++; - PlsrIrqLastCycles[pulseOutput] = elapsedCycles; - if (elapsedCycles > PlsrIrqMaxCycles[pulseOutput]) + timer->SR = ~(TIM_SR_UIF | TIM_SR_CC1IF); + if (PlsrPlatformSettingsDiffer( + &PlsrTimerActiveSetting[pulseOutput], + &PlsrTimerQueuedSetting[pulseOutput]) != 0U) { - PlsrIrqMaxCycles[pulseOutput] = elapsedCycles; + PlsrFrequencyVerifyPending[pulseOutput] = 1U; + PlsrTimerActiveFrequencyHz[pulseOutput] = + PlsrTimerQueuedFrequencyHz[pulseOutput]; + PlsrTimerActiveSetting[pulseOutput] = + PlsrTimerQueuedSetting[pulseOutput]; } + PlsrPulseTimerIrq(pulseOutput); + } +irq_done: + PlsrTimerIrqActive[pulseOutput] = 0U; +#if PLSR_DEBUG_TIMING +irq_record: + elapsedCycles = DWT->CYCCNT - startedAt; + PlsrIrqCount[timingOutput]++; + PlsrIrqLastCycles[timingOutput] = elapsedCycles; + if (elapsedCycles > PlsrIrqMaxCycles[timingOutput]) + { + PlsrIrqMaxCycles[timingOutput] = elapsedCycles; + } +#endif +} + +static uint8_t PlsrHandleScheduledAbVerify(uint8_t pulseOutput) +{ + uint8_t verifyOwner = PlsrAbVerifyOwner[pulseOutput]; + TIM_TypeDef *timer; +#if PLSR_DEBUG_TIMING + uint32_t startedAt; + uint32_t elapsedCycles; #endif + + if (verifyOwner > 2U) + { + return 0U; + } + timer = PlsrTimerMap[pulseOutput].timer; + if (((timer->SR & TIM_SR_UIF) == 0UL) + || ((timer->DIER & TIM_DIER_UIE) == 0UL)) + { + return 0U; + } +#if PLSR_DEBUG_TIMING + startedAt = DWT->CYCCNT; +#endif + timer->SR = ~TIM_SR_UIF; + timer->DIER &= ~TIM_DIER_UIE; + PlsrAbVerifyOwner[pulseOutput] = PLSR_COUNTER_NONE; + if (PlsrFrequencyVerifyPending[verifyOwner] + == PLSR_FREQUENCY_VERIFY_AB_AUX_IRQ) + { + PlsrFrequencyVerifyPending[verifyOwner] = + PLSR_FREQUENCY_VERIFY_NONE; + PlsrFrequencyVerifyPulseCount[verifyOwner] = 0U; + (void)PlsrVerifyActiveFrequency(verifyOwner); + } +#if PLSR_DEBUG_TIMING + elapsedCycles = DWT->CYCCNT - startedAt; + PlsrIrqCount[verifyOwner]++; + PlsrIrqLastCycles[verifyOwner] = elapsedCycles; + if (elapsedCycles > PlsrIrqMaxCycles[verifyOwner]) + { + PlsrIrqMaxCycles[verifyOwner] = elapsedCycles; + } +#endif + return 1U; +} + +static uint8_t PlsrFinalStopIrqIsPending(uint8_t pulseOutput) +{ + uint8_t owner = ((pulseOutput & 2U) == 0U) ? 0U : 2U; + TIM_TypeDef *timer = PlsrTimerMap[pulseOutput].timer; + + return ((PlsrAbStopPending[owner] != 0U) + && ((timer->SR & TIM_SR_CC1IF) != 0UL) + && ((timer->DIER & TIM_DIER_CC1IE) != 0UL)) ? 1U : 0U; +} + +static uint8_t PlsrHandleFinalArmJob(uint8_t pulseOutput) +{ + uint8_t owner = PlsrAbFinalArmJobOwner[pulseOutput]; +#if PLSR_DEBUG_TIMING + uint32_t startedAt; + uint32_t elapsedCycles; +#endif + + if (owner > 2U) + { + return 0U; + } + PlsrAbFinalArmJobOwner[pulseOutput] = PLSR_COUNTER_NONE; +#if PLSR_DEBUG_TIMING + startedAt = DWT->CYCCNT; +#endif + PlsrFinalArmJobIrq(owner); +#if PLSR_DEBUG_TIMING + elapsedCycles = DWT->CYCCNT - startedAt; + PlsrFinalArmJobLastCycles[owner] = elapsedCycles; + if (elapsedCycles > PlsrFinalArmJobMaxCycles[owner]) + { + PlsrFinalArmJobMaxCycles[owner] = elapsedCycles; + } +#endif + return 1U; +} + +static void PlsrDispatchTimerIrq(uint8_t pulseOutput) +{ + if (PlsrFinalStopIrqIsPending(pulseOutput) != 0U) + { + PlsrHandleTimerIrq(pulseOutput); + return; + } + if (PlsrHandleFinalArmJob(pulseOutput) != 0U) + { + return; + } + if (PlsrHandleScheduledAbVerify(pulseOutput) == 0U) + { + PlsrHandleTimerIrq(pulseOutput); } } void TIM1_UP_TIM10_IRQHandler(void) { - PlsrHandleTimerIrq(0U); + PlsrDispatchTimerIrq(0U); } void TIM8_UP_TIM13_IRQHandler(void) { - PlsrHandleTimerIrq(1U); + PlsrDispatchTimerIrq(1U); } void TIM1_TRG_COM_TIM11_IRQHandler(void) { - PlsrHandleTimerIrq(2U); + PlsrDispatchTimerIrq(2U); } void TIM8_TRG_COM_TIM14_IRQHandler(void) { - PlsrHandleTimerIrq(3U); + PlsrDispatchTimerIrq(3U); +} + +static void PlsrHandleCounterIrq(uint8_t counterIndex) +{ + TIM_TypeDef *counter; + + if (counterIndex >= PLSR_COUNTER_COUNT) + { + return; + } + counter = PlsrCounters[counterIndex]; + if (((counter->SR & TIM_SR_UIF) != 0UL) + && ((counter->DIER & TIM_DIER_UIE) != 0UL)) + { + counter->SR = ~TIM_SR_UIF; + PlsrCounterOverflowPulses[counterIndex] += + PLSR_COUNTER_BLOCK_PULSES; + } +} + +void TIM1_BRK_TIM9_IRQHandler(void) +{ + PlsrHandleCounterIrq(0U); +} + +void TIM8_BRK_TIM12_IRQHandler(void) +{ + PlsrHandleCounterIrq(1U); } #endif /* PLSR_HOST_TEST */ diff --git a/tests/plsr_host/test_plsr_host.c b/tests/plsr_host/test_plsr_host.c index 033b6bd..1113634 100644 --- a/tests/plsr_host/test_plsr_host.c +++ b/tests/plsr_host/test_plsr_host.c @@ -17,8 +17,51 @@ #define PLSR_COMMAND_START (0x0001U) #define PLSR_COMMAND_STOP (0x0002U) #define PLSR_COMMAND_CLEAR (0x0004U) +#define PLSR_ERROR_TIMER (4U) #define PLSR_ERROR_COUNT (5U) +#define PLSR_OUTPUT_MODE_PULSE_DIR (0U) +#define PLSR_OUTPUT_MODE_AB (1U) + +#define PLSR_DIAG_FLAGS_ADDRESS (0x2100U) +#define PLSR_DIAG_REASON_ADDRESS (0x2101U) +#define PLSR_DIAG_SEGMENT_ADDRESS (0x2102U) +#define PLSR_DIAG_MODE_DIRECTION_ADDRESS (0x2103U) +#define PLSR_DIAG_EXPECTED_COUNT_ADDRESS (0x2104U) +#define PLSR_DIAG_OBSERVED_COUNT_ADDRESS (0x2106U) +#define PLSR_DIAG_COUNT_ERROR_ADDRESS (0x2108U) +#define PLSR_DIAG_REQUESTED_FREQUENCY_ADDRESS (0x210AU) +#define PLSR_DIAG_EXPECTED_TIMER_ADDRESS (0x210CU) +#define PLSR_DIAG_ACTIVE_TIMER_ADDRESS (0x210EU) +#define PLSR_DIAG_REQUEST_ERROR_ADDRESS (0x2110U) +#define PLSR_DIAG_SAMPLE_COUNT_ADDRESS (0x2112U) +#define PLSR_DIAG_MISMATCH_COUNT_ADDRESS (0x2114U) +#define PLSR_DIAG_MAX_ERROR_ADDRESS (0x2116U) +#define PLSR_DIAG_FIRST_MISMATCH_ADDRESS (0x2118U) + +#define PLSR_DIAG_MONITORING_ACTIVE (0x0001U) +#define PLSR_DIAG_COUNT_CHECKED (0x0002U) +#define PLSR_DIAG_COUNT_PASS (0x0004U) +#define PLSR_DIAG_FREQUENCY_CHECKED (0x0008U) +#define PLSR_DIAG_FREQUENCY_PASS (0x0010U) +#define PLSR_DIAG_CURVE_CHECKED (0x0020U) +#define PLSR_DIAG_CURVE_PASS (0x0040U) +#define PLSR_DIAG_FAULT_LATCHED (0x0080U) + +#define PLSR_DIAG_REASON_NONE (0U) +#define PLSR_DIAG_REASON_COUNT (1U) +#define PLSR_DIAG_REASON_FREQUENCY (2U) +#define PLSR_DIAG_REASON_CURVE (3U) + +void PlsrTestSetDiagnosticCurveCounts(uint32_t sampleCount, + uint32_t mismatchCount); +uint8_t PlsrTestFlashNeedsStartupRecovery( + uint8_t haveValidRecord, + uint8_t sectorAHasProgrammedSlot, + uint32_t sectorAFirstErasedAddress, + uint8_t sectorBHasProgrammedSlot, + uint32_t sectorBFirstErasedAddress); + static const char *CurrentTest; static unsigned int AssertionCount; static unsigned int FailureCount; @@ -204,6 +247,11 @@ static uint32_t ReadU32(uint16_t address) return (uint32_t)words[0] | ((uint32_t)words[1] << 16U); } +static int32_t ReadI32(uint16_t address) +{ + return (int32_t)ReadU32(address); +} + static int32_t ReadPosition(void) { return (int32_t)ReadU32(PLSR_STATUS_FIRST_ADDRESS); @@ -337,12 +385,20 @@ static void TestProtocolBoundaries(void) PlsrModbusReadHolding(0x0FFEU, 1U, &value)); EXPECT_U(PLSR_MB_NOT_HANDLED, PlsrModbusReadHolding(0x1198U, 1U, &value)); + EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, + PlsrModbusReadHolding(0x11FFU, 2U, values)); + EXPECT_U(PLSR_MB_NOT_HANDLED, + PlsrModbusReadHolding(0x1201U, 1U, &value)); EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusReadHolding(0x0FFFU, 2U, values)); EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusReadHolding(0x1197U, 2U, values)); EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusReadHolding(0x2006U, 2U, values)); + EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, + PlsrModbusReadHolding(0x2119U, 2U, values)); + EXPECT_U(PLSR_MB_NOT_HANDLED, + PlsrModbusReadHolding(0x211AU, 1U, &value)); EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusReadHolding(0xFFFFU, 2U, values)); EXPECT_U(PLSR_MB_ILLEGAL_VALUE, @@ -372,6 +428,9 @@ static void TestProtocolBoundaries(void) EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusWriteHolding(0x2000U, 1U, &value)); + EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, + PlsrModbusWriteHolding(PLSR_DIAGNOSTIC_FIRST_ADDRESS, + 1U, &value)); EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, PlsrModbusWriteHolding(0x3000U, 2U, values)); value = 3U; @@ -385,207 +444,1479 @@ static void TestProtocolBoundaries(void) EXPECT_U(PLSR_MB_OK, WriteWord(0x1197U, 0U)); EXPECT_U(0U, ReadWord(0x1197U)); EXPECT_U(PLSR_MB_NOT_HANDLED, WriteWord(0x1198U, 0U)); + + EXPECT_U(PLSR_OUTPUT_MODE_PULSE_DIR, + ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + EXPECT_U(PLSR_MB_OK, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_OUTPUT_MODE_AB, ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, 2U)); + EXPECT_U(PLSR_OUTPUT_MODE_AB, ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + + EXPECT_U(0U, ReadWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS)); + EXPECT_U(PLSR_MB_OK, WriteWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, 0U)); + EXPECT_U(PLSR_MB_OK, WriteWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, 1U)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, + WriteWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, 2U)); + EXPECT_U(PLSR_MB_ILLEGAL_ADDRESS, + PlsrModbusWriteHolding(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, + 2U, values)); + EXPECT_U(0U, ReadWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS)); } -static void TestWaitZeroUsesOneMillisecond(void) +static void ConfigureAbMotion(uint16_t pulseOutput, + int32_t pulses, + uint32_t frequencyHz, + uint32_t startStopFrequencyHz, + uint16_t accelerationTimeMs, + uint16_t decelerationTimeMs) { - ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + frequencyHz, startStopFrequencyHz, + startStopFrequencyHz, accelerationTimeMs, + decelerationTimeMs); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, pulseOutput)); EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 1L, PLSR_WAIT_TIME, 0U, 0U, 0U)); + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); EXPECT_U(PLSR_MB_OK, - SetSegment(2U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + SetSegment(1U, frequencyHz, pulses, PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - PlsrTestEmitPulses(1UL); +} - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_WAITING, ReadStatus()); - EXPECT_U(1U, ReadCurrentSegment()); - EXPECT_U(0U, PlsrTestPulseIsActive()); +static void ExpectDiagnosticCleared(void) +{ + uint16_t words[0x1AU]; + uint16_t index; - PlsrPoll1ms(); - EXPECT_U(2U, ReadCurrentSegment()); - EXPECT_U(1U, PlsrTestPulseIsActive()); - PlsrTestEmitPulses(1UL); - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_I(2L, ReadPosition()); + EXPECT_U(PLSR_MB_OK, + PlsrModbusReadHolding(PLSR_DIAGNOSTIC_FIRST_ADDRESS, + 0x1AU, words)); + for (index = 0U; index < 0x18U; index++) + { + EXPECT_U(0U, words[index]); + } + EXPECT_U(0xFFFFU, words[0x18U]); + EXPECT_U(0xFFFFU, words[0x19U]); } -static void TestActZeroSkipsWithoutPulse(void) +static void ClearDiagnostic(void) { - ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 100L, PLSR_ACT_TIME, 0U, 0U, 0U)); - EXPECT_U(PLSR_MB_OK, - SetSegment(2U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); + WriteWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, 1U)); + ExpectDiagnosticCleared(); +} + +static void ExpectDiagnosticInterrupted(uint32_t expectedCycles, + uint32_t observedCycles) +{ + uint16_t flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + + EXPECT_U(0U, flags & PLSR_DIAG_MONITORING_ACTIVE); + EXPECT_U(0U, flags & (PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS)); + EXPECT_U(0U, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_NONE, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_U(expectedCycles, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(observedCycles, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); +} + +static void TestAbOutputPairsAndPhaseSequence(void) +{ + static const uint8_t positivePhases[4] = {2U, 3U, 1U, 0U}; + static const uint8_t negativePhases[4] = {1U, 3U, 2U, 0U}; + uint32_t transitionsBefore; + uint16_t quarter; + + ResetCore(); + ConfigureAbMotion(0U, 2L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, 3U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 250U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1006U, 1U)); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0U, PlsrTestAbTransitionCount()); EXPECT_U(1U, ReadCurrentSegment()); - EXPECT_I(0L, ReadPosition()); + EXPECT_U(0x0101U, ReadWord(PLSR_DIAG_MODE_DIRECTION_ADDRESS)); - PlsrPoll1ms(); - EXPECT_U(2U, ReadCurrentSegment()); + for (quarter = 0U; quarter < 4U; quarter++) + { + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(positivePhases[quarter], PlsrTestAbPhase()); + EXPECT_U((uint32_t)quarter + 1UL, + PlsrTestAbTransitionCount()); + EXPECT_I((quarter == 3U) ? 1L : 0L, ReadPosition()); + } EXPECT_U(1U, PlsrTestPulseIsActive()); - EXPECT_I(0L, ReadPosition()); + + transitionsBefore = PlsrTestAbTransitionCount(); PlsrTestEmitPulses(1UL); + EXPECT_U(transitionsBefore + 4UL, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0U, PlsrTestPulseIsActive()); PlsrPoll1ms(); EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_I(1L, ReadPosition()); -} + EXPECT_I(2L, ReadPosition()); -static void TestRelativeAndAbsoluteZeroDisplacement(void) -{ ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 0L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); + ConfigureAbMotion(2U, -1L, 2000UL, 2000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, 0U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 250U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1006U, 1U)); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0x0001U, ReadWord(PLSR_DIAG_MODE_DIRECTION_ADDRESS)); + for (quarter = 0U; quarter < 4U; quarter++) + { + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(negativePhases[quarter], PlsrTestAbPhase()); + EXPECT_I((quarter == 3U) ? -1L : 0L, ReadPosition()); + } EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); PlsrPoll1ms(); EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_I(0L, ReadPosition()); + EXPECT_I(-1L, ReadPosition()); +} - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 5L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - PlsrTestEmitPulses(5UL); - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_I(5L, ReadPosition()); +static void TestAbSinglePulseMaximumFrequencyMatrix(void) +{ + static const uint16_t outputs[2] = {0U, 2U}; + static const int32_t directions[2] = {1L, -1L}; + uint32_t transitionsBefore; + uint16_t outputIndex; + uint16_t directionIndex; - EXPECT_U(PLSR_MB_OK, WriteWord(0x1008U, PLSR_POSITION_ABSOLUTE)); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 5L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); + for (outputIndex = 0U; outputIndex < 2U; outputIndex++) + { + for (directionIndex = 0U; directionIndex < 2U; directionIndex++) + { + ResetCore(); + ConfigureAbMotion(outputs[outputIndex], directions[directionIndex], + 100000UL, 100000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0UL, PlsrTestAbTransitionCount()); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(directions[directionIndex], ReadPosition()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + transitionsBefore = PlsrTestAbTransitionCount(); + PlsrTestEmitAbQuarters(8UL); + EXPECT_U(transitionsBefore, PlsrTestAbTransitionCount()); + EXPECT_I(directions[directionIndex], ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_U(0U, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + } + } +} + +static void TestAbFastGateCleanupIsDeferredToPoll(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 1L, 100000UL, 100000UL, 0U, 0U); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0UL, PlsrTestAbCleanupCount()); + + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_U(0UL, PlsrTestAbCleanupCount()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_I(5L, ReadPosition()); + EXPECT_U(1UL, PlsrTestAbCleanupCount()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); } -static void TestSelfJumpCanStop(void) +static void TestAbFinalArmJobTailChainsOnce(void) { - unsigned int loop; - - ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 2L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 1U)); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + static const uint16_t outputs[2] = {0U, 2U}; + static const int32_t displacements[2] = {2L, -2L}; + uint16_t index; - for (loop = 0U; loop < 3U; loop++) + for (index = 0U; index < 2U; index++) { - PlsrTestEmitPulses(2UL); - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); - EXPECT_U(1U, ReadCurrentSegment()); + ResetCore(); + ConfigureAbMotion(outputs[index], displacements[index], + 100000UL, 100000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + PlsrTestEmitAbQuarters(4UL); EXPECT_U(1U, PlsrTestPulseIsActive()); - } + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0UL, PlsrTestAbFastGateCount()); + EXPECT_I((displacements[index] > 0L) ? 1L : -1L, + ReadPosition()); - StopAndSettle(); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(8UL, PlsrTestAbTransitionCount()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_I(displacements[index], ReadPosition()); + PlsrTestServiceFinalArmJob(); + EXPECT_I(displacements[index], ReadPosition()); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(2UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(2UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + } } -static void TestStopDeceleratesBeforeCut(void) +static void TestAbFinalBoundaryBeforeArmJobIsNoOp(void) { - unsigned int tick; - uint32_t middleFrequency; - ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 1000U); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 10000L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); + ConfigureAbMotion(0U, 2L, 100000UL, 100000UL, 0U, 0U); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - EXPECT_U(1000UL, PlsrTestOutputFrequency()); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); - EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); - EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestDeferFinalArmJob(1U); - for (tick = 0U; tick < 450U; tick++) - { - PlsrPoll1ms(); - PlsrTestEmitPulses(1UL); - } - middleFrequency = PlsrTestOutputFrequency(); - EXPECT_TRUE((middleFrequency > 100UL) && (middleFrequency < 1000UL)); + PlsrTestEmitAbQuarters(4UL); EXPECT_U(1U, PlsrTestPulseIsActive()); - EXPECT_U(PLSR_MB_OK, QueueCommand(PLSR_COMMAND_STOP)); + EXPECT_I(1L, ReadPosition()); - for (tick = 450U; tick < 900U; tick++) - { - PlsrPoll1ms(); - PlsrTestEmitPulses(1UL); - } - EXPECT_TRUE(PlsrTestOutputFrequency() > 100UL); - EXPECT_TRUE(PlsrTestOutputFrequency() <= 103UL); - EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); - EXPECT_U(1U, PlsrTestPulseIsActive()); - PlsrTestEmitPulses(1UL); - EXPECT_U(100UL, PlsrTestOutputFrequency()); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(8UL, PlsrTestAbTransitionCount()); + EXPECT_I(2L, ReadPosition()); + + PlsrTestServiceFinalArmJob(); + PlsrTestDeferFinalArmJob(0U); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(2L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(2UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); +} + +static void TestAbFinalArmJobFailureDoesNotCountFinalPulse(void) +{ + ResetCore(); + ConfigureAbMotion(2U, -2L, 100000UL, 100000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestDeferFinalArmJob(1U); + + PlsrTestEmitAbQuarters(4UL); EXPECT_U(1U, PlsrTestPulseIsActive()); - PlsrTestEmitPulses(1UL); + EXPECT_I(-1L, ReadPosition()); + PlsrTestFailNextStopRequest(); + PlsrTestServiceFinalArmJob(); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_I(-1L, ReadPosition()); + PlsrTestEmitAbQuarters(8UL); + EXPECT_I(-1L, ReadPosition()); + PlsrTestDeferFinalArmJob(0U); PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); - EXPECT_I(902L, ReadPosition()); + EXPECT_U(PLSR_STATUS_ERROR, ReadStatus()); + EXPECT_U(PLSR_ERROR_TIMER, ReadError()); + EXPECT_I(-1L, ReadPosition()); + ExpectDiagnosticInterrupted(2UL, 1UL); } -static void TestStopAtPendingBoundary(void) +static void TestAbStopMailboxAtPendingBoundary(void) { ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, - 0U, 0U, 0U)); + ConfigureAbMotion(0U, 1L, 100000UL, 100000UL, 0U, 0U); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - PlsrTestEmitPulses(1UL); + PlsrTestEmitAbQuarters(4UL); EXPECT_U(0U, PlsrTestPulseIsActive()); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_U(0UL, PlsrTestAbCleanupCount()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_U(PLSR_MB_DEVICE_BUSY, QueueCommand(PLSR_COMMAND_START)); + EXPECT_U(PLSR_MB_DEVICE_BUSY, QueueCommand(PLSR_COMMAND_CLEAR)); + EXPECT_U(PLSR_MB_OK, QueueCommand(PLSR_COMMAND_STOP)); + + PlsrPoll1ms(); EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + EXPECT_U(0UL, PlsrTestAbCleanupCount()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); PlsrPoll1ms(); EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); EXPECT_U(0U, ReadCurrentSegment()); + EXPECT_U(1UL, PlsrTestAbCleanupCount()); EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_CLEAR)); + EXPECT_U(PLSR_STATUS_IDLE, ReadStatus()); + EXPECT_I(0L, ReadPosition()); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitAbQuarters(4UL); PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(2UL, PlsrTestAbCleanupCount()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); +} + +static void TestAbActAndExtCutsFinishAtZero(void) +{ + uint32_t transitionsBefore; + + ResetCore(); + ConfigureAbMotion(0U, 100L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_ACT_TIME, + 0U, 1U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(2UL); + EXPECT_U(3U, PlsrTestAbPhase()); + PlsrPoll1ms(); + PlsrTestEmitAbQuarters(2UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(1L, ReadPosition()); + transitionsBefore = PlsrTestAbTransitionCount(); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(transitionsBefore, PlsrTestAbTransitionCount()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); + ExpectDiagnosticInterrupted(100UL, 1UL); + + ResetCore(); + ConfigureAbMotion(2U, -100L, 1000UL, 1000UL, 0U, 0U); + PlsrTestSetInput(0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, -100L, PLSR_EXT_SIGNAL, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(3UL); + EXPECT_U(2U, PlsrTestAbPhase()); + PlsrTestSetInput(0U, 1U); + PlsrPoll1ms(); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(-1L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); + ExpectDiagnosticInterrupted(100UL, 1UL); } -static void TestOneMillisecondDirectionDelay(void) +static void TestAbSubsequentSinglePulsesStayContinuous(void) { ResetCore(); - ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, - 1000UL, 1000UL, 100UL, 0U, 0U); - EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 1U)); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, + PLSR_SEND_SUBSEQUENT, 100000UL, 100000UL, 100000UL, + 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 0U)); EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 1000UL, 10L, PLSR_EXT_OR_COMPLETE, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 100000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(2U, 100000UL, 1L, PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(2U, ReadCurrentSegment()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_U(0UL, PlsrTestAbFastGateCount()); + EXPECT_I(1L, ReadPosition()); + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(8UL, PlsrTestAbTransitionCount()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_I(2L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); +} + +static void TestAbArmedFrequencyWriteDoesNotReopenOutput(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 1L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(2U, PlsrTestAbPhase()); + EXPECT_U(PLSR_MB_OK, WriteU32(0x1100U, 2000UL)); + PlsrPoll1ms(); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(1000UL, PlsrTestQueuedFrequency()); + PlsrTestEmitAbQuarters(3UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_I(1L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); +} + +static void TestAbStopRequestForcedFault(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 1L, 1000UL, 1000UL, 0U, 0U); + PlsrTestFailNextStopRequest(); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(0L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_ERROR, ReadStatus()); + EXPECT_U(PLSR_ERROR_TIMER, ReadError()); + EXPECT_I(0L, ReadPosition()); + ExpectDiagnosticInterrupted(1UL, 0UL); + + ResetCore(); + ConfigureAbMotion(2U, -100L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(2UL); + PlsrTestFailNextStopRequest(); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(0L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_ERROR, ReadStatus()); + EXPECT_U(PLSR_ERROR_TIMER, ReadError()); + EXPECT_I(0L, ReadPosition()); + ExpectDiagnosticInterrupted(100UL, 0UL); +} + +static void TestAbStopAfterFinalBoundaryIsArmed(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 1L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(2U, PlsrTestAbPhase()); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitAbQuarters(3UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_I(1L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); +} + +static void TestAbStopArmConsumesLatchedFinalQuarterOnce(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 100L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(3UL); + EXPECT_U(1U, PlsrTestAbPhase()); + EXPECT_U(3UL, PlsrTestAbTransitionCount()); + EXPECT_I(0L, ReadPosition()); + + PlsrTestLatchAbFinalQuarterOnNextStopArm(); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4UL, PlsrTestAbTransitionCount()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + EXPECT_I(1L, ReadPosition()); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_U(0U, ReadWord(PLSR_DIAG_FLAGS_ADDRESS) + & PLSR_DIAG_FAULT_LATCHED); +} + +static void TestAbRejectsUnpairedOutputs(void) +{ + ResetCore(); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 1U)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_OUTPUT_MODE_PULSE_DIR, + ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + EXPECT_U(1U, ReadWord(0x1000U)); + + ResetCore(); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 3U)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_OUTPUT_MODE_PULSE_DIR, + ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + + ResetCore(); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 2U)); + EXPECT_U(PLSR_MB_OK, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, WriteWord(0x1000U, 1U)); + EXPECT_U(2U, ReadWord(0x1000U)); + EXPECT_U(PLSR_MB_ILLEGAL_VALUE, WriteWord(0x1000U, 3U)); + EXPECT_U(2U, ReadWord(0x1000U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 0U)); + EXPECT_U(0U, ReadWord(0x1000U)); +} + +static void TestAbStopAtCompleteCycleBoundary(void) +{ + ResetCore(); + ConfigureAbMotion(0U, 100L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(2U, PlsrTestAbPhase()); + EXPECT_U(1U, PlsrTestAbTransitionCount()); + EXPECT_I(0L, ReadPosition()); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(0UL, PlsrTestAbFastGateCount()); + PlsrTestEmitAbQuarters(2UL); + EXPECT_U(1U, PlsrTestAbPhase()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_I(0L, ReadPosition()); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4U, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(1UL, PlsrTestAbFastGateCount()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); +} + +static void TestAbDynamicFrequencyChangesOnlyAtZeroPhase(void) +{ + uint32_t previousFrequency; + uint32_t currentFrequency; + uint16_t quarter; + uint8_t frequencyChanged = 0U; + + ResetCore(); + ConfigureAbMotion(0U, 20L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(2U, PlsrTestAbPhase()); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + + EXPECT_U(PLSR_MB_OK, WriteU32(0x1100U, 2000UL)); + PlsrPoll1ms(); + previousFrequency = PlsrTestOutputFrequency(); + EXPECT_U(1000UL, previousFrequency); + + for (quarter = 0U; quarter < 12U; quarter++) + { + PlsrTestEmitAbQuarters(1UL); + currentFrequency = PlsrTestOutputFrequency(); + if (currentFrequency != previousFrequency) + { + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0U, PlsrTestAbTransitionCount() & 3UL); + EXPECT_U(1000UL, previousFrequency); + EXPECT_U(2000UL, currentFrequency); + frequencyChanged = 1U; + break; + } + EXPECT_U(1000UL, currentFrequency); + previousFrequency = currentFrequency; + } + EXPECT_U(1U, frequencyChanged); + EXPECT_U(1U, PlsrTestPulseIsActive()); + StopAndSettle(); +} + +static void TestAbStaleFrequencyCommitAfterNaturalCompletion(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureAbMotion(0U, 2L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(PLSR_MB_OK, WriteU32(0x1100U, 2000UL)); + PlsrPoll1ms(); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(1000UL, PlsrTestQueuedFrequency()); + + PlsrTestCompleteAbCycleOnNextQueueCommit(); + PlsrTestEmitAbQuarters(4UL); + + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(8UL, PlsrTestAbTransitionCount()); + EXPECT_I(2L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS, + flags & (PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS)); + EXPECT_U(0U, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(2UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(2UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_REQUESTED_FREQUENCY_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_EXPECTED_TIMER_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_ACTIVE_TIMER_ADDRESS)); +} + +static void TestAbDirectionReversalRestartsFromZeroPhase(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, + PLSR_SEND_SUBSEQUENT, 1000UL, 1000UL, 1000UL, + 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1000U, 0U)); + EXPECT_U(PLSR_MB_OK, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, PLSR_OUTPUT_MODE_AB)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(2U, 1000UL, -1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + PlsrTestEmitAbQuarters(4UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(4U, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(1U, ReadCurrentSegment()); + EXPECT_I(1L, ReadPosition()); + + PlsrPoll1ms(); + EXPECT_U(2U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(0x0001U, ReadWord(PLSR_DIAG_MODE_DIRECTION_ADDRESS)); + PlsrTestEmitAbQuarters(1UL); + EXPECT_U(1U, PlsrTestAbPhase()); + EXPECT_U(5U, PlsrTestAbTransitionCount()); + EXPECT_I(1L, ReadPosition()); + PlsrTestEmitAbQuarters(3UL); + EXPECT_U(0U, PlsrTestAbPhase()); + EXPECT_U(8U, PlsrTestAbTransitionCount()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(0L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); +} + +static void TestAbModePersistence(void) +{ + ResetCore(); + ConfigureAbMotion(2U, 4L, 2345UL, 2345UL, 0U, 0U); + EXPECT_U(1U, PlsrInit()); + EXPECT_U(PLSR_STATUS_IDLE, ReadStatus()); + EXPECT_U(2U, ReadWord(0x1000U)); + EXPECT_U(PLSR_OUTPUT_MODE_AB, ReadWord(PLSR_OUTPUT_MODE_ADDRESS)); + EXPECT_U(2345UL, ReadU32(0x1100U)); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(4L, ReadPosition()); +} + +static void TestDiagnosticPass(void) +{ + uint16_t flags; + + ResetCore(); + ClearDiagnostic(); + ConfigureAbMotion(0U, 8L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(PLSR_MB_DEVICE_BUSY, + WriteWord(PLSR_OUTPUT_MODE_ADDRESS, + PLSR_OUTPUT_MODE_PULSE_DIR)); + EXPECT_U(PLSR_MB_DEVICE_BUSY, + WriteWord(PLSR_DIAGNOSTIC_CONTROL_ADDRESS, 1U)); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_TRUE((flags & PLSR_DIAG_MONITORING_ACTIVE) != 0U); + EXPECT_U(1U, ReadWord(PLSR_DIAG_SEGMENT_ADDRESS)); + EXPECT_U(0x0101U, ReadWord(PLSR_DIAG_MODE_DIRECTION_ADDRESS)); + EXPECT_U(8UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(0UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_REQUESTED_FREQUENCY_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_EXPECTED_TIMER_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_ACTIVE_TIMER_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_REQUEST_ERROR_ADDRESS)); + + PlsrTestEmitPulses(8UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(0U, flags & PLSR_DIAG_MONITORING_ACTIVE); + EXPECT_U(PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS, + flags & (PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS)); + EXPECT_U(PLSR_DIAG_FREQUENCY_CHECKED | PLSR_DIAG_FREQUENCY_PASS, + flags & (PLSR_DIAG_FREQUENCY_CHECKED + | PLSR_DIAG_FREQUENCY_PASS)); + EXPECT_U(PLSR_DIAG_CURVE_CHECKED | PLSR_DIAG_CURVE_PASS, + flags & (PLSR_DIAG_CURVE_CHECKED | PLSR_DIAG_CURVE_PASS)); + EXPECT_U(0U, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_NONE, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_U(8UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(8UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_REQUESTED_FREQUENCY_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_EXPECTED_TIMER_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_ACTIVE_TIMER_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_REQUEST_ERROR_ADDRESS)); + EXPECT_TRUE(ReadU32(PLSR_DIAG_SAMPLE_COUNT_ADDRESS) > 0UL); + EXPECT_U(0UL, ReadU32(PLSR_DIAG_MISMATCH_COUNT_ADDRESS)); + EXPECT_U(0UL, ReadU32(PLSR_DIAG_MAX_ERROR_ADDRESS)); + EXPECT_U(0xFFFFFFFFUL, + ReadU32(PLSR_DIAG_FIRST_MISMATCH_ADDRESS)); +} + +static void TestDiagnosticCountFaultAndClear(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureAbMotion(0U, 4L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestInjectCountOffset(1L); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_COUNT_CHECKED, + flags & PLSR_DIAG_COUNT_CHECKED); + EXPECT_U(0U, flags & PLSR_DIAG_COUNT_PASS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, + flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_COUNT, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_U(4UL, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(5UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(1L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); + + ClearDiagnostic(); +} + +static void TestDiagnosticFrequencyFaultAndClear(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureAbMotion(0U, 8L, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestInjectActiveFrequencyOffset(25L); + PlsrTestEmitPulses(8UL); + PlsrPoll1ms(); + + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_FREQUENCY_CHECKED, + flags & PLSR_DIAG_FREQUENCY_CHECKED); + EXPECT_U(0U, flags & PLSR_DIAG_FREQUENCY_PASS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, + flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_FREQUENCY, + ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_U(1000UL, ReadU32(PLSR_DIAG_EXPECTED_TIMER_ADDRESS)); + EXPECT_U(1025UL, ReadU32(PLSR_DIAG_ACTIVE_TIMER_ADDRESS)); + EXPECT_TRUE(ReadU32(PLSR_DIAG_MISMATCH_COUNT_ADDRESS) > 0UL); + EXPECT_U(25UL, ReadU32(PLSR_DIAG_MAX_ERROR_ADDRESS)); + EXPECT_TRUE(ReadU32(PLSR_DIAG_FIRST_MISMATCH_ADDRESS) + != 0xFFFFFFFFUL); + + ClearDiagnostic(); +} + +static void TestDiagnosticCurveFaultAndClear(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureAbMotion(0U, 50L, 1000UL, 100UL, 1000U, 1000U); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestInjectCurveMismatch(); + PlsrTestEmitPulses(50UL); + PlsrPoll1ms(); + + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_CURVE_CHECKED, + flags & PLSR_DIAG_CURVE_CHECKED); + EXPECT_U(0U, flags & PLSR_DIAG_CURVE_PASS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, + flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_CURVE, + ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_TRUE(ReadU32(PLSR_DIAG_MISMATCH_COUNT_ADDRESS) > 0UL); + EXPECT_TRUE(ReadU32(PLSR_DIAG_FIRST_MISMATCH_ADDRESS) + != 0xFFFFFFFFUL); + + ClearDiagnostic(); +} + +static void TestDiagnosticInterruptedSegments(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(2UL); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + ExpectDiagnosticInterrupted(100UL, 3UL); + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 10U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + ExpectDiagnosticInterrupted(100UL, 0UL); + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_ACT_TIME, + 0U, 1U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(3UL); + PlsrPoll1ms(); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + ExpectDiagnosticInterrupted(100UL, 4UL); + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + PlsrTestSetInput(0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_EXT_SIGNAL, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(2UL); + PlsrTestSetInput(0U, 1U); + PlsrPoll1ms(); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + ExpectDiagnosticInterrupted(100UL, 3UL); +} + +static void TestDiagnosticFaultLatchNeedsExplicitClear(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 4L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestInjectCountOffset(1L); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_DIAG_REASON_COUNT, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + + PlsrTestInjectCountOffset(0L); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_CLEAR)); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(0U, flags & PLSR_DIAG_COUNT_PASS); + EXPECT_U(PLSR_DIAG_REASON_COUNT, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_COUNT_CHECKED, flags & PLSR_DIAG_COUNT_CHECKED); + EXPECT_U(0U, flags & PLSR_DIAG_COUNT_PASS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_COUNT, ReadWord(PLSR_DIAG_REASON_ADDRESS)); + EXPECT_U(4UL, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); + + ClearDiagnostic(); +} + +static void TestDiagnosticFrequencyPassStaysFailed(void) +{ + uint16_t flags; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 4L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestInjectActiveFrequencyOffset(25L); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(0U, flags & PLSR_DIAG_FREQUENCY_PASS); + EXPECT_U(PLSR_DIAG_REASON_FREQUENCY, + ReadWord(PLSR_DIAG_REASON_ADDRESS)); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(4UL); + PlsrPoll1ms(); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(PLSR_DIAG_FREQUENCY_CHECKED, + flags & PLSR_DIAG_FREQUENCY_CHECKED); + EXPECT_U(0U, flags & PLSR_DIAG_FREQUENCY_PASS); + EXPECT_U(PLSR_DIAG_FAULT_LATCHED, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_FREQUENCY, + ReadWord(PLSR_DIAG_REASON_ADDRESS)); + + ClearDiagnostic(); +} + +static void TestDiagnosticCurveCountersSaturate(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 2L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestSetDiagnosticCurveCounts(0xFFFFFFFFUL, 0xFFFFFFFFUL); + PlsrTestInjectCurveMismatch(); + PlsrTestEmitPulses(2UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0xFFFFFFFFUL, ReadU32(PLSR_DIAG_SAMPLE_COUNT_ADDRESS)); + EXPECT_U(0xFFFFFFFFUL, ReadU32(PLSR_DIAG_MISMATCH_COUNT_ADDRESS)); + EXPECT_U(PLSR_DIAG_REASON_CURVE, ReadWord(PLSR_DIAG_REASON_ADDRESS)); +} + +static void TestWaitZeroUsesOneMillisecond(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_WAIT_TIME, 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(2U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(1UL); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_WAITING, ReadStatus()); + EXPECT_U(1U, ReadCurrentSegment()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + + PlsrPoll1ms(); + EXPECT_U(2U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(2L, ReadPosition()); +} + +static void TestActZeroSkipsWithoutPulse(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 2U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_ACT_TIME, 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(2U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(1U, ReadCurrentSegment()); + EXPECT_I(0L, ReadPosition()); + + PlsrPoll1ms(); + EXPECT_U(2U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_I(0L, ReadPosition()); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(1L, ReadPosition()); +} + +static void TestRelativeAndAbsoluteZeroDisplacement(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 0L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(0L, ReadPosition()); + + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 5L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(5UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(5L, ReadPosition()); + + EXPECT_U(PLSR_MB_OK, WriteWord(0x1008U, PLSR_POSITION_ABSOLUTE)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 5L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(5L, ReadPosition()); +} + +static void ConfigureTenSegmentMove(const uint8_t *jumpSegments) +{ + uint16_t segment; + + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 10U, + PLSR_SEND_COMPLETE, 1000UL, 1000UL, 1000UL, + 0U, 0U); + for (segment = 1U; segment <= 10U; segment++) + { + EXPECT_U(PLSR_MB_OK, + SetSegment((uint8_t)segment, 1000UL, + (int32_t)segment, PLSR_EXT_OR_COMPLETE, + 0U, 0U, + (jumpSegments != NULL) + ? jumpSegments[segment - 1U] : 0U)); + } +} + +static void TestAllTenSegmentsRunInSequence(void) +{ + int32_t expectedPosition = 0L; + uint16_t segment; + + ResetCore(); + ConfigureTenSegmentMove(NULL); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + for (segment = 1U; segment <= 10U; segment++) + { + EXPECT_U(segment, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses((uint32_t)segment); + expectedPosition += (int32_t)segment; + EXPECT_I(expectedPosition, ReadPosition()); + PlsrPoll1ms(); + if (segment < 10U) + { + EXPECT_U(segment + 1U, ReadCurrentSegment()); + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + } + } + + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0U, ReadCurrentSegment()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_I(55L, ReadPosition()); +} + +static void TestAllTenSegmentsRunThroughJumpChain(void) +{ + static const uint8_t jumps[10] = + { + 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 2U, 0U + }; + static const uint8_t order[10] = + { + 1U, 3U, 5U, 7U, 9U, 2U, 4U, 6U, 8U, 10U + }; + int32_t expectedPosition = 0L; + uint16_t index; + + ResetCore(); + ConfigureTenSegmentMove(jumps); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + for (index = 0U; index < 10U; index++) + { + uint8_t segment = order[index]; + + EXPECT_U(segment, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses((uint32_t)segment); + expectedPosition += (int32_t)segment; + EXPECT_I(expectedPosition, ReadPosition()); + PlsrPoll1ms(); + if (index + 1U < 10U) + { + EXPECT_U(order[index + 1U], ReadCurrentSegment()); + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + } + } + + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0U, ReadCurrentSegment()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_I(55L, ReadPosition()); +} + +static void TestStartSegmentTenRunsNormally(void) +{ + ResetCore(); + ConfigureTenSegmentMove(NULL); + EXPECT_U(PLSR_MB_OK, WriteWord(0x100AU, 10U)); + EXPECT_U(10U, ReadWord(0x100AU)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(10U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + + PlsrTestEmitPulses(10UL); + EXPECT_I(10L, ReadPosition()); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(0U, ReadCurrentSegment()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_I(10L, ReadPosition()); +} + +static void TestSelfJumpCanStop(void) +{ + unsigned int loop; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 2L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 1U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + for (loop = 0U; loop < 3U; loop++) + { + PlsrTestEmitPulses(2UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + EXPECT_U(1U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + } + + StopAndSettle(); +} + +static void TestStopDeceleratesBeforeCut(void) +{ + unsigned int tick; + uint32_t middleFrequency; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 1000U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 10000L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + + for (tick = 0U; tick < 450U; tick++) + { + PlsrPoll1ms(); + PlsrTestEmitPulses(1UL); + } + middleFrequency = PlsrTestOutputFrequency(); + EXPECT_TRUE((middleFrequency > 100UL) && (middleFrequency < 1000UL)); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_MB_OK, QueueCommand(PLSR_COMMAND_STOP)); + + for (tick = 450U; tick < 900U; tick++) + { + PlsrPoll1ms(); + PlsrTestEmitPulses(1UL); + } + EXPECT_TRUE(PlsrTestOutputFrequency() > 100UL); + EXPECT_TRUE(PlsrTestOutputFrequency() <= 103UL); + EXPECT_U(PLSR_STATUS_DECELERATING, ReadStatus()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + EXPECT_U(100UL, PlsrTestOutputFrequency()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_I(902L, ReadPosition()); +} + +static void TestStopAtPendingBoundary(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + PlsrTestEmitPulses(1UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_STOP)); + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(0U, ReadCurrentSegment()); + EXPECT_I(1L, ReadPosition()); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_STOPPED, ReadStatus()); + EXPECT_U(0U, PlsrTestPulseIsActive()); +} + +static void TestOneMillisecondDirectionDelay(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 1U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 10L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestPulseIsActive()); + + PlsrPoll1ms(); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + StopAndSettle(); +} + +static void ExpectDirectionPinLevels(uint8_t selectedOutput, + uint8_t selectedPinLevel) +{ + uint8_t output; + + for (output = 0U; output < 4U; output++) + { + EXPECT_U((output == selectedOutput) ? selectedPinLevel : 1U, + PlsrTestDirectionPinLevel(output)); + } +} + +static void TestDirectionOutputPolarityMatrix(void) +{ + uint8_t directionOutput; + uint8_t negativeLogic; + uint8_t positive; + + for (directionOutput = 0U; directionOutput < 4U; directionOutput++) + { + for (negativeLogic = 0U; negativeLogic < 2U; negativeLogic++) + { + for (positive = 0U; positive < 2U; positive++) + { + uint8_t logicalLevel = positive ^ negativeLogic; + uint8_t pinLevel = logicalLevel ^ 1U; + uint8_t output; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, + PLSR_SEND_COMPLETE, 1000UL, 1000UL, + 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, directionOutput)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 2U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1006U, negativeLogic)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, + (positive != 0U) ? 1L : -1L, + PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); + + EXPECT_U(directionOutput, ReadWord(0x1001U)); + EXPECT_U(negativeLogic, ReadWord(0x1006U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(logicalLevel, PlsrTestDirectionLevel()); + ExpectDirectionPinLevels(directionOutput, pinLevel); + EXPECT_U(0U, PlsrTestPulseIsActive()); + for (output = 0U; output < 4U; output++) + { + EXPECT_U(1UL, PlsrTestDirectionWriteCount(output)); + EXPECT_U(((output == directionOutput) + && (pinLevel == 0U)) ? 1UL : 0UL, + PlsrTestDirectionTransitionCount(output)); + } + + PlsrPoll1ms(); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I((positive != 0U) ? 1L : -1L, ReadPosition()); + } + } + } +} + +static void TestDirectionSameAndReverseSegments(void) +{ + uint8_t output; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 3U, + PLSR_SEND_COMPLETE, 1000UL, 1000UL, 1000UL, + 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, 2U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 2U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1006U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(2U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(3U, 1000UL, -1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(1U, PlsrTestDirectionLevel()); + ExpectDirectionPinLevels(2U, 0U); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(1U, PlsrTestPulseIsActive()); + + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(2U, ReadCurrentSegment()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + ExpectDirectionPinLevels(2U, 0U); + EXPECT_U(1UL, PlsrTestDirectionTransitionCount(2U)); + + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(3U, ReadCurrentSegment()); + EXPECT_U(0U, PlsrTestDirectionLevel()); + ExpectDirectionPinLevels(2U, 1U); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(2UL, PlsrTestDirectionTransitionCount(2U)); + for (output = 0U; output < 4U; output++) + { + EXPECT_U(3UL, PlsrTestDirectionWriteCount(output)); + if (output != 2U) + { + EXPECT_U(0UL, PlsrTestDirectionTransitionCount(output)); + } + } + + PlsrPoll1ms(); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(1L, ReadPosition()); +} + +static void TestDirectionOutputCanChangeBetweenCommands(void) +{ + uint8_t output; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, + PLSR_SEND_COMPLETE, 1000UL, 1000UL, 1000UL, + 0U, 0U); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, 0U)); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1005U, 1U)); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + ExpectDirectionPinLevels(0U, 0U); + EXPECT_U(0U, PlsrTestPulseIsActive()); + PlsrPoll1ms(); + EXPECT_U(1U, PlsrTestPulseIsActive()); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_MB_OK, WriteWord(0x1001U, 3U)); + EXPECT_U(3U, ReadWord(0x1001U)); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + ExpectDirectionPinLevels(3U, 0U); EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(2UL, PlsrTestDirectionTransitionCount(0U)); + EXPECT_U(1UL, PlsrTestDirectionTransitionCount(3U)); + for (output = 0U; output < 4U; output++) + { + EXPECT_U(2UL, PlsrTestDirectionWriteCount(output)); + } PlsrPoll1ms(); EXPECT_U(1U, PlsrTestPulseIsActive()); - EXPECT_U(1000UL, PlsrTestOutputFrequency()); - StopAndSettle(); + PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_I(2L, ReadPosition()); } static void TestExtEdgeAtNaturalBoundary(void) @@ -766,8 +2097,11 @@ static void TestOldRampDoesNotRetargetSeamlessNextSegment(void) static void TestShortProfileBoundaryMatrix(void) { - static const uint16_t pulseCounts[] = {1U, 2U, 10U, 99U, 100U, 101U}; - uint32_t samples[3][101]; + static const uint16_t pulseCounts[] = + { + 1U, 2U, 10U, 99U, 100U, 101U, 258U + }; + uint32_t samples[3][258]; uint64_t previousDurationNs[3] = {0ULL, 0ULL, 0ULL}; uint64_t durationNs[3]; unsigned int countIndex; @@ -809,6 +2143,10 @@ static void TestShortProfileBoundaryMatrix(void) durationNs[curveMode] += PulsePeriodNs(samples[curveMode][pulse]); PlsrTestEmitPulses(1UL); + if (((pulse + 1U) % 100U) == 0U) + { + PlsrPoll1ms(); + } if ((pulse + 1U) < pulseCounts[countIndex]) { EXPECT_U(1U, PlsrTestPulseIsActive()); @@ -908,6 +2246,40 @@ static void TestShortProfileBoundaryMatrix(void) EXPECT_U(1U, anySmoothDiffersFromSine); } +static void TestShortProfile258IsFullyPrecomputed(void) +{ + uint16_t curveMode; + + for (curveMode = 0U; curveMode <= 2U; curveMode++) + { + ResetCore(); + ConfigureCommon(curveMode, PLSR_POSITION_RELATIVE, 1U, + PLSR_SEND_COMPLETE, 100000UL, 1000UL, 1000UL, + 100U, 100U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 100000UL, 258L, + PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + EXPECT_U(256U, PlsrTestProfileQueueCount()); + EXPECT_U(0UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(256UL, PlsrTestProfileQueueWriteIndex()); + EXPECT_U(258U, PlsrTestProfileProducerNextPeriod()); + + PlsrTestEmitPulses(258UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_U(256UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(256UL, PlsrTestProfileQueueWriteIndex()); + EXPECT_I(258L, ReadPosition()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + } +} + static void TestShortFinalDeceleratesWithoutPoll(void) { uint16_t curveMode; @@ -940,6 +2312,10 @@ static void TestShortFinalDeceleratesWithoutPoll(void) EXPECT_TRUE(currentFrequencyHz >= 99990UL); durationNs += PulsePeriodNs(currentFrequencyHz); previousFrequencyHz = currentFrequencyHz; + if (((pulse + 1UL) % 100UL) == 0UL) + { + PlsrPoll1ms(); + } } EXPECT_TRUE(durationNs >= 99990ULL); EXPECT_TRUE(durationNs <= 100010ULL); @@ -952,18 +2328,18 @@ static void TestShortFinalDeceleratesWithoutPoll(void) } } +static void ExpectCompletedDiagnostic(uint32_t pulseCount); + static void TestZeroToMaximumRampKeepsConfiguredDuration(void) { uint16_t curveMode; uint32_t firstFrequencyHz[3]; - uint32_t previousFrequencyHz; - uint32_t currentFrequencyHz; - uint32_t frequencyStepHz; - uint32_t maximumStepHz; - uint32_t pulse; - uint64_t durationNs; - const uint64_t expectedDurationNs = 20000000ULL; - const uint64_t toleranceNs = 100000ULL; + uint32_t frequencyHz; + uint32_t pulseAccumulator; + uint32_t pulsesThisMillisecond; + uint32_t emittedPulses; + uint32_t tick; + const uint32_t pulseCount = 3000UL; for (curveMode = 0U; curveMode <= 2U; curveMode++) { @@ -972,163 +2348,175 @@ static void TestZeroToMaximumRampKeepsConfiguredDuration(void) PLSR_SEND_COMPLETE, 100000UL, 0UL, 100000UL, 20U, 0U); EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 100000UL, 1000L, + SetSegment(1U, 100000UL, (int32_t)pulseCount, PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - EXPECT_U(1U, PlsrTestPulseIsActive()); - - previousFrequencyHz = PlsrTestOutputFrequency(); - firstFrequencyHz[curveMode] = previousFrequencyHz; - EXPECT_TRUE(previousFrequencyHz >= 400UL); - EXPECT_TRUE(previousFrequencyHz <= 2500UL); - maximumStepHz = 0UL; - durationNs = PulsePeriodNs(previousFrequencyHz); + EXPECT_U(0U, PlsrTestPulseIsActive()); - for (pulse = 1UL; pulse < 1000UL; pulse++) + pulseAccumulator = 0UL; + emittedPulses = 0UL; + for (tick = 1UL; tick <= 20UL; tick++) { - PlsrTestEmitPulses(1UL); + PlsrPoll1ms(); EXPECT_U(1U, PlsrTestPulseIsActive()); - currentFrequencyHz = PlsrTestOutputFrequency(); - EXPECT_TRUE(currentFrequencyHz >= previousFrequencyHz); - EXPECT_TRUE(currentFrequencyHz <= 100000UL); - frequencyStepHz = currentFrequencyHz - previousFrequencyHz; - if (frequencyStepHz > maximumStepHz) + frequencyHz = PlsrTestOutputFrequency(); + EXPECT_TRUE(frequencyHz != 0UL); + EXPECT_TRUE(frequencyHz <= 100000UL); + if (tick == 1UL) { - maximumStepHz = frequencyStepHz; + firstFrequencyHz[curveMode] = frequencyHz; } - durationNs += PulsePeriodNs(currentFrequencyHz); - previousFrequencyHz = currentFrequencyHz; + if (tick < 20UL) + { + EXPECT_U(PLSR_STATUS_ACCELERATING, ReadStatus()); + } + else + { + EXPECT_U(PLSR_STATUS_RUNNING, ReadStatus()); + } + + pulseAccumulator += frequencyHz; + pulsesThisMillisecond = pulseAccumulator / 1000UL; + pulseAccumulator %= 1000UL; + PlsrTestEmitPulses(pulsesThisMillisecond); + emittedPulses += pulsesThisMillisecond; } - EXPECT_TRUE(maximumStepHz <= 10000UL); - EXPECT_TRUE(previousFrequencyHz >= 99000UL); - EXPECT_TRUE(UnsignedDifference64(durationNs, expectedDurationNs) - <= toleranceNs); - PlsrTestEmitPulses(1UL); + EXPECT_TRUE(emittedPulses < pulseCount); + PlsrTestEmitPulses(pulseCount - emittedPulses); EXPECT_U(0U, PlsrTestPulseIsActive()); PlsrPoll1ms(); EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); EXPECT_U(PLSR_ERROR_NONE, ReadError()); - EXPECT_I(1000L, ReadPosition()); + EXPECT_I((long)pulseCount, ReadPosition()); + ExpectCompletedDiagnostic(pulseCount); } EXPECT_TRUE(firstFrequencyHz[0] > firstFrequencyHz[1]); EXPECT_TRUE(firstFrequencyHz[1] > firstFrequencyHz[2]); } -static void TestMaximumPulseRampKeepsReachableDuration(void) +typedef struct { - uint16_t curveMode; - uint32_t previousFrequencyHz; - uint32_t currentFrequencyHz; - uint32_t frequencyStepHz; - uint32_t maximumStepHz; - uint32_t pulse; - uint32_t reachablePeakHz = IntegerSquareRoot64( - (uint64_t)2U * 65535UL * 100000UL * 1000UL / 1311UL); - uint64_t durationNs; - uint64_t expectedDurationNs = - (uint64_t)2U * 65535UL * 1000000000ULL / reachablePeakHz; - uint64_t toleranceNs = expectedDurationNs / 500ULL + 1000000ULL; - - for (curveMode = 0U; curveMode <= 2U; curveMode++) + uint32_t emittedPulses; + uint32_t elapsedMs; + uint32_t maximumFrequencyHz; + uint32_t finalFrequencyHz; +} REAL_TIME_PROFILE_STATS; + +static void RunProfileAtOneMillisecondCadence( + uint32_t pulseCount, + REAL_TIME_PROFILE_STATS *stats) +{ + uint32_t pulseAccumulator = 0UL; + uint32_t frequencyHz; + uint32_t pulsesThisMillisecond; + uint32_t remainingPulses; + + stats->emittedPulses = 0UL; + stats->elapsedMs = 0UL; + stats->maximumFrequencyHz = 0UL; + stats->finalFrequencyHz = 0UL; + + while ((stats->emittedPulses < pulseCount) + && (PlsrTestPulseIsActive() != 0U) + && (stats->elapsedMs < 2000UL)) { - ResetCore(); - ConfigureCommon(curveMode, PLSR_POSITION_RELATIVE, 1U, - PLSR_SEND_COMPLETE, 100000UL, 0UL, 100000UL, - 1311U, 0U); - EXPECT_U(PLSR_MB_OK, - SetSegment(1U, 100000UL, 65535L, - PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); - EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - EXPECT_U(1U, PlsrTestPulseIsActive()); - - previousFrequencyHz = PlsrTestOutputFrequency(); - EXPECT_TRUE(previousFrequencyHz > 1UL); - EXPECT_TRUE(previousFrequencyHz < reachablePeakHz); - maximumStepHz = 0UL; - durationNs = PulsePeriodNs(previousFrequencyHz); - - for (pulse = 1UL; pulse < 65535UL; pulse++) + PlsrPoll1ms(); + stats->elapsedMs++; + if (PlsrTestPulseIsActive() == 0U) { - PlsrTestEmitPulses(1UL); - EXPECT_U(1U, PlsrTestPulseIsActive()); - currentFrequencyHz = PlsrTestOutputFrequency(); - EXPECT_TRUE(currentFrequencyHz >= previousFrequencyHz); - EXPECT_TRUE(currentFrequencyHz <= reachablePeakHz + 5UL); - frequencyStepHz = currentFrequencyHz - previousFrequencyHz; - if (frequencyStepHz > maximumStepHz) - { - maximumStepHz = frequencyStepHz; - } - durationNs += PulsePeriodNs(currentFrequencyHz); - previousFrequencyHz = currentFrequencyHz; + break; } - EXPECT_TRUE(maximumStepHz <= 5000UL); - EXPECT_TRUE(previousFrequencyHz * 100UL - >= reachablePeakHz * 99UL); - EXPECT_TRUE(UnsignedDifference64(durationNs, expectedDurationNs) - <= toleranceNs); - PlsrTestEmitPulses(1UL); - EXPECT_U(0U, PlsrTestPulseIsActive()); - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_U(PLSR_ERROR_NONE, ReadError()); - EXPECT_I(65535L, ReadPosition()); + frequencyHz = PlsrTestOutputFrequency(); + EXPECT_TRUE(frequencyHz != 0UL); + if (frequencyHz > stats->maximumFrequencyHz) + { + stats->maximumFrequencyHz = frequencyHz; + } + stats->finalFrequencyHz = frequencyHz; + pulseAccumulator += frequencyHz; + pulsesThisMillisecond = pulseAccumulator / 1000UL; + pulseAccumulator %= 1000UL; + remainingPulses = pulseCount - stats->emittedPulses; + if (pulsesThisMillisecond > remainingPulses) + { + pulsesThisMillisecond = remainingPulses; + } + PlsrTestEmitPulses(pulsesThisMillisecond); + stats->emittedPulses += pulsesThisMillisecond; } + + PlsrPoll1ms(); + EXPECT_U(pulseCount, stats->emittedPulses); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + EXPECT_I((long)pulseCount, ReadPosition()); +} + +static void ExpectCompletedDiagnostic(uint32_t pulseCount) +{ + uint16_t flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + + EXPECT_U(pulseCount, ReadU32(PLSR_DIAG_EXPECTED_COUNT_ADDRESS)); + EXPECT_U(pulseCount, ReadU32(PLSR_DIAG_OBSERVED_COUNT_ADDRESS)); + EXPECT_I(0L, ReadI32(PLSR_DIAG_COUNT_ERROR_ADDRESS)); + EXPECT_U(PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS + | PLSR_DIAG_FREQUENCY_CHECKED | PLSR_DIAG_FREQUENCY_PASS + | PLSR_DIAG_CURVE_CHECKED | PLSR_DIAG_CURVE_PASS, + flags & (PLSR_DIAG_COUNT_CHECKED | PLSR_DIAG_COUNT_PASS + | PLSR_DIAG_FREQUENCY_CHECKED + | PLSR_DIAG_FREQUENCY_PASS + | PLSR_DIAG_CURVE_CHECKED | PLSR_DIAG_CURVE_PASS)); + EXPECT_U(0U, flags & PLSR_DIAG_FAULT_LATCHED); + EXPECT_U(PLSR_DIAG_REASON_NONE, ReadWord(PLSR_DIAG_REASON_ADDRESS)); +} + +static void TestLongProfile259UsesMillisecondRamp(void) +{ + REAL_TIME_PROFILE_STATS stats; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 100000UL, 1000UL, 1000UL, 100U, 100U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 100000UL, 259L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_U(0UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(0UL, PlsrTestProfileQueueWriteIndex()); + + RunProfileAtOneMillisecondCadence(259UL, &stats); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_TRUE(stats.elapsedMs > 1UL); + ExpectCompletedDiagnostic(259UL); } -static void TestMaximumSingleRampWithoutPoll(void) +static void TestMaximumProfileOneMillisecondCadence(void) { + REAL_TIME_PROFILE_STATS stats; uint16_t curveMode; - uint32_t previousFrequencyHz; - uint32_t currentFrequencyHz; - uint32_t minimumFrequencyHz; - uint32_t maximumFrequencyHz; - uint32_t pulse; for (curveMode = 0U; curveMode <= 2U; curveMode++) { ResetCore(); ConfigureCommon(curveMode, PLSR_POSITION_RELATIVE, 1U, - PLSR_SEND_COMPLETE, 1000UL, 100000UL, 0UL, - 1000U, 1000U); + PLSR_SEND_COMPLETE, 100000UL, 1000UL, 1000UL, + 100U, 100U); EXPECT_U(PLSR_MB_OK, SetSegment(1U, 100000UL, 65535L, PLSR_EXT_OR_COMPLETE, 0U, 0U, 0U)); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); - previousFrequencyHz = PlsrTestOutputFrequency(); - minimumFrequencyHz = previousFrequencyHz; - maximumFrequencyHz = previousFrequencyHz; - EXPECT_TRUE(previousFrequencyHz >= 99000UL); - EXPECT_TRUE(previousFrequencyHz <= 100000UL); - - for (pulse = 1UL; pulse < 65535UL; pulse++) - { - PlsrTestEmitPulses(1UL); - EXPECT_U(1U, PlsrTestPulseIsActive()); - currentFrequencyHz = PlsrTestOutputFrequency(); - EXPECT_TRUE(currentFrequencyHz <= previousFrequencyHz); - EXPECT_TRUE(currentFrequencyHz >= 99000UL); - if (currentFrequencyHz < minimumFrequencyHz) - { - minimumFrequencyHz = currentFrequencyHz; - } - if (currentFrequencyHz > maximumFrequencyHz) - { - maximumFrequencyHz = currentFrequencyHz; - } - previousFrequencyHz = currentFrequencyHz; - } - EXPECT_TRUE(minimumFrequencyHz > 1UL); - EXPECT_TRUE(maximumFrequencyHz <= 100000UL); - EXPECT_TRUE(minimumFrequencyHz < maximumFrequencyHz); - PlsrTestEmitPulses(1UL); - EXPECT_U(0U, PlsrTestPulseIsActive()); - PlsrPoll1ms(); - EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); - EXPECT_U(PLSR_ERROR_NONE, ReadError()); - EXPECT_I(65535L, ReadPosition()); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_U(0UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(0UL, PlsrTestProfileQueueWriteIndex()); + + RunProfileAtOneMillisecondCadence(65535UL, &stats); + EXPECT_TRUE(stats.maximumFrequencyHz >= 99990UL); + EXPECT_U(1000UL, stats.finalFrequencyHz); + ExpectCompletedDiagnostic(65535UL); } } @@ -1148,6 +2536,7 @@ static void TestShortProfileTimerFailure(void) EXPECT_U(PLSR_STATUS_ERROR, ReadStatus()); EXPECT_U(PLSR_ERROR_TIMER, ReadError()); EXPECT_I(1L, ReadPosition()); + ExpectDiagnosticInterrupted(10UL, 1UL); } static void TestStopImmediatelyAfterSubsequentHandoff(void) @@ -1331,6 +2720,177 @@ static void TestCurrentFrequencyIsDynamic(void) StopAndSettle(); } +static void StartMaximumShortProfile(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 100000UL, 1000UL, 1000UL, 100U, 100U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 100000UL, 258L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(256U, PlsrTestProfileQueueCount()); +} + +static void TestProfileQueueStaleDoesNotAdvance(void) +{ + uint32_t readIndex; + uint32_t headFrequencyHz; + uint16_t producerPeriod; + uint16_t activePeriod; + + StartMaximumShortProfile(); + readIndex = PlsrTestProfileQueueReadIndex(); + headFrequencyHz = PlsrTestProfileQueueHeadFrequency(); + producerPeriod = PlsrTestProfileProducerNextPeriod(); + activePeriod = PlsrTestActiveProfileNextPeriod(); + EXPECT_TRUE(headFrequencyHz != 0UL); + + PlsrTestStaleNextFrequencyAtUpdate(); + PlsrTestEmitPulses(1UL); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(readIndex, PlsrTestProfileQueueReadIndex()); + EXPECT_U(256U, PlsrTestProfileQueueCount()); + EXPECT_U(headFrequencyHz, PlsrTestProfileQueueHeadFrequency()); + EXPECT_U(producerPeriod, PlsrTestProfileProducerNextPeriod()); + EXPECT_U(activePeriod, PlsrTestActiveProfileNextPeriod()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + + PlsrTestEmitPulses(1UL); + EXPECT_U(readIndex + 1UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(255U, PlsrTestProfileQueueCount()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); +} + +static void TestProfileQueueRetargetInvalidatesGeneration(void) +{ + uint32_t generationBefore; + uint32_t generationAfterWrite; + + StartMaximumShortProfile(); + generationBefore = PlsrTestProfileQueueGeneration(); + EXPECT_U(PLSR_MB_OK, WriteU32(0x1100U, 2000UL)); + generationAfterWrite = PlsrTestProfileQueueGeneration(); + EXPECT_TRUE(generationAfterWrite != generationBefore); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_U(0UL, PlsrTestProfileQueueReadIndex()); + EXPECT_U(0UL, PlsrTestProfileQueueWriteIndex()); + + PlsrPoll1ms(); + EXPECT_TRUE(PlsrTestProfileQueueGeneration() != generationAfterWrite); + EXPECT_U(0U, PlsrTestProfileQueueCount()); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); +} + +static void TestFinalPulseGatesBeforeDiagnosticFinish(void) +{ + uint32_t gateEvent; + uint32_t diagnosticEvent; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 1000UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 1L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(1UL); + + gateEvent = PlsrTestLastGateEvent(); + diagnosticEvent = PlsrTestLastDiagnosticFinishEvent(); + EXPECT_TRUE(gateEvent != 0UL); + EXPECT_U(gateEvent + 1UL, diagnosticEvent); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_U(PLSR_DIAG_COUNT_PASS, + ReadWord(PLSR_DIAG_FLAGS_ADDRESS) & PLSR_DIAG_COUNT_PASS); +} + +static void TestDeferredFrequencyRetriesAfterStale(void) +{ + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 1000UL, 100UL, 0U, 0U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 100L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + EXPECT_U(PLSR_MB_OK, WriteU32(0x1100U, 2000UL)); + PlsrPoll1ms(); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(1000UL, PlsrTestQueuedFrequency()); + + PlsrTestStaleNextFrequencyAtUpdate(); + PlsrTestEmitPulses(1UL); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(1000UL, PlsrTestQueuedFrequency()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + + PlsrTestEmitPulses(1UL); + EXPECT_U(1000UL, PlsrTestOutputFrequency()); + EXPECT_U(2000UL, PlsrTestQueuedFrequency()); + EXPECT_I(2L, ReadPosition()); + + PlsrTestEmitPulses(1UL); + EXPECT_U(2000UL, PlsrTestOutputFrequency()); + EXPECT_U(2000UL, PlsrTestQueuedFrequency()); + EXPECT_I(3L, ReadPosition()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + StopAndSettle(); +} + +static void TestShortProfileRetriesSameSampleAfterStale(void) +{ + uint32_t expectedThirdFrequencyHz; + uint32_t expectedFourthFrequencyHz; + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 100UL, 100UL, 1000U, 1000U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 10L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + PlsrTestEmitPulses(1UL); + expectedThirdFrequencyHz = PlsrTestQueuedFrequency(); + PlsrTestEmitPulses(1UL); + expectedFourthFrequencyHz = PlsrTestQueuedFrequency(); + EXPECT_TRUE(expectedThirdFrequencyHz != expectedFourthFrequencyHz); + + ResetCore(); + ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, + 1000UL, 100UL, 100UL, 1000U, 1000U); + EXPECT_U(PLSR_MB_OK, + SetSegment(1U, 1000UL, 10L, PLSR_EXT_OR_COMPLETE, + 0U, 0U, 0U)); + EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); + + PlsrTestStaleNextFrequencyAtUpdate(); + PlsrTestEmitPulses(1UL); + EXPECT_U(1U, PlsrTestPulseIsActive()); + EXPECT_U(PlsrTestOutputFrequency(), PlsrTestQueuedFrequency()); + EXPECT_I(1L, ReadPosition()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + + PlsrTestEmitPulses(1UL); + EXPECT_U(expectedThirdFrequencyHz, PlsrTestQueuedFrequency()); + EXPECT_I(2L, ReadPosition()); + + PlsrTestEmitPulses(1UL); + EXPECT_U(expectedThirdFrequencyHz, PlsrTestOutputFrequency()); + EXPECT_U(expectedFourthFrequencyHz, PlsrTestQueuedFrequency()); + EXPECT_I(3L, ReadPosition()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); + PlsrTestEmitPulses(7UL); + EXPECT_U(0U, PlsrTestPulseIsActive()); + EXPECT_I(10L, ReadPosition()); + PlsrPoll1ms(); + EXPECT_U(PLSR_STATUS_COMPLETED, ReadStatus()); + EXPECT_U(PLSR_ERROR_NONE, ReadError()); +} + static void TestPollMailboxDefersPlatformFailure(void) { ResetCore(); @@ -1704,6 +3264,8 @@ static void TestCommandMailboxValidatesBeforeQueue(void) static void TestCommandMailboxStartFailureBecomesError(void) { + uint16_t flags; + ResetCore(); ConfigureCommon(0U, PLSR_POSITION_RELATIVE, 1U, PLSR_SEND_COMPLETE, 1000UL, 1000UL, 1000UL, 0U, 0U); @@ -1721,6 +3283,9 @@ static void TestCommandMailboxStartFailureBecomesError(void) EXPECT_U(PLSR_ERROR_INVALID_RESOURCE, ReadError()); EXPECT_U(0U, ReadCurrentSegment()); EXPECT_U(0U, PlsrTestPulseIsActive()); + flags = ReadWord(PLSR_DIAG_FLAGS_ADDRESS); + EXPECT_U(0U, flags & PLSR_DIAG_MONITORING_ACTIVE); + EXPECT_U(0U, flags & PLSR_DIAG_FAULT_LATCHED); EXPECT_U(PLSR_MB_DEVICE_BUSY, QueueCommand(PLSR_COMMAND_START)); EXPECT_U(PLSR_MB_OK, QueueCommand(PLSR_COMMAND_CLEAR)); @@ -1776,6 +3341,22 @@ static void TestPersistenceAcrossReinit(void) EXPECT_I(0L, ReadPosition()); } +static void TestFlashStartupRecoveryDecision(void) +{ + EXPECT_U(1U, PlsrTestFlashNeedsStartupRecovery(0U, 1U, 0UL, + 1U, 0UL)); + EXPECT_U(0U, PlsrTestFlashNeedsStartupRecovery(1U, 1U, 0UL, + 1U, 0UL)); + EXPECT_U(0U, PlsrTestFlashNeedsStartupRecovery(0U, 1U, 0x080C0000UL, + 1U, 0UL)); + EXPECT_U(0U, PlsrTestFlashNeedsStartupRecovery(0U, 1U, 0UL, + 1U, 0x080E0000UL)); + EXPECT_U(0U, PlsrTestFlashNeedsStartupRecovery(0U, 0U, 0UL, + 1U, 0UL)); + EXPECT_U(0U, PlsrTestFlashNeedsStartupRecovery(0U, 1U, 0UL, + 0U, 0UL)); +} + static void TestPositionSchedulesFlashSave(void) { unsigned int tick; @@ -1789,16 +3370,19 @@ static void TestPositionSchedulesFlashSave(void) for (tick = 0U; tick < 1001U; tick++) { PlsrPoll1ms(); + PlsrServicePersistence(); } PlsrTestResetSaveCount(); EXPECT_U(PLSR_MB_OK, SendCommand(PLSR_COMMAND_START)); PlsrTestEmitPulses(1UL); PlsrPoll1ms(); + PlsrServicePersistence(); EXPECT_U(0UL, PlsrTestSaveCount()); for (tick = 0U; tick < 1001U; tick++) { PlsrPoll1ms(); + PlsrServicePersistence(); } EXPECT_U(1UL, PlsrTestSaveCount()); @@ -1806,6 +3390,7 @@ static void TestPositionSchedulesFlashSave(void) for (tick = 0U; tick < 1001U; tick++) { PlsrPoll1ms(); + PlsrServicePersistence(); } EXPECT_U(2UL, PlsrTestSaveCount()); } @@ -1878,13 +3463,62 @@ static const TEST_CASE TestCases[] = { {"u64_by_u32_division", TestU64ByU32Division}, {"protocol_boundaries", TestProtocolBoundaries}, + {"ab_output_pairs_phase_sequence", TestAbOutputPairsAndPhaseSequence}, + {"ab_single_pulse_100khz_matrix", + TestAbSinglePulseMaximumFrequencyMatrix}, + {"ab_fast_gate_cleanup_deferred_to_poll", + TestAbFastGateCleanupIsDeferredToPoll}, + {"ab_final_arm_job_tail_chain_once", + TestAbFinalArmJobTailChainsOnce}, + {"ab_final_boundary_before_arm_job_noop", + TestAbFinalBoundaryBeforeArmJobIsNoOp}, + {"ab_final_arm_job_failure_no_final_count", + TestAbFinalArmJobFailureDoesNotCountFinalPulse}, + {"ab_stop_mailbox_pending_boundary", + TestAbStopMailboxAtPendingBoundary}, + {"ab_act_ext_cut_zero_boundary", TestAbActAndExtCutsFinishAtZero}, + {"ab_subsequent_single_pulse_continuous", + TestAbSubsequentSinglePulsesStayContinuous}, + {"ab_armed_frequency_write", TestAbArmedFrequencyWriteDoesNotReopenOutput}, + {"ab_stop_request_forced_fault", TestAbStopRequestForcedFault}, + {"ab_stop_after_final_boundary_armed", + TestAbStopAfterFinalBoundaryIsArmed}, + {"ab_stop_arm_latched_final_quarter_once", + TestAbStopArmConsumesLatchedFinalQuarterOnce}, + {"ab_rejects_unpaired_outputs", TestAbRejectsUnpairedOutputs}, + {"ab_stop_complete_cycle_boundary", TestAbStopAtCompleteCycleBoundary}, + {"ab_dynamic_frequency_zero_boundary", + TestAbDynamicFrequencyChangesOnlyAtZeroPhase}, + {"ab_stale_frequency_commit_after_completion", + TestAbStaleFrequencyCommitAfterNaturalCompletion}, + {"ab_direction_reversal_zero_restart", + TestAbDirectionReversalRestartsFromZeroPhase}, + {"ab_mode_persistence", TestAbModePersistence}, + {"diagnostic_pass", TestDiagnosticPass}, + {"diagnostic_count_fault_clear", TestDiagnosticCountFaultAndClear}, + {"diagnostic_frequency_fault_clear", + TestDiagnosticFrequencyFaultAndClear}, + {"diagnostic_curve_fault_clear", TestDiagnosticCurveFaultAndClear}, + {"diagnostic_interrupted_segments", TestDiagnosticInterruptedSegments}, + {"diagnostic_fault_latch_explicit_clear", + TestDiagnosticFaultLatchNeedsExplicitClear}, + {"diagnostic_frequency_pass_latched", + TestDiagnosticFrequencyPassStaysFailed}, + {"diagnostic_curve_counter_saturation", + TestDiagnosticCurveCountersSaturate}, {"wait_zero_one_ms", TestWaitZeroUsesOneMillisecond}, {"act_zero_no_pulse", TestActZeroSkipsWithoutPulse}, {"relative_absolute_zero", TestRelativeAndAbsoluteZeroDisplacement}, + {"ten_segments_sequence", TestAllTenSegmentsRunInSequence}, + {"ten_segments_jump_chain", TestAllTenSegmentsRunThroughJumpChain}, + {"start_segment_ten", TestStartSegmentTenRunsNormally}, {"self_jump_stop", TestSelfJumpCanStop}, {"stop_deceleration", TestStopDeceleratesBeforeCut}, {"stop_pending_boundary", TestStopAtPendingBoundary}, {"direction_delay_one_ms", TestOneMillisecondDirectionDelay}, + {"direction_output_polarity_matrix", TestDirectionOutputPolarityMatrix}, + {"direction_same_reverse_segments", TestDirectionSameAndReverseSegments}, + {"direction_output_change", TestDirectionOutputCanChangeBetweenCommands}, {"ext_edge_at_natural_boundary", TestExtEdgeAtNaturalBoundary}, {"ext_cut_natural_boundary_interleavings", TestExtCutAndNaturalBoundaryInterleavings}, @@ -1893,12 +3527,19 @@ static const TEST_CASE TestCases[] = {"ext_edge_seamless_epoch", TestExtEdgeDoesNotCutSeamlessNextSegment}, {"ramp_seamless_epoch", TestOldRampDoesNotRetargetSeamlessNextSegment}, {"short_profile_boundary_matrix", TestShortProfileBoundaryMatrix}, + {"short_profile_258_fully_precomputed", + TestShortProfile258IsFullyPrecomputed}, {"short_final_no_poll", TestShortFinalDeceleratesWithoutPoll}, {"zero_to_maximum_ramp_duration", TestZeroToMaximumRampKeepsConfiguredDuration}, - {"maximum_pulse_ramp_duration", - TestMaximumPulseRampKeepsReachableDuration}, - {"maximum_single_ramp_no_poll", TestMaximumSingleRampWithoutPoll}, + {"long_profile_259_1ms_ramp", TestLongProfile259UsesMillisecondRamp}, + {"maximum_profile_1ms_cadence", + TestMaximumProfileOneMillisecondCadence}, + {"profile_queue_stale_no_advance", TestProfileQueueStaleDoesNotAdvance}, + {"profile_queue_retarget_generation", + TestProfileQueueRetargetInvalidatesGeneration}, + {"final_pulse_gate_before_diagnostic", + TestFinalPulseGatesBeforeDiagnosticFinish}, {"short_timer_failure", TestShortProfileTimerFailure}, {"stop_after_subsequent_handoff", TestStopImmediatelyAfterSubsequentHandoff}, @@ -1906,6 +3547,10 @@ static const TEST_CASE TestCases[] = {"short_dynamic_retarget", TestShortProfileDynamicRetarget}, {"short_ext_cut", TestShortProfileExtCut}, {"current_frequency_dynamic", TestCurrentFrequencyIsDynamic}, + {"deferred_frequency_retries_after_stale", + TestDeferredFrequencyRetriesAfterStale}, + {"short_profile_retries_same_sample_after_stale", + TestShortProfileRetriesSameSampleAfterStale}, {"poll_mailbox_failure", TestPollMailboxDefersPlatformFailure}, {"future_frequency_on_arrival", TestFutureSegmentFrequencyAppliesOnArrival}, @@ -1928,6 +3573,7 @@ static const TEST_CASE TestCases[] = TestCommandMailboxStartFailureBecomesError}, {"wait_signal_positive", TestWaitSignalPositivePath}, {"persistence_reinit", TestPersistenceAcrossReinit}, + {"flash_startup_recovery_decision", TestFlashStartupRecoveryDecision}, {"position_flash_save", TestPositionSchedulesFlashSave}, {"busy_reset_absolute_gate", TestBusyResetInvalidatesAbsolutePosition}, {"position_overflow", TestPositionOverflowStopsWithError} @@ -1945,6 +3591,7 @@ int main(void) CurrentTest = TestCases[index].name; (void)printf("RUN %s\n", CurrentTest); + (void)fflush(stdout); TestCases[index].function(); if (FailureCount == failuresBefore) {

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