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NXP_MKV56F512/drivers/fsl_ftfx_adapter.h

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  1. /*

  2.  * Copyright 2017-2020 NXP

  3.  * All rights reserved.

  4.  *

  5.  * SPDX-License-Identifier: BSD-3-Clause

  6.  *

  7.  */

  8. 

  9. #ifndef FSL_FTFX_ADAPTER_H

  10. #define FSL_FTFX_ADAPTER_H

  11. 

  12. /*******************************************************************************

  13.  * Definitions

  14.  ******************************************************************************/

  15. 

  16. #define INVALID_REG_MASK (0)

  17. #define INVALID_REG_SHIFT (0)

  18. #define INVALID_REG_ADDRESS (NULL)

  19. #define INVALID_REG_VALUE (0x00U)

  20. 

  21. /* @brief Flash register access type defines */

  22. #define FTFx_REG8_ACCESS_TYPE volatile uint8_t *

  23. #define FTFx_REG32_ACCESS_TYPE volatile uint32_t *

  24. 

  25. /*!

  26.  * @name Common flash register info defines

  27.  * @{

  28.  */

  29. #if defined(FTFA)

  30. #define FTFx FTFA

  31. #define FTFx_BASE FTFA_BASE

  32. #define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK

  33. #define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK

  34. #define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK

  35. #define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK

  36. #define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK

  37. #define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK

  38. #define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK

  39. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM

  40. #define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK

  41. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */

  42. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM

  43. #define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK

  44. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */

  45. #elif defined(FTFE)

  46. #define FTFx FTFE

  47. #define FTFx_BASE FTFE_BASE

  48. #define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK

  49. #define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK

  50. #define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK

  51. #define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK

  52. #define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK

  53. #define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK

  54. #define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK

  55. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM

  56. #define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK

  57. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */

  58. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM

  59. #define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK

  60. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */

  61. #elif defined(FTFL)

  62. #define FTFx FTFL

  63. #define FTFx_BASE FTFL_BASE

  64. #define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK

  65. #define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK

  66. #define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK

  67. #define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK

  68. #define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK

  69. #define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK

  70. #define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK

  71. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM

  72. #define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK

  73. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */

  74. #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM

  75. #define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK

  76. #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */

  77. #else

  78. #error "Unknown flash controller"

  79. #endif

  80. /*@}*/

  81. 

  82. /*!

  83.  * @name Common flash register access info defines

  84.  * @{

  85.  */

  86. #define FTFx_FCCOB3_REG (FTFx->FCCOB3)

  87. #define FTFx_FCCOB5_REG (FTFx->FCCOB5)

  88. #define FTFx_FCCOB6_REG (FTFx->FCCOB6)

  89. #define FTFx_FCCOB7_REG (FTFx->FCCOB7)

  90. 

  91. #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)

  92. #if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK)

  93. #define FTFx_FLASH1_HAS_INT_PROT_REG (1)

  94. #define FTFx_FPROTSH_REG (FTFx->FPROTSH)

  95. #define FTFx_FPROTSL_REG (FTFx->FPROTSL)

  96. #else

  97. #define FTFx_FLASH1_HAS_INT_PROT_REG (0)

  98. #endif

  99. #endif

  100. 

  101. #if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK)

  102. #define FTFx_FLASH0_HAS_HIGH_PROT_REG (1)

  103. #define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3)

  104. #define FTFx_FPROTH3_REG (FTFx->FPROTH3)

  105. #define FTFx_FPROTH2_REG (FTFx->FPROTH2)

  106. #define FTFx_FPROTH1_REG (FTFx->FPROTH1)

  107. #define FTFx_FPROTH0_REG (FTFx->FPROTH0)

  108. #else

  109. #define FTFx_FLASH0_HAS_HIGH_PROT_REG (0)

  110. #endif

  111. 

  112. #if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK)

  113. #define FTFx_FPROT_LOW_REG (FTFx->FPROTL3)

  114. #define FTFx_FPROTL3_REG (FTFx->FPROTL3)

  115. #define FTFx_FPROTL2_REG (FTFx->FPROTL2)

  116. #define FTFx_FPROTL1_REG (FTFx->FPROTL1)

  117. #define FTFx_FPROTL0_REG (FTFx->FPROTL0)

  118. #elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK)

  119. #define FTFx_FPROT_LOW_REG (FTFx->FPROT3)

  120. #define FTFx_FPROTL3_REG (FTFx->FPROT3)

  121. #define FTFx_FPROTL2_REG (FTFx->FPROT2)

  122. #define FTFx_FPROTL1_REG (FTFx->FPROT1)

  123. #define FTFx_FPROTL0_REG (FTFx->FPROT0)

  124. #endif

  125. 

  126. #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)

  127. #if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK)

  128. #define FTFx_FLASH1_HAS_INT_XACC_REG (1)

  129. #define FTFx_XACCSH_REG (FTFx->XACCSH)

  130. #define FTFx_XACCSL_REG (FTFx->XACCSL)

  131. #define FTFx_FACSSS_REG (FTFx->FACSSS)

  132. #define FTFx_FACSNS_REG (FTFx->FACSNS)

  133. #else

  134. #define FTFx_FLASH1_HAS_INT_XACC_REG (0)

  135. #endif

  136. #endif

  137. 

  138. #if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \

  139.      defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK))

  140. #define FTFx_FLASH0_HAS_INT_XACC_REG (1)

  141. #define FTFx_XACCH3_REG (FTFx->XACCH3)

  142. #define FTFx_XACCL3_REG (FTFx->XACCL3)

  143. #define FTFx_FACSS_REG (FTFx->FACSS)

  144. #define FTFx_FACSN_REG (FTFx->FACSN)

  145. #else

  146. #define FTFx_FLASH0_HAS_INT_XACC_REG (0)

  147. #endif

  148. /*@}*/

  149. 

  150. /*!

  151.  * @brief MCM cache register access info defines.

  152.  */

  153. #if defined(MCM_PLACR_CFCC_MASK)

  154. #define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK

  155. #define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT

  156. #if defined(MCM0)

  157. #define MCM0_CACHE_REG MCM0->PLACR

  158. #elif defined(MCM) && (!defined(MCM1))

  159. #define MCM0_CACHE_REG MCM->PLACR

  160. #endif

  161. #if defined(MCM1)

  162. #define MCM1_CACHE_REG MCM1->PLACR

  163. #elif defined(MCM) && (!defined(MCM0))

  164. #define MCM1_CACHE_REG MCM->PLACR

  165. #endif

  166. #else

  167. #define MCM_CACHE_CLEAR_MASK INVALID_REG_MASK

  168. #define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT

  169. #define MCM0_CACHE_REG (INVALID_REG_ADDRESS)

  170. #define MCM1_CACHE_REG (INVALID_REG_ADDRESS)

  171. #endif

  172. 

  173. /*!

  174.  * @brief FMC cache register access info defines.

  175.  */

  176. #if defined(FMC_PFB01CR_S_INV_MASK)

  177. #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_INV_MASK

  178. #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT

  179. #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR

  180. #elif defined(FMC_PFB01CR_S_B_INV_MASK)

  181. #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_B_INV_MASK

  182. #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT

  183. #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR

  184. #elif defined(FMC_PFB0CR_S_INV_MASK)

  185. #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_INV_MASK

  186. #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT

  187. #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR

  188. #elif defined(FMC_PFB0CR_S_B_INV_MASK)

  189. #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_B_INV_MASK

  190. #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT

  191. #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR

  192. #else

  193. #define FMC_SPECULATION_INVALIDATE_MASK INVALID_REG_MASK

  194. #define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT

  195. #define FMC_SPECULATION_INVALIDATE(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)

  196. #define FMC_SPECULATION_INVALIDATE_REG (INVALID_REG_ADDRESS)

  197. #endif

  198. 

  199. #if defined(FMC_PFB01CR_CINV_WAY_MASK)

  200. #define FMC_CACHE_CLEAR_MASK FMC_PFB01CR_CINV_WAY_MASK

  201. #define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT

  202. #define FMC_CACHE_CLEAR(x) FMC_PFB01CR_CINV_WAY(x)

  203. #elif defined(FMC_PFB0CR_CINV_WAY_MASK)

  204. #define FMC_CACHE_CLEAR_MASK FMC_PFB0CR_CINV_WAY_MASK

  205. #define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT

  206. #define FMC_CACHE_CLEAR(x) FMC_PFB0CR_CINV_WAY(x)

  207. #else

  208. #define FMC_CACHE_CLEAR_MASK INVALID_REG_MASK

  209. #define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT

  210. #define FMC_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)

  211. #endif

  212. 

  213. #if defined(FMC_PFB01CR_B0DPE_MASK)

  214. #define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK

  215. #define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK

  216. #define FMC_CACHE_REG FMC->PFB01CR

  217. #elif defined(FMC_PFB0CR_B0DPE_MASK)

  218. #define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK

  219. #define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK

  220. #define FMC_CACHE_REG FMC->PFB0CR

  221. #else

  222. #define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK

  223. #define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK

  224. #define FMC_CACHE_REG (INVALID_REG_ADDRESS)

  225. #endif

  226. 

  227. /*!

  228.  * @brief MSCM cache register access info defines.

  229.  */

  230. #if defined(MSCM_OCMDR_OCM1_MASK)

  231. #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCM1_MASK

  232. #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT

  233. #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCM1(x)

  234. #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)

  235. #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR0_OCM1_MASK

  236. #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT

  237. #define MSCM_SPECULATION_SET(x) MSCM_OCMDR0_OCM1(x)

  238. #elif defined(MSCM_OCMDR_OCMC1_MASK)

  239. #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCMC1_MASK

  240. #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT

  241. #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCMC1(x)

  242. #else

  243. #define MSCM_SPECULATION_SET_MASK INVALID_REG_MASK

  244. #define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT

  245. #define MSCM_SPECULATION_SET(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)

  246. #endif

  247. 

  248. #if defined(MSCM_OCMDR_OCM2_MASK)

  249. #define MSCM_CACHE_CLEAR_MASK MSCM_OCMDR_OCM2_MASK

  250. #define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT

  251. #define MSCM_CACHE_CLEAR(x) MSCM_OCMDR_OCM2(x)

  252. #else

  253. #define MSCM_CACHE_CLEAR_MASK INVALID_REG_MASK

  254. #define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT

  255. #define MSCM_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK)

  256. #endif

  257. 

  258. #if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK)

  259. #define MSCM_OCMDR0_REG MSCM->OCMDR[0]

  260. #define MSCM_OCMDR1_REG MSCM->OCMDR[1]

  261. #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK)

  262. #define MSCM_OCMDR0_REG MSCM->OCMDR0

  263. #define MSCM_OCMDR1_REG MSCM->OCMDR1

  264. #else

  265. #define MSCM_OCMDR0_REG (INVALID_REG_ADDRESS)

  266. #define MSCM_OCMDR1_REG (INVALID_REG_ADDRESS)

  267. #endif

  268. 

  269. /*!

  270.  * @brief MSCM prefetch speculation defines.

  271.  */

  272. #define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U)

  273. #define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U)

  274. #define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U)

  275. #define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U)

  276. 

  277. /*!

  278.  * @brief SIM PFSIZE register access info defines.

  279.  */

  280. #if defined(SIM_FCFG1_CORE0_PFSIZE_MASK)

  281. #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_CORE0_PFSIZE_MASK

  282. #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT

  283. #define SIM_FCFG1_REG SIM->FCFG1

  284. #elif defined(SIM_FCFG1_PFSIZE_MASK)

  285. #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_PFSIZE_MASK

  286. #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT

  287. #define SIM_FCFG1_REG SIM->FCFG1

  288. #else

  289. #define SIM_FLASH0_PFSIZE_MASK INVALID_REG_MASK

  290. #define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT

  291. #define SIM_FCFG1_REG INVALID_REG_VALUE

  292. #endif

  293. 

  294. #if defined(SIM_FCFG1_CORE1_PFSIZE_MASK)

  295. #define SIM_FLASH1_PFSIZE_MASK SIM_FCFG1_CORE1_PFSIZE_MASK

  296. #define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT

  297. #else

  298. #define SIM_FLASH1_PFSIZE_MASK INVALID_REG_MASK

  299. #define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT

  300. #endif

  301. 

  302. /*!

  303.  * @name Dual core/flash configuration

  304.  * @{

  305.  */

  306. /*! @brief Redefines some flash features. */

  307. #if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID)

  308. #if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u)

  309. #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS

  310. #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT

  311. #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE

  312. #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE

  313. #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE

  314. #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  315. #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  316. #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT

  317. #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS

  318. #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT

  319. #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE

  320. #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE

  321. #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE

  322. #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \

  323.     defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)

  324. #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT

  325. #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT

  326. #else

  327. #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  328. #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  329. #endif

  330. #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT

  331. #elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u)

  332. #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS

  333. #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT

  334. #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE

  335. #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE

  336. #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE

  337. #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \

  338.     defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT)

  339. #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT

  340. #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT

  341. #else

  342. #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  343. #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  344. #endif

  345. #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT

  346. #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS

  347. #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT

  348. #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE

  349. #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE

  350. #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE

  351. #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  352. #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  353. #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT

  354. #endif

  355. #else /* undfine FSL_FEATURE_FLASH_CURRENT_CORE_ID */

  356. #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS

  357. #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT

  358. #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE

  359. #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE

  360. #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE

  361. #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  362. #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  363. #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT

  364. #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)

  365. #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS

  366. #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT

  367. #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE

  368. #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE

  369. #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE

  370. #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT

  371. #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT

  372. #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT

  373. #else /* undfine FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH or FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS */

  374. #define FLASH1_FEATURE_PFLASH_START_ADDRESS 0

  375. #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT 0

  376. #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE 0

  377. #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE 0

  378. #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE 0

  379. #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 0

  380. #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0

  381. #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 0

  382. #endif

  383. #endif

  384. 

  385. #if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT

  386. #define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT

  387. #else

  388. #define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT

  389. #endif

  390. 

  391. /*@}*/

  392. 

  393. #endif /* FSL_FTFX_ADAPTER_H */