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5.4 KiB

  1. /*
  2. * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2017 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef _FSL_CRC_H_
  9. #define _FSL_CRC_H_
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup crc
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @name Driver version */
  19. /*@{*/
  20. /*! @brief CRC driver version. Version 2.0.1.
  21. *
  22. * Current version: 2.0.1
  23. *
  24. * Change log:
  25. * - Version 2.0.1
  26. * - move DATA and DATALL macro definition from header file to source file
  27. * - Version 2.0.2
  28. * - Fix MISRA issues
  29. */
  30. #define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
  31. /*@}*/
  32. #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
  33. /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
  34. #define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
  35. #endif
  36. /*! @brief CRC bit width */
  37. typedef enum _crc_bits
  38. {
  39. kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */
  40. kCrcBits32 = 1U /*!< Generate 32-bit CRC code */
  41. } crc_bits_t;
  42. /*! @brief CRC result type */
  43. typedef enum _crc_result
  44. {
  45. kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum.
  46. Reflect out and final xor protocol features are applied. */
  47. kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
  48. Reflect out and final xor protocol feature are not applied.
  49. Intermediate checksum can be used as a seed for CRC_Init()
  50. to continue adding data to this checksum. */
  51. } crc_result_t;
  52. /*!
  53. * @brief CRC protocol configuration.
  54. *
  55. * This structure holds the configuration for the CRC protocol.
  56. *
  57. */
  58. typedef struct _crc_config
  59. {
  60. uint32_t polynomial; /*!< CRC Polynomial, MSBit first.
  61. Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
  62. uint32_t seed; /*!< Starting checksum value */
  63. bool reflectIn; /*!< Reflect bits on input. */
  64. bool reflectOut; /*!< Reflect bits on output. */
  65. bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
  66. crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
  67. crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
  68. CRC_Get32bitResult() */
  69. } crc_config_t;
  70. /*******************************************************************************
  71. * API
  72. ******************************************************************************/
  73. #if defined(__cplusplus)
  74. extern "C" {
  75. #endif
  76. /*!
  77. * @brief Enables and configures the CRC peripheral module.
  78. *
  79. * This function enables the clock gate in the SIM module for the CRC peripheral.
  80. * It also configures the CRC module and starts a checksum computation by writing the seed.
  81. *
  82. * @param base CRC peripheral address.
  83. * @param config CRC module configuration structure.
  84. */
  85. void CRC_Init(CRC_Type *base, const crc_config_t *config);
  86. /*!
  87. * @brief Disables the CRC peripheral module.
  88. *
  89. * This function disables the clock gate in the SIM module for the CRC peripheral.
  90. *
  91. * @param base CRC peripheral address.
  92. */
  93. static inline void CRC_Deinit(CRC_Type *base)
  94. {
  95. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  96. /* gate clock */
  97. CLOCK_DisableClock(kCLOCK_Crc0);
  98. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  99. }
  100. /*!
  101. * @brief Loads default values to the CRC protocol configuration structure.
  102. *
  103. * Loads default values to the CRC protocol configuration structure. The default values are as follows.
  104. * @code
  105. * config->polynomial = 0x1021;
  106. * config->seed = 0xFFFF;
  107. * config->reflectIn = false;
  108. * config->reflectOut = false;
  109. * config->complementChecksum = false;
  110. * config->crcBits = kCrcBits16;
  111. * config->crcResult = kCrcFinalChecksum;
  112. * @endcode
  113. *
  114. * @param config CRC protocol configuration structure.
  115. */
  116. void CRC_GetDefaultConfig(crc_config_t *config);
  117. /*!
  118. * @brief Writes data to the CRC module.
  119. *
  120. * Writes input data buffer bytes to the CRC data register.
  121. * The configured type of transpose is applied.
  122. *
  123. * @param base CRC peripheral address.
  124. * @param data Input data stream, MSByte in data[0].
  125. * @param dataSize Size in bytes of the input data buffer.
  126. */
  127. void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
  128. /*!
  129. * @brief Reads the 32-bit checksum from the CRC module.
  130. *
  131. * Reads the CRC data register (either an intermediate or the final checksum).
  132. * The configured type of transpose and complement is applied.
  133. *
  134. * @param base CRC peripheral address.
  135. * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
  136. */
  137. uint32_t CRC_Get32bitResult(CRC_Type *base);
  138. /*!
  139. * @brief Reads a 16-bit checksum from the CRC module.
  140. *
  141. * Reads the CRC data register (either an intermediate or the final checksum).
  142. * The configured type of transpose and complement is applied.
  143. *
  144. * @param base CRC peripheral address.
  145. * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
  146. */
  147. uint16_t CRC_Get16bitResult(CRC_Type *base);
  148. #if defined(__cplusplus)
  149. }
  150. #endif
  151. /*!
  152. *@}
  153. */
  154. #endif /* _FSL_CRC_H_ */