diff --git a/PLSR/PLSR/Core/Inc/tim.h b/PLSR/PLSR/Core/Inc/tim.h index 028bf5f..5f1741f 100644 --- a/PLSR/PLSR/Core/Inc/tim.h +++ b/PLSR/PLSR/Core/Inc/tim.h @@ -28,6 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "usart.h" +#include "math.h" /* USER CODE BEGIN Includes */ @@ -138,7 +139,6 @@ typedef struct { uint32_t target_freq; // 目标频率(Hz) uint32_t target_pulse; // 目标脉冲数 uint8_t next_section; // 下一段号(0表示结束) - //PLSR_SectionState_t section_state; // 段状态 PLSR_WaitCondition_t wait_condition; // 等待条件 } PLSR_SectionConfig_t; @@ -160,8 +160,8 @@ typedef struct { // 运行状态参数 PLSR_RunState_t run_state; // 运行状态 - uint32_t accel_step_count; // 加速步数计数 - uint32_t decel_step_count; // 减速步数计数 + uint32_t accel_pulse_count; // 加速脉冲数 + uint32_t decel_pulse_count; // 减速脉冲数 uint32_t const_pulse_count; // 匀速脉冲计数 uint32_t freq_step; // 频率步长 uint32_t wait_start_tick; // 等待开始时间 @@ -172,6 +172,12 @@ typedef struct { uint16_t start_section; //<起始段数 uint32_t default_freq; //<脉冲默认速度 + // 新增：默认加减速参数 + uint32_t default_accel_time_ms; // 默认加速时间(ms) + uint32_t default_decel_time_ms; // 默认减速时间(ms) + uint32_t accel_rate; // 加速度(Hz/ms) = default_freq / default_accel_time_ms + uint32_t decel_rate; // 减速度(Hz/ms) = default_freq / default_decel_time_ms + PLSR_SectionConfig_t section[PLSR_MAX_SECTIONS]; // 段配置数组 } PLSR_RouteConfig_t; @@ -184,7 +190,7 @@ typedef struct { #define PLSR_DEFAULT_START_SECTION 0 // 默认起始段编号 #define PLSR_TASK_CHECK_INTERVAL 100 // 每100个脉冲通知任务一次 - +extern uint32_t g_plsr_total_pulse_count; @@ -211,7 +217,8 @@ void PLSR_Section_StartNewSection(PLSR_RouteConfig_t* route); //<启动新 // ==================== PLSR加减速算法函数 ==================== float PLSR_Accel_CalculateCurve(float progress); //<曲线加速算法 float PLSR_Accel_CalculateSine(float progress); //<正弦加速算法 -void PLSR_Accel_Process(PLSR_RouteConfig_t* route); //<加减速执行函数 +void PLSR_Accel_Process(PLSR_RouteConfig_t* route); //<加减速执行函数(新的直线加减速) +void PLSR_Accel_UpdateRates(PLSR_RouteConfig_t* route); //<更新加减速度 // ==================== PLSR等待条件处理函数 ==================== void PLSR_Wait_StartTimer(PLSR_RouteConfig_t* route); //<等待条件计数器 @@ -220,10 +227,7 @@ uint8_t PLSR_Wait_CheckExtEvent(PLSR_RouteConfig_t* route); //<检查外部 void PLSR_SetExtEvent(uint8_t flag); //<设置外部事件标志->调用:外部触发PLSR_SetExtEvent(1); void PLSR_ClearExtEvent(void); //<清除外部事件标志 void PLSR_SetSectionCondition(PLSR_RouteConfig_t* route, uint8_t section_num, uint8_t flag); //<设置段等待条件标志,暂不考虑 -uint32_t PLSR_GetWaitTick(void); - -// UCOSII任务相关函数 -uint8_t PLSR_CheckTaskNotification(void); +uint32_t PLSR_GetWaitTick(void); //<暂时无用 // ==================== PLSR计数器控制函数 ==================== //定时器2相关 void PLSR_Counter_Start(void); @@ -239,14 +243,15 @@ void PLSR_TIM6_Start(void); //<在路径开始 void PLSR_TIM6_Stop(void); - void PLSR_Accel_CalculateSteps(PLSR_RouteConfig_t* route, uint32_t time_ms, uint8_t is_accel); //<计算加减速步数 +// 注意：PLSR_Accel_CalculateSteps函数已被删除，改为使用新的直线加减速算法 void PLSR_Section_ProcessConstSpeed(PLSR_RouteConfig_t* route); //<匀速状态处理,检查段脉冲是否发完,若完成进入等待模式 void PLSR_ChackWait_End(PLSR_RouteConfig_t* route); //<检查等待条件是否成立,满足条件进行段切换 uint8_t PLSR_Section_CheckPulseComplete(PLSR_RouteConfig_t* route); //<检查脉冲是否完成. // ==================== PLSR全局变量声明 ==================== extern PLSR_RouteConfig_t g_plsr_route; // 全局PLSR路径控制结构体 -extern uint8_t g_plsr_ext_event_flag; // 外部事件标志 +extern uint8_t g_plsr_ext_event_flag; // 外部事件标志 +extern uint32_t g_plsr_total_pulse_count; // 全局累加脉冲计数器(程序运行期间持续累加，不清零) /* USER CODE END Prototypes */ #ifdef __cplusplus diff --git a/PLSR/PLSR/Core/Src/main.c b/PLSR/PLSR/Core/Src/main.c index d6a1bb7..8e3a024 100644 --- a/PLSR/PLSR/Core/Src/main.c +++ b/PLSR/PLSR/Core/Src/main.c @@ -103,7 +103,6 @@ int main(void) MX_DMA_Init(); /* 初始化备份SRAM和DMA */ BackupSRAM_Init(); - /* USER CODE BEGIN 2 */ /* 初始化uC/OS-II */ OSInit(); @@ -191,16 +190,12 @@ static void StartupTask(void *p_arg) /* 初始化SysTick */ OS_CPU_SysTickInitFreq(SystemCoreClock); - - PLSR_PWM_Init(); - PLSR_Route_Init(&g_plsr_route); - - - + /* 启用统计任务 */ #if OS_TASK_STAT_EN > 0u OSStatInit(); #endif + /* 创建启动任务 */ err = OSTaskCreateExt(MODBUSTask, (void *)0, @@ -233,7 +228,6 @@ static void StartupTask(void *p_arg) static void MODBUSTask(void *p_arg) { (void)p_arg; - uint8_t data = 0; while (1) { Modbus_Process(); @@ -246,6 +240,9 @@ static void KeyTask(void *p_arg) { (void)p_arg; uint8_t startflag = 0; + OSTimeDly(2000); //<等待硬件完全初始化. + PLSR_PWM_Init(); + PLSR_Route_Init(&g_plsr_route); while (1) { if(ModbusSlave.holding_regs[0x2000] == 1) //按下发送脉冲按钮后,向0x3000地址写1,松手写2,设置地址偏移为0x1000,所以这里值为0x2000 @@ -260,10 +257,8 @@ static void KeyTask(void *p_arg) if(startflag == 1) { PLSR_Route_Start(&g_plsr_route); - PLSR_Section_Process(&g_plsr_route); + //PLSR_Section_Process(&g_plsr_route); } - - OSTimeDlyHMSM(0, 0, 0, 10); /* 延时10ms */ } } diff --git a/PLSR/PLSR/Core/Src/tim.c b/PLSR/PLSR/Core/Src/tim.c index 2d12aeb..f7f86a5 100644 --- a/PLSR/PLSR/Core/Src/tim.c +++ b/PLSR/PLSR/Core/Src/tim.c @@ -26,6 +26,7 @@ PLSR_RouteConfig_t g_plsr_route; // 全局PLSR路径控制结构体 // g_plsr_system_tick已删除 - 不再使用UCOSII时间基准 uint8_t g_plsr_ext_event_flag = 0; // 外部事件标志 +uint32_t g_plsr_total_pulse_count = 0; // 全局累加脉冲计数器(程序运行期间持续累加，不清零) // ==================== PLSR内部变量 ==================== static uint32_t s_tim6_update_freq_us = 1000; // TIM6更新频率(微秒) @@ -171,24 +172,6 @@ uint32_t PLSR_GetWaitTick(void) return s_wait_time_counter; } -/** - * @brief 检查任务通知标志 - * @retval 1: 有通知, 0: 无通知 - * - * 该函数用于UCOSII任务中检查是否需要进行段处理。 - * 调用后会自动清除通知标志。 - */ -uint8_t PLSR_CheckTaskNotification(void) -{ - if(s_task_notification_flag) - { - s_task_notification_flag = 0; - return 1; - } - return 0; -} - - // 辅助函数声明已在文件开头声明 /* USER CODE END 1 */ @@ -224,7 +207,7 @@ void MX_TIM2_Init(void) } // 配置外部时钟源 - ETR模式 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_ETRMODE2; // 外部时钟模式2 - sClockSourceConfig.ClockPolarity = TIM_CLOCKPOLARITY_NONINVERTED; // 上升沿触发 + sClockSourceConfig.ClockPolarity = TIM_CLOCKPOLARITY_INVERTED; // 下降沿触发 sClockSourceConfig.ClockPrescaler = TIM_CLOCKPRESCALER_DIV1; // 不分频 sClockSourceConfig.ClockFilter = 0; // 无滤波 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) @@ -469,7 +452,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* TIM2 interrupt Init */ - HAL_NVIC_SetPriority(TIM2_IRQn, 4, 0); + HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); HAL_NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspInit 1 */ @@ -484,7 +467,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) __HAL_RCC_TIM6_CLK_ENABLE(); // 配置TIM6中断 - HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); // 设置中断优先级为最高(0,0) + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); // 设置中断优先级为最高(0,0) HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); // 使能TIM6中断 /* USER CODE BEGIN TIM6_MspInit 1 */ @@ -765,8 +748,6 @@ void PLSR_PWM_Stop(void) { // 停止PWM输出 HAL_TIM_PWM_Stop(&htim10, TIM_CHANNEL_1); - // 停止TIM2计数器 - HAL_TIM_Base_Stop(&htim2); // TIM2恢复用于脉冲计数 } @@ -780,7 +761,8 @@ void PLSR_PWM_Stop(void) */ static void PLSR_CalculateTimerParams(uint32_t frequency, uint16_t* prescaler, uint32_t* period) { - // STM32F4系列定时器时钟频率（通常为84MHz，具体取决于系统配置） + // STM32F4系列定时器时钟频率（APB1定时器通常为84MHz，APB2定时器为168MHz） + // 这里使用168MHz，适用于APB2上的高速定时器（如TIM1、TIM8等） uint32_t timer_clock = 168000000; // 定时器频率计算原理： @@ -789,34 +771,79 @@ static void PLSR_CalculateTimerParams(uint32_t frequency, uint16_t* prescaler, u // 频率为0时的异常处理 if (frequency == 0) { - *prescaler = 0; - *period = 0; + *prescaler = 65535; // 最大预分频器 + *period = 65535; // 最大周期，输出最低频率 + return; + } + + // 频率过高时的处理（超过定时器时钟频率） + if (frequency > timer_clock) { + *prescaler = 0; // 最小预分频器 + *period = 0; // 最小周期，输出最高频率 return; } // 计算总的计数值：定时器时钟频率除以目标频率 - uint32_t total_count = timer_clock / frequency; + uint64_t total_count = (uint64_t)timer_clock / frequency; + + // 如果总计数值超出范围，直接设置为最低频率 + if (total_count > (uint64_t)65536 * 65536) { + *prescaler = 65535; + *period = 65535; + return; + } - // 遍历所有可能的预分频器值，寻找合适的组合 - // 预分频器范围：1-65536（寄存器值0-65535） - for (uint16_t psc = 1; psc <= 65535; psc++) { - // 计算对应的自动重装载值 - uint32_t arr = total_count / psc; + // 优化搜索策略：寻找最佳的预分频器和自动重装载值组合 + // 目标：找到误差最小且分辨率最高的组合 + uint32_t best_prescaler = 65535; + uint32_t best_period = 65535; + uint32_t min_error = UINT32_MAX; + + // 计算合理的搜索范围，避免无效遍历 + uint32_t max_psc = (total_count > 65535) ? 65535 : (uint32_t)total_count; + uint32_t min_psc = (total_count + 65535) / 65536; // 确保ARR不超过65535 + if (min_psc == 0) min_psc = 1; + + // 遍历预分频器值，寻找最佳组合 + for (uint32_t psc = min_psc; psc <= max_psc; psc++) { + // 计算对应的自动重装载值（四舍五入） + uint32_t arr = (uint32_t)((total_count + psc/2) / psc); - // 检查自动重装载值是否在有效范围内（1-65536，寄存器值0-65535） - if (arr <= 65535 && arr >= 1) { - // 找到合适的组合，转换为寄存器值（实际值减1） - *prescaler = psc - 1; // 预分频器寄存器值 = 实际预分频值 - 1 - *period = arr - 1; // 自动重装载寄存器值 = 实际重装载值 - 1 - return; + // 检查自动重装载值是否在有效范围内 + if (arr >= 1 && arr <= 65536) { + // 计算实际输出频率和误差 + uint32_t actual_total = psc * arr; + uint32_t actual_freq = timer_clock / actual_total; + uint32_t error = (actual_freq > frequency) ? + (actual_freq - frequency) : (frequency - actual_freq); + + // 选择误差最小的组合，误差相同时选择分辨率更高的（ARR更大） + if (error < min_error || (error == min_error && arr > best_period + 1)) { + min_error = error; + best_prescaler = psc - 1; // 转换为寄存器值 + best_period = arr - 1; // 转换为寄存器值 + + // 如果找到精确匹配，直接返回 + if (error == 0) { + *prescaler = best_prescaler; + *period = best_period; + return; + } + } } } - // 如果找不到合适的值组合，使用默认的1kHz配置 - // 预分频器 = 83 (实际分频84)，自动重装载 = 999 (实际计数1000) - // 输出频率 = 84MHz / (84 * 1000) = 1kHz - *prescaler = 83; // 84MHz / 84 = 1MHz - *period = 999; // 1MHz / 1000 = 1kHz + // 返回找到的最佳组合 + *prescaler = best_prescaler; + *period = best_period; + + // 如果没有找到合理的组合，使用默认的1kHz配置 + if (min_error == UINT32_MAX) { + // 预分频器 = 167 (实际分频168)，自动重装载 = 999 (实际计数1000) + // 输出频率 = 168MHz / (168 * 1000) = 1kHz + *prescaler = 167; // 168MHz / 168 = 1MHz + *period = 999; // 1MHz / 1000 = 1kHz + } } @@ -918,19 +945,362 @@ void PLSR_TIM6_Stop(void) } static uint32_t AllPluse = 0; //总脉冲个数 +static uint32_t s_last_total_pulse = 0; //上次记录的总脉冲数，用于实时累加 + +/** + * @brief 更新Modbus寄存器中的脉冲计数 + * @param pulse_count: 全局累加脉冲计数值 + * @retval None + * @note 将32位全局累加脉冲计数分解为两个16位寄存器供上位机读取 + */ +static void PLSR_UpdateModbusPulseCount(uint32_t pulse_count) +{ + // 将32位全局累加脉冲计数分解为两个16位寄存器 + ModbusSlave.holding_regs[0x1000] = pulse_count & 0xFFFF; // 低16位 + ModbusSlave.holding_regs[0x1001] = (pulse_count >> 16) & 0xFFFF; // 高16位 +} +// /** +// * @brief 计算加减速匀速各自可发的脉冲数 +// * @param route: 路径控制结构体指针 +// * @retval None +// * @note 根据当前段的目标脉冲数，计算加速、匀速、减速各阶段的脉冲分配 +// * 优先保证能减速到0，然后考虑加速过程，最后分配匀速脉冲 +// */ +// void Calculate_PluseNum(PLSR_RouteConfig_t *route) +// { +// uint32_t accel_pulse_num = 0; // 加速过程脉冲数 +// uint32_t decel_pulse_num = 0; // 减速过程脉冲数 +// uint32_t total_pulse_num = 0; // 加减速总脉冲数 +// uint32_t const_pulse_num = 0; // 匀速过程脉冲数 +// float accel_time = 0; // 加速时间(ms) +// float decel_time = 0; // 减速时间(ms) + +// // 参数有效性检查 +// if (route == NULL || route->current_section_num == 0) return; + +// // 获取当前段配置（段号从1开始，数组索引从0开始） +// PLSR_SectionConfig_t* current_section = &route->section[route->current_section_num - 1]; + +// // 只处理线性加减速算法 +// if (route->accel_config.accel_algorithm == PLSR_ACCEL_LINEAR) +// { +// // 检查加减速率是否有效，避免除零错误 +// if (route->accel_rate == 0 || route->decel_rate == 0) +// { +// // 如果加减速率无效，直接设置为匀速或停止 +// if (route->current_freq > 0) +// { +// route->run_state = PLSR_STATE_CONST; +// } +// else +// { +// route->run_state = PLSR_STATE_IDLE; +// } +// return; +// } + +// // 计算理想情况下的加减速时间和脉冲数 +// if (current_section->target_freq > route->current_freq) +// { +// // 需要加速：从当前频率加速到目标频率 +// accel_time = (float)(current_section->target_freq - route->current_freq) / route->accel_rate; // ms +// // 加速过程脉冲数 = 平均速度 × 时间 = (v0 + v1)/2 × t +// accel_pulse_num = (uint32_t)((route->current_freq + current_section->target_freq) * accel_time / 2000.0f); +// } + +// // 计算从目标频率减速到0的时间和脉冲数 +// decel_time = (float)current_section->target_freq / route->decel_rate; // ms +// // 减速过程脉冲数 = 平均速度 × 时间 = (v1 + 0)/2 × t +// decel_pulse_num = (uint32_t)(current_section->target_freq * decel_time / 2000.0f); + +// // 理想情况下加减速需要的总脉冲数 +// total_pulse_num = accel_pulse_num + decel_pulse_num; + +// // 判断实际脉冲数是否满足理想的加减速过程 +// if (current_section->target_pulse < total_pulse_num) +// { +// // 脉冲数不足，需要重新分配 + +// if (route->current_freq != 0) +// { +// // 起始频率不为0的情况 +// // 首先计算从当前频率减速到0所需的最少脉冲数 +// float min_decel_time = (float)route->current_freq / route->decel_rate; // ms +// uint32_t min_decel_pulse = (uint32_t)(route->current_freq * min_decel_time / 2000.0f); + +// if (current_section->target_pulse <= min_decel_pulse) +// { +// // 脉冲数只够减速，直接进入减速模式 +// route->run_state = PLSR_STATE_DECEL; +// accel_pulse_num = 0; +// decel_pulse_num = current_section->target_pulse; +// const_pulse_num = 0; +// } +// else +// { +// // 脉冲数够减速，剩余脉冲按加减速时间比例分配 +// uint32_t remaining_pulse = current_section->target_pulse - min_decel_pulse; + +// accel_pulse_num = remaining_pulse * route->decel_rate +// / (route->accel_rate + route->decel_rate); +// decel_pulse_num = min_decel_pulse + (remaining_pulse * route->accel_rate +// / (route->accel_rate + route->decel_rate)); +// const_pulse_num = 0; +// } +// } +// else +// { +// accel_pulse_num = current_section->target_pulse * route->decel_rate +// / (route->accel_rate + route->decel_rate); +// decel_pulse_num = current_section->target_pulse * route->accel_rate +// / (route->accel_rate + route->decel_rate); +// const_pulse_num = 0; +// } +// } else +// { +// // 脉冲数充足，有匀速过程 +// const_pulse_num = current_section->target_pulse - total_pulse_num; + +// // 设置初始运行状态 +// if (current_section->target_freq > route->current_freq) +// { +// route->run_state = PLSR_STATE_ACCEL; // 需要先加速 +// } +// else if (current_section->target_freq < route->current_freq) +// { +// route->run_state = PLSR_STATE_DECEL; // 需要先减速 +// } else +// { +// route->run_state = PLSR_STATE_CONST; // 直接匀速 +// } +// } +// route->accel_pulse_count = accel_pulse_num; +// route->const_pulse_count = const_pulse_num; +// route->decel_pulse_count = decel_pulse_num; +// } +// } + +void Calculate_PluseNum(PLSR_RouteConfig_t *route) +{ + uint32_t accel_pulse_num = 0; // 加速过程脉冲数 + uint32_t decel_pulse_num = 0; // 减速过程脉冲数 + uint32_t total_pulse_num = 0; // 加减速总脉冲数 + uint32_t const_pulse_num = 0; // 匀速过程脉冲数 + float accel_time = 0; // 加速时间(ms) + float decel_time = 0; // 减速时间(ms) + float actual_target_freq = 0; // 实际能达到的目标频率 + + // 参数有效性检查 + if (route == NULL || route->current_section_num == 0) return; + + // 获取当前段配置（段号从1开始，数组索引从0开始） + PLSR_SectionConfig_t* current_section = &route->section[route->current_section_num - 1]; + + // 只处理线性加减速算法 + if (route->accel_config.accel_algorithm == PLSR_ACCEL_LINEAR) + { + // 检查加减速率是否有效，避免除零错误 + if (route->accel_rate == 0 || route->decel_rate == 0) + { + if (route->current_freq > 0) + { + route->run_state = PLSR_STATE_CONST; + } + else + { + route->run_state = PLSR_STATE_IDLE; + } + return; + } + + float v0 = route->current_freq; // 起始频率 + float vt = current_section->target_freq; // 期望目标频率 + float a = route->accel_rate; // 加速度 + float d = route->decel_rate; // 减速度 + uint32_t total_pulses = current_section->target_pulse; // 总脉冲数 + + // 情况1：检查是否只需要减速 + if (vt <= v0) + { + // 只需要减速或保持当前速度 + if (vt == v0) + { + // 保持当前速度 + route->run_state = PLSR_STATE_CONST; + accel_pulse_num = 0; + const_pulse_num = total_pulses; + decel_pulse_num = 0; + } + else + { + // 需要减速 + route->run_state = PLSR_STATE_DECEL; + decel_time = (v0 - vt) / d; // ms + decel_pulse_num = (uint32_t)((v0 + vt) * decel_time / 2000.0f); + + if (decel_pulse_num <= total_pulses) + { + // 脉冲数足够，剩余为匀速 + accel_pulse_num = 0; + const_pulse_num = total_pulses - decel_pulse_num; + actual_target_freq = vt; + } + else + { + // 脉冲数不够，重新计算实际能减速到的频率 + // 解方程：total_pulses = (v0 + vf) * t / 2000，其中 t = (v0 - vf) / d + // 化简得：total_pulses * 2000 * d = (v0 + vf) * (v0 - vf) = v0^2 - vf^2 + // 所以：vf^2 = v0^2 - total_pulses * 2000 * d + float vf_squared = v0 * v0 - total_pulses * 2000.0f * d; + if (vf_squared >= 0) + { + actual_target_freq = sqrt(vf_squared); + decel_time = (v0 - actual_target_freq) / d; + accel_pulse_num = 0; + const_pulse_num = 0; + decel_pulse_num = total_pulses; + } + else + { + // 数学上不可行，设为停止 + actual_target_freq = 0; + decel_time = v0 / d; + accel_pulse_num = 0; + const_pulse_num = 0; + decel_pulse_num = total_pulses; + } + } + } + } + else + { + // 需要加速：从v0加速到vt，然后减速到0 + // 先检查理想情况下是否可行 + accel_time = (vt - v0) / a; // ms + decel_time = vt / d; // ms + + accel_pulse_num = (uint32_t)((v0 + vt) * accel_time / 2000.0f); + decel_pulse_num = (uint32_t)(vt * decel_time / 2000.0f); + total_pulse_num = accel_pulse_num + decel_pulse_num; + + if (total_pulse_num <= total_pulses) + { + // 脉冲数充足，有匀速过程 + const_pulse_num = total_pulses - total_pulse_num; + actual_target_freq = vt; + route->run_state = PLSR_STATE_ACCEL; + } + else + { + // 脉冲数不足，需要求解实际能达到的最大频率 + // 设实际最大频率为vm + // 约束条件：加速脉冲数 + 减速脉冲数 = 总脉冲数 + // 加速脉冲数 = (v0 + vm) * (vm - v0) / (2000 * a) + // 减速脉冲数 = vm^2 / (2000 * d) + // + // 联立方程：(v0 + vm) * (vm - v0) / (2000 * a) + vm^2 / (2000 * d) = total_pulses + // 化简：(vm^2 - v0^2) / (2000 * a) + vm^2 / (2000 * d) = total_pulses + // 整理：vm^2 * (1/(2000*a) + 1/(2000*d)) - v0^2/(2000*a) = total_pulses + // 即：vm^2 * (a + d)/(2000*a*d) = total_pulses + v0^2/(2000*a) + + float coefficient = (a + d) / (2000.0f * a * d); + float constant = total_pulses + (v0 * v0) / (2000.0f * a); + float vm_squared = constant / coefficient; + + if (vm_squared > 0) + { + actual_target_freq = sqrt(vm_squared); + + // 确保不超过期望目标频率 + if (actual_target_freq > vt) + { + actual_target_freq = vt; + } + + // 重新计算各阶段时间和脉冲数 + if (actual_target_freq > v0) + { + accel_time = (actual_target_freq - v0) / a; + decel_time = actual_target_freq / d; + + accel_pulse_num = (uint32_t)((v0 + actual_target_freq) * accel_time / 2000.0f); + decel_pulse_num = (uint32_t)(actual_target_freq * decel_time / 2000.0f); + + // 由于浮点计算误差，调整脉冲数确保总和正确 + uint32_t calculated_total = accel_pulse_num + decel_pulse_num; + if (calculated_total < total_pulses) + { + // 余数分配给加速阶段 + accel_pulse_num += (total_pulses - calculated_total); + } + else if (calculated_total > total_pulses) + { + // 从减速阶段减去多余的脉冲 + uint32_t excess = calculated_total - total_pulses; + if (decel_pulse_num > excess) + { + decel_pulse_num -= excess; + } + else + { + decel_pulse_num = 0; + accel_pulse_num = total_pulses; + } + } + + const_pulse_num = 0; + route->run_state = PLSR_STATE_ACCEL; + } + else + { + // 实际频率不高于起始频率，直接设为匀速 + actual_target_freq = v0; + accel_pulse_num = 0; + const_pulse_num = total_pulses; + decel_pulse_num = 0; + route->run_state = PLSR_STATE_CONST; + } + } + else + { + // 数学上不可行，保持当前频率 + actual_target_freq = v0; + accel_pulse_num = 0; + const_pulse_num = total_pulses; + decel_pulse_num = 0; + route->run_state = PLSR_STATE_CONST; + } + } + } + + // 保存计算结果 + route->accel_pulse_count = accel_pulse_num; + route->const_pulse_count = const_pulse_num; + route->decel_pulse_count = decel_pulse_num; + + // 如果需要，可以将实际目标频率保存到某个字段 + // route->actual_target_freq = actual_target_freq; + } +} + + void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { // TIM2中断：负责段切换逻辑 if(htim->Instance == TIM2) { - // 累加总脉冲数 - AllPluse += __HAL_TIM_GetAutoreload(&htim2); + // 精确累加当前段已发送的脉冲数 + uint32_t current_section_pulses = __HAL_TIM_GetAutoreload(&htim2); + AllPluse += current_section_pulses; g_plsr_route.pulse_count = AllPluse; - // 检查当前段是否完成 - if (PLSR_Section_CheckPulseComplete(&g_plsr_route)) - { + // 立即停止PWM输出，防止多发脉冲 + PLSR_PWM_Stop(); + + // 更新Modbus寄存器（TIM6中断会实时累加全局计数器） + PLSR_UpdateModbusPulseCount(g_plsr_total_pulse_count); + // 当前段脉冲发送完毕，进入等待状态 g_plsr_route.run_state = PLSR_STATE_WAIT; @@ -940,15 +1310,17 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) // 等待条件满足，切换到下一段 PLSR_SectionConfig_t* current_section = &g_plsr_route.section[g_plsr_route.current_section_num - 1]; - if (current_section->next_section == 0 && g_plsr_route.current_section_num == g_plsr_route.section_num) //< 当前段是最后一段且跳转段为0，路径结束 + if (current_section->next_section == 0 || g_plsr_route.current_section_num >= g_plsr_route.section_num) { + // 当前段是最后一段或跳转段为0，路径结束 PLSR_Route_Stop(&g_plsr_route); return; } - else if (current_section->next_section > 0 && current_section->next_section <= PLSR_MAX_SECTIONS) + else if (current_section->next_section <= PLSR_MAX_SECTIONS) { // 更新prevPulseCount为当前段的累计脉冲数 - if (g_plsr_route.mode == PLSR_MODE_RELATIVE) { + if (g_plsr_route.mode == PLSR_MODE_RELATIVE) + { g_plsr_route.prevPulseCount = g_plsr_route.pulse_count; } @@ -959,15 +1331,60 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) // 启动新段 PLSR_Section_StartNewSection(&g_plsr_route); - // 设置TIM2的自动重载值为新段的脉冲数 + // 计算新段需要发送的脉冲数 PLSR_SectionConfig_t* new_section = &g_plsr_route.section[g_plsr_route.current_section_num - 1]; uint32_t next_pulse_target; - if (g_plsr_route.mode == PLSR_MODE_RELATIVE) { + if (g_plsr_route.mode == PLSR_MODE_RELATIVE) + { + // 相对模式：每段发送指定的脉冲数 next_pulse_target = new_section->target_pulse; - } else { - next_pulse_target = new_section->target_pulse - g_plsr_route.pulse_count; + } + else + { + // 绝对模式：发送到绝对位置所需的脉冲数 + if (new_section->target_pulse > g_plsr_route.pulse_count) + { + next_pulse_target = new_section->target_pulse - g_plsr_route.pulse_count; + } + else + { + // 目标位置小于等于当前位置，该段不发送脉冲 + next_pulse_target = 0; + } + } + + // 处理脉冲数 + if (next_pulse_target == 0) + { + // 绝对模式下目标位置已达到，直接切换到下一段或结束 + // 检查是否还有下一段 + if (new_section->next_section == 0 || g_plsr_route.current_section_num >= g_plsr_route.section_num) + { + // 没有下一段，路径结束 + PLSR_Route_Stop(&g_plsr_route); + return; + } + else + { + // 该段无需发送脉冲，立即完成并检查下一段 + // 这种情况下直接标记当前段完成，等待下次中断处理 + g_plsr_route.run_state = PLSR_STATE_WAIT; + return; + } + } + else if (next_pulse_target > 0 && next_pulse_target <= 0xFFFFFFFF) + { + __HAL_TIM_SetAutoreload(&htim2, next_pulse_target); + // 重置TIM2计数器后再启动PWM + __HAL_TIM_SET_COUNTER(&htim2, 0); + PLSR_PWM_Start(); + } + else + { + // 脉冲数异常，停止路径 + PLSR_Route_Stop(&g_plsr_route); + return; } - __HAL_TIM_SetAutoreload(&htim2, next_pulse_target); } else { @@ -976,54 +1393,34 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) return; } } - } - - // 重置TIM2计数器 - __HAL_TIM_SET_COUNTER(&htim2, 0); } - // TIM6中断：仅负责加减速过程的频率更新和等待时间计时 + // TIM6中断：负责加减速过程的频率更新、等待时间计时和实时脉冲计数更新 if(htim->Instance == TIM6) { // 等待时间计数器累加 s_wait_time_counter++; - - // 处理加速和减速过程中的频率更新 - if(g_plsr_route.run_state == PLSR_STATE_ACCEL && g_plsr_route.accel_step_count > 0) - { - g_plsr_route.current_freq += g_plsr_route.freq_step; - PLSR_PWM_SetFrequency(g_plsr_route.current_freq); - if(g_plsr_route.current_freq > 0) - { - PLSR_PWM_Start(); - } - - g_plsr_route.accel_step_count--; - - // 加速完成，进入匀速状态 - if(g_plsr_route.accel_step_count == 0) - { - g_plsr_route.run_state = PLSR_STATE_CONST; - } + + uint32_t current_tim2_count = __HAL_TIM_GET_COUNTER(&htim2); + + // 计算当前段已发送的总脉冲数 + uint32_t current_pulse_count = AllPluse + current_tim2_count; + + // 实时累加脉冲增量到全局计数器 + if (current_pulse_count > s_last_total_pulse) { + uint32_t pulse_increment = current_pulse_count - s_last_total_pulse; + g_plsr_total_pulse_count += pulse_increment; + s_last_total_pulse = current_pulse_count; } - else if(g_plsr_route.run_state == PLSR_STATE_DECEL && g_plsr_route.decel_step_count > 0) + // 更新路由结构体的脉冲计数（使用原子操作保证一致性） + g_plsr_route.pulse_count = current_pulse_count; + + // 实时更新Modbus寄存器，供上位机读取（发送全局累加脉冲计数） + PLSR_UpdateModbusPulseCount(g_plsr_total_pulse_count); + // 处理加减速过程中的频率更新（使用新的直线加减速算法） + if(g_plsr_route.run_state == PLSR_STATE_ACCEL || g_plsr_route.run_state == PLSR_STATE_DECEL) { - g_plsr_route.current_freq -= g_plsr_route.freq_step; - PLSR_PWM_SetFrequency(g_plsr_route.current_freq); - - if(g_plsr_route.current_freq <= 0) //频率减为0时一般进入等待,且脉冲也已发完 - { - g_plsr_route.run_state = PLSR_STATE_WAIT; - PLSR_PWM_Stop(); - } - - g_plsr_route.decel_step_count--; - - // 减速完成，进入匀速状态 - if(g_plsr_route.decel_step_count == 0) - { - g_plsr_route.run_state = PLSR_STATE_CONST; - } + PLSR_Accel_Process(&g_plsr_route); } } } @@ -1039,9 +1436,16 @@ void PLSR_Route_Set(PLSR_RouteConfig_t* route) route->mode = ModbusSlave.holding_regs[6]; //绝对/相对 route->section_num = ModbusSlave.holding_regs[7]; //总段数 route->start_section = ModbusSlave.holding_regs[8]; - route->default_freq = ModbusSlave.holding_regs[9]<<16|ModbusSlave.holding_regs[10]; - route->accel_config.accel_time_ms = ModbusSlave.holding_regs[11]; - route->accel_config.decel_time_ms = ModbusSlave.holding_regs[12]; + route->default_freq = ModbusSlave.holding_regs[9]|ModbusSlave.holding_regs[10]<<16; + route->default_accel_time_ms = ModbusSlave.holding_regs[11]; + route->default_decel_time_ms = ModbusSlave.holding_regs[12]; + + // 新增：设置默认加减速时间 + route->default_accel_time_ms = ModbusSlave.holding_regs[11]; // 使用相同的加速时间 + route->default_decel_time_ms = ModbusSlave.holding_regs[12]; // 使用相同的减速时间 + + // 自动更新加减速度 + PLSR_Accel_UpdateRates(route); route->start_freq = 0; // 起始频率：0Hz route->end_freq = 0; // 结束频率：0Hz @@ -1055,7 +1459,7 @@ void PLSR_Route_Set(PLSR_RouteConfig_t* route) route->section[i].target_pulse = (((uint32_t)ModbusSlave.holding_regs[258+(16*i)]) | (uint32_t)ModbusSlave.holding_regs[259+(16*i)]<<16); route->section[i].wait_condition.wait_type = ModbusSlave.holding_regs[260+(16*i)]; route->section[i].next_section = ModbusSlave.holding_regs[261+(16*i)]; - } + } } void PLSR_Route_Init(PLSR_RouteConfig_t* route) @@ -1070,16 +1474,19 @@ void PLSR_Route_Init(PLSR_RouteConfig_t* route) route->direction = PLSR_DIR_FORWARD; // 运行方向：默认正向 + // 初始化新增的加减速参数 + route->default_accel_time_ms = 0; // 默认加速时间：清零 + route->default_decel_time_ms = 0; // 默认减速时间：清零 + route->accel_rate = 0; // 加速度：清零 + route->decel_rate = 0; // 减速度：清零 // 初始化运行状态参数 - 清零所有运行时状态 route->run_state = PLSR_STATE_IDLE; // 运行状态：空闲 - route->accel_step_count = 0; // 加速步数计数：清零 - route->decel_step_count = 0; // 减速步数计数：清零 route->const_pulse_count = 0; // 匀速脉冲计数：清零 route->freq_step = 0; // 频率步进值：清零 route->wait_start_tick = 0; // 等待开始时刻：清零 route->act_start_tick = 0; // ACT开始时刻：清零 - + PLSR_PWM_Stop(); // 停止PWM输出 PLSR_TIM6_Stop(); // 停止TIM6定时器 PLSR_TIM6_SetUpdateFreq(1000); //初始化TIM6更新频率为1000us @@ -1097,7 +1504,7 @@ void PLSR_Route_Start(PLSR_RouteConfig_t* route) // 状态检查 - 避免重复启动 if (route->route_state == PLSR_ROUTE_RUNNING) return; - + // 启动时初始化用户可配置参数 PLSR_Route_Set(route); @@ -1112,12 +1519,38 @@ void PLSR_Route_Start(PLSR_RouteConfig_t* route) // 重置全局脉冲计数器 AllPluse = 0; + // 重置上次记录的总脉冲数，用于实时累加计算 + s_last_total_pulse = g_plsr_route.pulse_count; + // 启动第一段 PLSR_Section_StartNewSection(route); - // 设置TIM2的自动重载值为第一段的脉冲数 + // 计算第一段需要发送的脉冲数 PLSR_SectionConfig_t* first_section = &route->section[route->current_section_num - 1]; - __HAL_TIM_SetAutoreload(&htim2, first_section->target_pulse); + uint32_t first_pulse_target; + if (route->mode == PLSR_MODE_RELATIVE) + { + // 相对模式：每段发送指定的脉冲数 + first_pulse_target = first_section->target_pulse; + } + else + { + // 绝对模式：发送到绝对位置所需的脉冲数 + // 第一段从0位置开始，所以脉冲数就是目标位置 + first_pulse_target = first_section->target_pulse; + } + + // 确保脉冲数有效 + if (first_pulse_target > 0 && first_pulse_target <= 0xFFFF) + { + __HAL_TIM_SetAutoreload(&htim2, first_pulse_target); + } + else + { + // 脉冲数无效，设置为1避免除零错误 + __HAL_TIM_SetAutoreload(&htim2, 1); + } + // 重置TIM2计数器 __HAL_TIM_SET_COUNTER(&htim2, 0); @@ -1152,15 +1585,13 @@ void PLSR_Route_Stop(PLSR_RouteConfig_t* route) route->run_state = PLSR_STATE_IDLE; route->current_freq = 0; - // 重置计数器和脉冲数 + // 重置计数器 __HAL_TIM_SET_COUNTER(&htim2, 0); - AllPluse = 0; - route->pulse_count = 0; + // 注意：不重置AllPluse，保持累计脉冲数 + // AllPluse = 0; // 注释掉，避免重复加速问题 + //route->pulse_count = 0; route->prevPulseCount = 0; - // 重置加减速参数 - route->accel_step_count = 0; - route->decel_step_count = 0; route->freq_step = 0; } @@ -1220,25 +1651,17 @@ void PLSR_Section_StartNewSection(PLSR_RouteConfig_t* route) { // 目标频率大于当前频率：需要加速到目标频率 route->run_state = PLSR_STATE_ACCEL; - // 计算加速过程的步数和参数（参数1表示加速过程） - PLSR_Accel_CalculateSteps(route, route->accel_config.accel_time_ms, 1); } else if (route->target_freq < route->current_freq) { // 目标频率小于当前频率：需要减速到目标频率 route->run_state = PLSR_STATE_DECEL; - // 计算减速过程的步数和参数（参数0表示减速过程） - PLSR_Accel_CalculateSteps(route, route->accel_config.decel_time_ms, 0); } else { // 目标频率等于当前频率：无需加减速，直接进入匀速状态 route->run_state = PLSR_STATE_CONST; } - - // 计算匀速段可以发送的脉冲数（扣除加减速段的脉冲数） - PLSR_Section_CalculateConstPulse(route); - //为等待时间计数赋值 PLSR_Wait_StartTimer(route); } @@ -1335,64 +1758,9 @@ float PLSR_Accel_CalculateSine(float progress) * @retval None * @note 根据时间和频率差计算加减速所需的步数 */ -static void PLSR_Accel_CalculateSteps(PLSR_RouteConfig_t* route, uint32_t time_ms, uint8_t is_accel) -{ - // 参数有效性检查：路径指针不能为空，时间不能为0 - if (route == NULL || time_ms == 0) return; - - // 计算频率差值，根据加速或减速模式确定计算方式 - uint32_t freq_diff; - if (is_accel) - { - // 加速模式：计算目标频率与当前频率的差值（目标频率应大于当前频率） - freq_diff = (route->target_freq > route->current_freq) ? - (route->target_freq - route->current_freq) : 0; - } - else - { - // 减速模式：计算当前频率与目标频率的差值（当前频率应大于目标频率） - freq_diff = (route->current_freq > route->target_freq) ? - (route->current_freq - route->target_freq) : 0; - } - - // 如果频率差为0，说明无需加减速，清零相关参数并返回 - if (freq_diff == 0) - { - route->accel_step_count = 0; - route->decel_step_count = 0; - route->freq_step = 0; - return; - } - - - // TIM6更新周期从微秒转换为毫秒：s_tim6_update_freq_us / 1000 - uint32_t total_steps = time_ms / (s_tim6_update_freq_us / 1000); //< 根据指定加减速时间和TIM6更新周期计算总步数 - // 确保至少有1步，避免除零错误 - if (total_steps == 0) total_steps = 1; - - // 计算每步的频率变化量：频率差值除以总步数 - route->freq_step = freq_diff / total_steps; - // 确保每步至少变化1Hz，避免频率变化过小导致无效果 - if (route->freq_step == 0) route->freq_step = 1; - - // 根据实际的每步频率变化量，重新计算精确的总步数 - // 这样可以确保最终频率能够准确达到目标值 - total_steps = freq_diff / route->freq_step; - - // 根据加速或减速模式，设置对应的步数计数器 - if (is_accel) - { - // 加速模式：设置加速步数，清零减速步数 - route->accel_step_count = total_steps; - route->decel_step_count = 0; - } - else - { - // 减速模式：设置减速步数，清零加速步数 - route->accel_step_count = 0; - route->decel_step_count = total_steps; - } -} +// 注意：PLSR_Accel_CalculateSteps函数已被删除 +// 新的直线加减速算法不再需要复杂的步数计算 +// 改为使用PLSR_Accel_Process函数在TIM6中断中直接处理加减速 /** * @brief 加减速处理函数 @@ -1405,20 +1773,91 @@ void PLSR_Accel_Process(PLSR_RouteConfig_t* route) // 参数有效性检查 if (route == NULL) return; - + // TIM6更新周期(ms) + uint32_t tim6_period_ms = s_tim6_update_freq_us / 1000; + if (tim6_period_ms == 0) tim6_period_ms = 1; // 避免除零错误 + uint8_t first_flag = (route->current_freq == 0); + if ((route->run_state == PLSR_STATE_ACCEL && route->current_freq >= route->target_freq) || + (route->run_state == PLSR_STATE_DECEL && route->current_freq <= route->target_freq)) + { + route->run_state = PLSR_STATE_CONST; + return; + } // ==================== 加速处理 ==================== if (route->run_state == PLSR_STATE_ACCEL) { - + // 计算频率增量 = 加速度 * 时间间隔 + uint32_t freq_increment = route->accel_rate * tim6_period_ms; + + // 更新当前频率 + route->current_freq += freq_increment; + + // 检查是否达到目标频率 + if (route->current_freq >= route->target_freq) { + route->current_freq = route->target_freq; // 限制到目标频率 + route->run_state = PLSR_STATE_CONST; // 切换到匀速状态 + } + // 更新PWM频率 + PLSR_PWM_SetFrequency(route->current_freq); + if(first_flag == 1 && route->current_freq != 0) + { + first_flag = 0; + PLSR_PWM_Start(); + } + } // ==================== 减速处理 ==================== else if (route->run_state == PLSR_STATE_DECEL) { - + // 计算频率减量 = 减速度 * 时间间隔 + uint32_t freq_decrement = route->decel_rate * tim6_period_ms; + + // 更新当前频率 + if (route->current_freq > freq_decrement) { + route->current_freq -= freq_decrement; + } + else + { + route->current_freq = 0; // 防止频率变为负数 + } + + // 检查是否达到目标频率 + if (route->current_freq <= route->target_freq) { + route->current_freq = route->target_freq; // 限制到目标频率 + route->run_state = PLSR_STATE_CONST; // 切换到匀速状态 + } + + // 更新PWM频率 + PLSR_PWM_SetFrequency(route->current_freq); } } +/** + * @brief 更新加减速度 + * @param route: 路径控制结构体指针 + * @retval None + * @note 根据默认频率和加减速时间重新计算加减速度 + */ +void PLSR_Accel_UpdateRates(PLSR_RouteConfig_t* route) +{ + if (route == NULL) return; + + // 计算加速度 (Hz/ms) + if (route->default_accel_time_ms > 0) { + route->accel_rate = route->default_freq / route->default_accel_time_ms; + } else { + route->accel_rate = 0; // 避免除零错误 + } + + // 计算减速度 (Hz/ms) + if (route->default_decel_time_ms > 0) { + route->decel_rate = route->default_freq / route->default_decel_time_ms; + } else { + route->decel_rate = 0; // 避免除零错误 + } +} + /** * @brief 匀速状态处理 @@ -1503,7 +1942,7 @@ uint8_t PLSR_Section_CheckWaitCondition(PLSR_RouteConfig_t* route) // 根据等待条件类型进行相应的检查 switch (wait_cond->wait_type) { case PLSR_WAIT_PLUSEEND: - return PLSR_Section_CheckPulseComplete(route); + return 1; case PLSR_WAIT_TIME: // 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CMSIS-Pack @@ -1094,7 +1114,7 @@ Main - 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34050 @@ -1173,7 +1193,7 @@ Trace - 00200000010000000200FFFF01001100434D4643546F6F6C426172427574746F6E539200000000040089000000FFFEFF03450054004D0000000000000000000000000001000000010000000180549200000000000025000000FFFEFF03530057004F00000000000000000000000000010000000100000000000000FFFEFF05540072006100630065002F000000 + 00200000010000000200FFFF01001100434D4643546F6F6C426172427574746F6E53920000000004008A000000FFFEFF03450054004D0000000000000000000000000001000000010000000180549200000000000025000000FFFEFF03530057004F00000000000000000000000000010000000100000000000000FFFEFF05540072006100630065002F000000 34110 diff --git a/PLSR/PLSR/EWARM/settings/test.1.dnx b/PLSR/PLSR/EWARM/settings/test.1.dnx index 3f8abc0..2022675 100644 --- a/PLSR/PLSR/EWARM/settings/test.1.dnx +++ b/PLSR/PLSR/EWARM/settings/test.1.dnx @@ -14,13 +14,13 @@ 46232557 - _ 0 - _ 0 0 2 + _ 0 + _ 0 - 3949072944 + 1822529156 _ 0 @@ -75,22 +75,6 @@ 0 $PROJ_DIR$\ITM.log - - _ 0 - _ "" - - - _ 0 - _ "" - _ 0 - - - 0 - - - 0 - 0 - 0 0 @@ -136,9 +120,15 @@ 1 0 - - 0 - + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + 0 3 @@ -152,4 +142,14 @@ 1 + + 0 + + + 0 + + + 0 + 0 + diff --git a/PLSR/PLSR/EWARM/test.1.dep b/PLSR/PLSR/EWARM/test.1.dep index 02f2d83..c446d53 100644 --- a/PLSR/PLSR/EWARM/test.1.dep +++ b/PLSR/PLSR/EWARM/test.1.dep @@ -5,274 +5,402 @@ test.1 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - $PROJ_DIR$\..\Core\Src\modbus_crc.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - $PROJ_DIR$\..\Core\Src\stm32f4xx_it.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - $PROJ_DIR$\..\Core\Src\stm32f4xx_hal_msp.c - $PROJ_DIR$\..\Core\Src\tim.c - $PROJ_DIR$\..\Core\Src\modbus_log.c - $PROJ_DIR$\..\Core\Src\gpio.c - $PROJ_DIR$\..\Core\Src\stm32f4xx_hal_timebase_tim.c - $PROJ_DIR$\..\Core\Src\flash_save.c - $PROJ_DIR$\..\Core\Src\usart.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - $PROJ_DIR$\..\Core\Src\system_stm32f4xx.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - $PROJ_DIR$\..\Core\Src\dma.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - $PROJ_DIR$\startup_stm32f407xx.s - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c - $PROJ_DIR$\..\Core\Src\main.c - $PROJ_DIR$\..\UCOS\Source\os_tmr.c - $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_dma.o - 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$PROJ_DIR$\test.1\Obj\stm32f4xx_ll_dma.__cstat.et - $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_rcc.o + $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_dma_ex.__cstat.et $PROJ_DIR$\test.1\Obj\ucos_ii.o - $PROJ_DIR$\test.1\Obj\app_hooks.__cstat.et - $PROJ_DIR$\..\Core\Inc\stm32f4xx_hal_conf.h - $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_rng.__cstat.et - $PROJ_DIR$\test.1\List\test.1.map - $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_dac.o - $PROJ_DIR$\..\UCOS\Source\os_mutex.c - $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_gpio.__cstat.et + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h + $PROJ_DIR$\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h + $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_spi.xcl + $PROJ_DIR$\test.1\Obj\gpio.o + $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_usart.o $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_rcc_ex.__cstat.et - $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_tim.o + $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_msp.__cstat.et + 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$PROJ_DIR$\test.1\Exe\test.1.hex - $PROJ_DIR$\..\UCOS\Ports\os_cpu.h - $PROJ_DIR$\..\UCOS\Source\ucos_ii.h - $PROJ_DIR$\test.1\Obj\modbus_crc.__cstat.et - $PROJ_DIR$\..\Core\Inc\tim.h - $TOOLKIT_DIR$\lib\m7M_tls.a - $TOOLKIT_DIR$\inc\c\stdlib.h - $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_rcc_ex.o - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h - $PROJ_DIR$\test.1\Obj\stm32f4xx_hal_crc.o + $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_gpio.xcl + $PROJ_DIR$\test.1\Obj\stm32f4xx_ll_spi.o + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $PROJ_DIR$\test.1\Obj\test.1.pbd - [ROOT_NODE] + $PROJ_DIR$\startup_stm32f407xx.s - ILINK - 65 72 + AARM + 20 + + + + + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + + + BICOMP + 64 + + + ICCARM + 43 + + + __cstat + 181 + + + + + ICCARM + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 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+ $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + + BICOMP + 27 + ICCARM - 190 + 21 __cstat @@ -282,677 +410,799 @@ ICCARM - 81 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 216 70 211 141 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c + $PROJ_DIR$\..\Core\Src\dma.c + + BICOMP + 112 + ICCARM - 197 + 201 __cstat - 129 + 40 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 248 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c + + BICOMP + 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189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 110 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 36 23 270 120 278 72 282 242 114 3 266 119 211 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + + BICOMP + 159 + ICCARM - 221 + 47 __cstat - 162 + 38 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + + BICOMP + 180 + ICCARM - 60 + 195 __cstat - 96 + 106 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 $PROJ_DIR$\..\Core\Src\stm32f4xx_it.c + + BICOMP + 224 + ICCARM - 49 + 48 __cstat - 100 + 22 ICCARM - 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 78 224 152 204 124 160 223 149 + 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 29 122 105 242 23 59 118 251 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + + BICOMP + 232 + ICCARM - 48 + 28 __cstat - 79 + 8 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 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- $PROJ_DIR$\..\Core\Src\tim.c + $PROJ_DIR$\..\Core\Src\modbus_crc.c + + BICOMP + 66 + ICCARM - 109 + 89 __cstat - 135 + 98 ICCARM - 226 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 167 124 159 99 158 228 154 204 81 208 209 39 123 + 114 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 265 77 255 103 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 $PROJ_DIR$\..\Core\Src\modbus_log.c + + BICOMP + 220 + ICCARM - 153 + 204 __cstat - 53 + 58 ICCARM - 209 167 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 124 159 99 158 228 154 204 81 208 + 266 36 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 23 270 120 278 72 282 242 114 3 $PROJ_DIR$\..\Core\Src\gpio.c + + BICOMP + 61 + ICCARM - 101 + 14 __cstat - 117 + 73 ICCARM - 42 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 53 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Core\Src\stm32f4xx_hal_timebase_tim.c + $PROJ_DIR$\..\Core\Src\usart.c + + BICOMP + 54 + ICCARM - 85 + 78 __cstat - 111 + 192 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 36 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 23 270 120 278 72 282 242 114 3 266 - $PROJ_DIR$\..\Core\Src\flash_save.c + $PROJ_DIR$\..\Core\Src\main.c + + BICOMP + 203 + ICCARM - 210 + 264 __cstat - 113 + 257 ICCARM - 208 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 167 114 124 159 99 158 228 154 204 81 209 + 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 53 122 105 242 23 59 118 251 110 36 270 120 278 72 282 114 3 266 119 211 248 - $PROJ_DIR$\..\Core\Src\usart.c + $PROJ_DIR$\..\Core\Src\stm32f4xx_hal_timebase_tim.c + + BICOMP + 96 + ICCARM - 95 + 235 __cstat - 139 + 100 ICCARM - 167 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 124 159 99 158 228 154 204 81 208 209 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c + + BICOMP + 102 + ICCARM - 232 + 256 __cstat - 168 + 258 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Core\Src\system_stm32f4xx.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c + + BICOMP + 65 + ICCARM - 41 + 213 __cstat - 63 + 69 ICCARM - 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 216 70 211 141 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c + $PROJ_DIR$\..\Core\Src\flash_save.c + + BICOMP + 81 + ICCARM - 195 + 259 __cstat - 50 + 4 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 3 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 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1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + $PROJ_DIR$\..\Core\Src\stm32f4xx_hal_msp.c + + BICOMP + 32 + ICCARM - 94 + 83 __cstat - 75 + 17 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 74 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\startup_stm32f407xx.s + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c - AARM - 206 + BICOMP + 39 - - - - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c - ICCARM - 35 + 2 __cstat - 46 + 92 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c + + BICOMP + 263 + ICCARM - 89 + 184 __cstat - 43 + 197 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Core\Src\main.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c + + BICOMP + 188 + ICCARM - 93 + 179 __cstat - 33 + 111 ICCARM - 114 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 42 224 152 204 124 160 223 149 226 167 159 99 158 228 154 81 208 209 136 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\test.1\Exe\test.1.out + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_crc.c - OBJCOPY - 222 + BICOMP + 34 - ILINK - 72 + ICCARM + 5 + + + __cstat + 218 - ILINK - 47 45 51 210 101 93 190 153 165 84 150 206 156 125 232 197 195 155 217 48 212 94 35 89 115 221 60 67 229 131 77 110 85 164 218 83 49 133 73 29 106 220 103 214 147 107 215 31 62 41 109 68 95 32 146 227 44 + ICCARM + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_rcc.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c - ICCARM - 147 - - - __cstat - 121 + BICOMP + 200 - - - - $PROJ_DIR$\..\UCOS\Ports\os_cpu_c.c - ICCARM - 84 + 15 __cstat - 198 + 223 ICCARM - 224 152 204 124 116 122 87 203 189 34 160 223 149 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c + $PROJ_DIR$\..\UCOS\Source\ucos_ii.c + + BICOMP + 116 + ICCARM - 110 + 9 __cstat - 104 + 63 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 122 105 242 23 168 49 207 239 93 0 59 118 251 44 244 31 90 191 193 238 50 19 198 $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_exti.c + + BICOMP + 26 + ICCARM - 106 + 236 __cstat - 61 + 80 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dac.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_i2c.c + + BICOMP + 85 + ICCARM - 73 + 71 __cstat - 161 + 76 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_rng.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dma.c + + BICOMP + 123 + ICCARM - 107 + 82 __cstat - 71 + 228 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usart.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_gpio.c + + BICOMP + 280 + ICCARM - 62 + 227 __cstat - 144 + 42 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + + BICOMP + 70 + ICCARM - 131 + 254 __cstat - 169 + 189 ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\UCOS\Source\ucos_ii.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c + + BICOMP + 233 + ICCARM - 68 + 99 __cstat - 126 + 274 ICCARM - 224 152 204 124 116 122 87 203 189 34 160 223 149 92 142 64 82 74 196 205 186 148 28 + 265 77 255 103 30 84 121 107 168 49 207 239 93 75 231 97 208 210 12 115 6 0 217 240 33 7 229 222 104 196 261 25 230 10 1 37 11 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_crc.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_pwr.c + + BICOMP + 268 + ICCARM - 133 + 166 __cstat - 134 + 113 $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_spi.c + + BICOMP + 13 + ICCARM - 215 + 281 __cstat - 157 + 262 @@ -961,207 +1211,208 @@ AARM - 165 + 234 - $PROJ_DIR$\..\UCOS\Ports\os_dbg.c + $PROJ_DIR$\test.1\Exe\test.1.out - ICCARM - 150 + OBJCOPY + 221 - __cstat + ILINK 57 - ICCARM - 224 152 204 124 116 122 87 203 189 34 160 223 149 + ILINK + 35 51 201 259 14 264 89 204 234 253 246 20 46 179 5 21 28 2 256 276 213 184 269 43 83 279 41 94 56 47 226 195 235 99 15 254 48 164 243 82 236 227 71 166 18 277 281 199 67 91 95 9 78 86 87 237 108 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_dac.c + + BICOMP + 271 + ICCARM - 83 + 243 __cstat - 213 + 109 - - - ICCARM - 216 70 211 141 37 166 127 120 116 122 87 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34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 - - - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_gpio.c + $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_rcc.c + + BICOMP + 194 + ICCARM - 220 + 18 __cstat - 219 + 190 - $PROJ_DIR$\..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c + [ROOT_NODE] - ICCARM - 77 - - - __cstat - 118 + ILINK + 173 57 - - - ICCARM - 216 70 211 141 37 166 127 120 116 122 87 203 189 59 102 145 112 55 138 86 30 34 231 140 230 58 119 98 97 52 143 137 88 80 91 202 128 - - diff --git a/PLSR/PLSR/EWARM/test.1/Exe/test.1.hex b/PLSR/PLSR/EWARM/test.1/Exe/test.1.hex index 783eb23..08a6e13 100644 --- a/PLSR/PLSR/EWARM/test.1/Exe/test.1.hex +++ b/PLSR/PLSR/EWARM/test.1/Exe/test.1.hex @@ -1,29 +1,29 @@ :020000040800F2 -:10000000508C0020F5670008216600082366000870 -:100010002566000827660008296600080000000021 -:100020000000000000000000000000002B66000837 -:100030002D660008000000002F66000837660008E3 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+:1066500002000100FEE7FEE7FEE7FEE7FEE7704707 +:10666000704780B5FBF7A1F801BD80B5FBF76CF969 +:1066700001BD80B51B48FCF7E9FB1B48FCF7E6FBB6 +:1066800001BD80B5F9F7C6FDFDF7DBFD1748FFF743 +:1066900085F8F9F7CDFD01BD80B51548FCF7D6FBAF +:1066A00001BD80B51348FCF7D1FB01BD80B5F9F7FA +:1066B000B1FD1148FEF749FDF9F7BAFD01BD80B5FE +:1066C000F9F7A8FD0D48FEF740FDF9F7B1FD01BD52 +:1066D00080B5F9F79FFD0A48FEF737FDF9F7A8FDE9 +:1066E00001BD000058790020307A0020507B002046 +:1066F000A0790020E879002048780020A8780020C0 +:106700008877002010B5074979441831064C7C443D +:10671000163404E00A68081D114488470146A14266 +:10672000F8D110BD2C0000004C0000004EF688513E +:10673000CEF20001086840F470000860BFF34F8F8C +:10674000BFF36F8F4FF00070E1EE100A704700004A +:10675000BFC2FFFF587C00001000002000000000B6 +:1067600067CDFFFF10000000E000000000000020E7 +:10677000000000001800000000F00DF8002801D013 +:10678000FFF7C0FFAFF300800020AFF30080FCF7FD +:10679000B1FE00F002F80120704700F001B8F000EF +:1067A0000746384600F002F8FBE7010080B5AFF37A +:1067B0000080024A11001820ABBEFBE72600020051 +:1067C00075432F4F532D494920546D724C6F636BA5 +:1067D0000000000075432F4F532D494920546D721E +:1067E0005369676E616C000000000000000000004B +:1067F000010203040607080975432F4F532D494929 +:106800002049646C6500000075432F4F532D4949A2 +:10681000205374617400000075432F4F532D494974 +:1068200020546D7200000000014880470148004775 +:1068300039680008596800080248016851F470017D +:106840000160704788ED00E0004002401000000049 +:106850000024F400E8030000AFF30080FFF766FFB8 +:10686000FFF78AFF00061016000610160000000051 +:106870000102030478563412FFF7FEBFFFF7FEBF94 :10688000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3C :10689000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2C :1068A000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF1C @@ -1685,12 +1685,15 @@ :10693000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF8B :10694000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF7B :10695000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF6B -:10696000FFF7FEBFFFF7FEBFFFF7FEBF01001000FD -:1069700014000200050001003F00010001000500B5 -:106980000100180078000100040001000400180054 -:106990000800010004000100010001008000010066 -:1069A000160001000100000101000100010040008B -:1069B0005C00E8030100747201001000010008008F -:0C69C0000A0028008002080040001A189D -:040000050800682562 +:10696000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF5B +:10697000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF4B +:10698000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF3B +:10699000FFF7FEBFFFF7FEBFFFF7FEBFFFF7FEBF2B +:1069A0000100100014000200050001003F0001007A +:1069B000010005000100180078000100040001003A +:1069C000040018000800010004000100010001009B +:1069D000800001001600010001000001010001001B +:1069E000010040005C00E803010074720100100027 +:1069F000010008000A0028008002080040001A1860 +:04000005080068592E :00000001FF diff --git a/PLSR/PLSR/EWARM/test.1/Exe/test.1.out b/PLSR/PLSR/EWARM/test.1/Exe/test.1.out index 6e15144..c1c6d5a 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Exe/test.1.out and b/PLSR/PLSR/EWARM/test.1/Exe/test.1.out differ diff --git a/PLSR/PLSR/EWARM/test.1/Exe/test.1.sim b/PLSR/PLSR/EWARM/test.1/Exe/test.1.sim index 9cad38e..5e9b51b 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Exe/test.1.sim and b/PLSR/PLSR/EWARM/test.1/Exe/test.1.sim differ diff --git a/PLSR/PLSR/EWARM/test.1/List/test.1.map b/PLSR/PLSR/EWARM/test.1/List/test.1.map index 240300b..3bdf475 100644 --- a/PLSR/PLSR/EWARM/test.1/List/test.1.map +++ b/PLSR/PLSR/EWARM/test.1/List/test.1.map @@ -1,6 +1,6 @@ ############################################################################### # -# IAR ELF Linker V8.40.1.212/W32 for ARM 12/Aug/2025 16:51:14 +# IAR ELF Linker V8.40.1.212/W32 for ARM 13/Aug/2025 19:55:15 # Copyright 2007-2019 IAR Systems AB. # # Output file = @@ -8,7 +8,7 @@ # Map file = # e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\test.1\List\test.1.map # Command line = -# -f C:\Users\Mortal\AppData\Local\Temp\EW5CF.tmp +# -f C:\Users\Mortal\AppData\Local\Temp\EW874C.tmp # (e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\test.1\Obj\app_hooks.o # e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\test.1\Obj\dma.o # e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\test.1\Obj\flash_save.o @@ -109,97 +109,84 @@ initialize by copy { rw }; .intvec ro code 0x800'0000 0x188 startup_stm32f407xx.o [1] - 0x800'0188 0x188 -"P1": 0x6844 +"P1": 0x6878 .text ro code 0x800'0188 0x15dc ucos_ii.o [1] CODE ro code 0x800'1764 0xc4 os_cpu_a.o [1] .text ro code 0x800'1828 0x190 os_cpu_c.o [1] .text ro code 0x800'19b8 0x1c0 os_dbg.o [1] .text ro code 0x800'1b78 0x10 app_hooks.o [1] - .text ro code 0x800'1b88 0xdbc tim.o [1] - .text ro code 0x800'2944 0x66 ABImemset.o [4] - .text ro code 0x800'29aa 0x3a zero_init3.o [4] - .text ro code 0x800'29e4 0xaae stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3492 0x2e copy_init3.o [4] - .text ro code 0x800'34c0 0x208 main.o [1] - .text ro code 0x800'36c8 0xac stm32f4xx_hal_tim_ex.o [1] - .text ro code 0x800'3774 0x274 stm32f4xx_hal_gpio.o [1] - .text ro code 0x800'39e8 0x114 stm32f4xx_hal_cortex.o [1] - .text ro code 0x800'3afc 0x220 flash_save.o [1] - .text ro code 0x800'3d1c 0x230 I64DivMod.o [4] - .text ro code 0x800'3f4c 0x2 stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3f4e 0x2 stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3f50 0x2 stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3f52 0x2 stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3f54 0x2 stm32f4xx_hal_tim_ex.o [1] - .text ro code 0x800'3f56 0x2 stm32f4xx_hal_tim.o [1] - .text ro code 0x800'3f58 0x2 stm32f4xx_hal_tim_ex.o [1] - .rodata const 0x800'3f5a 0x2 os_dbg.o [1] - .text ro code 0x800'3f5c 0x34 stm32f4xx_hal.o [1] - .text ro code 0x800'3f90 0xe4 gpio.o [1] - .text ro code 0x800'4074 0x7c8 usart.o [1] - .text ro code 0x800'483c 0x40 dma.o [1] - .text ro code 0x800'487c 0x3ec stm32f4xx_hal_rcc.o [1] - .text ro code 0x800'4c68 0x260 stm32f4xx_hal_rcc.o [1] - .text ro code 0x800'4ec8 0x1c stm32f4xx_hal_pwr.o [1] - .text ro code 0x800'4ee4 0x544 stm32f4xx_hal_dma.o [1] - .text ro code 0x800'5428 0x38 stm32f4xx_hal_pwr_ex.o [1] - .text ro code 0x800'5460 0x2 I64DivZer.o [4] - .rodata const 0x800'5462 0x2 os_dbg.o [1] - .text ro code 0x800'5464 0xc0 stm32f4xx_hal_timebase_tim.o [1] - .text ro code 0x800'5524 0x48 stm32f4xx_hal_msp.o [1] - .text ro code 0x800'556c 0x14 memset.o [4] - .text ro code 0x800'5580 0xc64 stm32f4xx_hal_uart.o [1] - .text ro code 0x800'61e4 0xa6 ABImemcpy.o [4] - .rodata const 0x800'628a 0x2 os_dbg.o [1] - .text ro code 0x800'628c 0x38 modbus_crc.o [1] - .text ro code 0x800'62c4 0x44 modbus_log.o [1] - .text ro code 0x800'6308 0xc stm32f4xx_hal.o [1] - .text ro code 0x800'6314 0x2 stm32f4xx_hal_uart.o [1] - .text ro code 0x800'6316 0x2 stm32f4xx_hal_uart.o [1] - .text ro code 0x800'6318 0x2 stm32f4xx_hal_uart.o [1] - .text ro code 0x800'631a 0x2 stm32f4xx_hal_uart.o [1] - .text ro code 0x800'631c 0x2 stm32f4xx_hal_uart.o [1] - .rodata const 0x800'631e 0x2 os_dbg.o [1] - .rodata const 0x800'6320 0x200 modbus_crc.o [1] - .rodata const 0x800'6520 0x100 ucos_ii.o [1] - .text ro code 0x800'6620 0xb0 stm32f4xx_it.o [1] - .text ro code 0x800'66d0 0x28 data_init.o [4] - .text ro code 0x800'66f8 0x22 fpinit_M.o [3] - .iar.init_table const 0x800'671c 0x24 - Linker created - - .rodata const 0x800'6740 0x2 os_dbg.o [1] - .text ro code 0x800'6744 0x1e cmain.o [4] - .text ro code 0x800'6762 0x4 low_level_init.o [2] - .text ro code 0x800'6766 0x4 exit.o [2] - .rodata const 0x800'676a 0x2 os_dbg.o [1] - .text ro code 0x800'676c 0xa cexit.o [4] - .rodata const 0x800'6776 0x2 os_dbg.o [1] - .text ro code 0x800'6778 0x14 exit.o [5] - .rodata const 0x800'678c 0x14 ucos_ii.o [1] - .rodata const 0x800'67a0 0x14 ucos_ii.o [1] - .rodata const 0x800'67b4 0x10 system_stm32f4xx.o [1] - .rodata const 0x800'67c4 0x10 ucos_ii.o [1] - .rodata const 0x800'67d4 0x10 ucos_ii.o [1] - .rodata const 0x800'67e4 0x10 ucos_ii.o [1] - .text ro code 0x800'67f4 0x10 startup_stm32f407xx.o [1] - .text ro code 0x800'6804 0x10 system_stm32f4xx.o [1] - Initializer bytes const 0x800'6814 0x10 - .text ro code 0x800'6824 0xc cstartup_M.o [4] - .rodata const 0x800'6830 0x8 stm32f4xx_hal_dma.o [1] - .rodata const 0x800'6838 0x8 system_stm32f4xx.o [1] - .rodata const 0x800'6840 0x4 os_dbg.o [1] - .text ro code 0x800'6844 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6848 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'684c 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6850 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6854 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6858 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'685c 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6860 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6864 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6868 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'686c 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6870 0x4 startup_stm32f407xx.o [1] - .text ro code 0x800'6874 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'1b88 0xe20 tim.o [1] + .text ro code 0x800'29a8 0x66 ABImemset.o [4] + .text ro code 0x800'2a0e 0x3a zero_init3.o [4] + .text ro code 0x800'2a48 0xa7e stm32f4xx_hal_tim.o [1] + .text ro code 0x800'34c6 0x2e copy_init3.o [4] + .text ro code 0x800'34f4 0x208 main.o [1] + .text ro code 0x800'36fc 0xac stm32f4xx_hal_tim_ex.o [1] + .text ro code 0x800'37a8 0x274 stm32f4xx_hal_gpio.o [1] + .text ro code 0x800'3a1c 0x114 stm32f4xx_hal_cortex.o [1] + .text ro code 0x800'3b30 0x220 flash_save.o [1] + .text ro code 0x800'3d50 0x230 I64DivMod.o [4] + .text ro code 0x800'3f80 0x2 stm32f4xx_hal_tim.o [1] + .text ro code 0x800'3f82 0x2 stm32f4xx_hal_tim.o [1] + .text ro code 0x800'3f84 0x2 stm32f4xx_hal_tim.o [1] + .text ro code 0x800'3f86 0x2 stm32f4xx_hal_tim.o [1] + .text ro code 0x800'3f88 0x2 stm32f4xx_hal_tim_ex.o [1] + .text ro code 0x800'3f8a 0x2 stm32f4xx_hal_tim.o [1] + .text ro code 0x800'3f8c 0x2 stm32f4xx_hal_tim_ex.o [1] + .rodata const 0x800'3f8e 0x2 os_dbg.o [1] + .text ro code 0x800'3f90 0x34 stm32f4xx_hal.o [1] + .text ro code 0x800'3fc4 0xe4 gpio.o [1] + .text ro code 0x800'40a8 0x7c8 usart.o [1] + .text ro code 0x800'4870 0x40 dma.o [1] + .text ro code 0x800'48b0 0x3ec stm32f4xx_hal_rcc.o [1] + .text ro code 0x800'4c9c 0x260 stm32f4xx_hal_rcc.o [1] + .text ro code 0x800'4efc 0x1c stm32f4xx_hal_pwr.o [1] + .text ro code 0x800'4f18 0x544 stm32f4xx_hal_dma.o [1] + .text ro code 0x800'545c 0x38 stm32f4xx_hal_pwr_ex.o [1] + .text ro code 0x800'5494 0x2 I64DivZer.o [4] + .rodata const 0x800'5496 0x2 os_dbg.o [1] + .text ro code 0x800'5498 0xc0 stm32f4xx_hal_timebase_tim.o [1] + .text ro code 0x800'5558 0x48 stm32f4xx_hal_msp.o [1] + .text ro code 0x800'55a0 0x14 memset.o [4] + .text ro code 0x800'55b4 0xc64 stm32f4xx_hal_uart.o [1] + .text ro code 0x800'6218 0xa6 ABImemcpy.o [4] + .rodata const 0x800'62be 0x2 os_dbg.o [1] + .text ro code 0x800'62c0 0x38 modbus_crc.o [1] + .text ro code 0x800'62f8 0x44 modbus_log.o [1] + .text ro code 0x800'633c 0xc stm32f4xx_hal.o [1] + .text ro code 0x800'6348 0x2 stm32f4xx_hal_uart.o [1] + .text ro code 0x800'634a 0x2 stm32f4xx_hal_uart.o [1] + .text ro code 0x800'634c 0x2 stm32f4xx_hal_uart.o [1] + .text ro code 0x800'634e 0x2 stm32f4xx_hal_uart.o [1] + .text ro code 0x800'6350 0x2 stm32f4xx_hal_uart.o [1] + .rodata const 0x800'6352 0x2 os_dbg.o [1] + .rodata const 0x800'6354 0x200 modbus_crc.o [1] + .rodata const 0x800'6554 0x100 ucos_ii.o [1] + .text ro code 0x800'6654 0xb0 stm32f4xx_it.o [1] + .text ro code 0x800'6704 0x28 data_init.o [4] + .text ro code 0x800'672c 0x22 fpinit_M.o [3] + .iar.init_table const 0x800'6750 0x24 - Linker created - + .rodata const 0x800'6774 0x2 os_dbg.o [1] + .text ro code 0x800'6778 0x1e cmain.o [4] + .text ro code 0x800'6796 0x4 low_level_init.o [2] + .text ro code 0x800'679a 0x4 exit.o [2] + .rodata const 0x800'679e 0x2 os_dbg.o [1] + .text ro code 0x800'67a0 0xa cexit.o [4] + .rodata const 0x800'67aa 0x2 os_dbg.o [1] + .text ro code 0x800'67ac 0x14 exit.o [5] + .rodata const 0x800'67c0 0x14 ucos_ii.o [1] + .rodata const 0x800'67d4 0x14 ucos_ii.o [1] + .rodata const 0x800'67e8 0x10 system_stm32f4xx.o [1] + .rodata const 0x800'67f8 0x10 ucos_ii.o [1] + .rodata const 0x800'6808 0x10 ucos_ii.o [1] + .rodata const 0x800'6818 0x10 ucos_ii.o [1] + .text ro code 0x800'6828 0x10 startup_stm32f407xx.o [1] + .text ro code 0x800'6838 0x10 system_stm32f4xx.o [1] + Initializer bytes const 0x800'6848 0x10 + .text ro code 0x800'6858 0xc cstartup_M.o [4] + .rodata const 0x800'6864 0x8 stm32f4xx_hal_dma.o [1] + .rodata const 0x800'686c 0x8 system_stm32f4xx.o [1] + .rodata const 0x800'6874 0x4 os_dbg.o [1] .text ro code 0x800'6878 0x4 startup_stm32f407xx.o [1] .text ro code 0x800'687c 0x4 startup_stm32f407xx.o [1] .text ro code 0x800'6880 0x4 startup_stm32f407xx.o [1] @@ -261,32 +248,19 @@ initialize by copy { rw }; .text ro code 0x800'6960 0x4 startup_stm32f407xx.o [1] .text ro code 0x800'6964 0x4 startup_stm32f407xx.o [1] .text ro code 0x800'6968 0x4 startup_stm32f407xx.o [1] - .rodata const 0x800'696c 0x2 os_dbg.o [1] - .rodata const 0x800'696e 0x2 os_dbg.o [1] - .rodata const 0x800'6970 0x2 os_dbg.o [1] - .rodata const 0x800'6972 0x2 os_dbg.o [1] - .rodata const 0x800'6974 0x2 os_dbg.o [1] - .rodata const 0x800'6976 0x2 os_dbg.o [1] - .rodata const 0x800'6978 0x2 os_dbg.o [1] - .rodata const 0x800'697a 0x2 os_dbg.o [1] - .rodata const 0x800'697c 0x2 os_dbg.o [1] - .rodata const 0x800'697e 0x2 os_dbg.o [1] - .rodata const 0x800'6980 0x2 os_dbg.o [1] - .rodata const 0x800'6982 0x2 os_dbg.o [1] - .rodata const 0x800'6984 0x2 os_dbg.o [1] - .rodata const 0x800'6986 0x2 os_dbg.o [1] - .rodata const 0x800'6988 0x2 os_dbg.o [1] - .rodata const 0x800'698a 0x2 os_dbg.o [1] - .rodata const 0x800'698c 0x2 os_dbg.o [1] - .rodata const 0x800'698e 0x2 os_dbg.o [1] - .rodata const 0x800'6990 0x2 os_dbg.o [1] - .rodata const 0x800'6992 0x2 os_dbg.o [1] - .rodata const 0x800'6994 0x2 os_dbg.o [1] - .rodata const 0x800'6996 0x2 os_dbg.o [1] - .rodata const 0x800'6998 0x2 os_dbg.o [1] - .rodata const 0x800'699a 0x2 os_dbg.o [1] - .rodata const 0x800'699c 0x2 os_dbg.o [1] - .rodata const 0x800'699e 0x2 os_dbg.o [1] + .text ro code 0x800'696c 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6970 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6974 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6978 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'697c 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6980 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6984 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6988 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'698c 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6990 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6994 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'6998 0x4 startup_stm32f407xx.o [1] + .text ro code 0x800'699c 0x4 startup_stm32f407xx.o [1] .rodata const 0x800'69a0 0x2 os_dbg.o [1] .rodata const 0x800'69a2 0x2 os_dbg.o [1] .rodata const 0x800'69a4 0x2 os_dbg.o [1] @@ -309,9 +283,35 @@ initialize by copy { rw }; .rodata const 0x800'69c6 0x2 os_dbg.o [1] .rodata const 0x800'69c8 0x2 os_dbg.o [1] .rodata const 0x800'69ca 0x2 os_dbg.o [1] - .rodata const 0x800'69cc 0x0 zero_init3.o [4] - .rodata const 0x800'69cc 0x0 copy_init3.o [4] - - 0x800'69cc 0x6844 + .rodata const 0x800'69cc 0x2 os_dbg.o [1] + .rodata const 0x800'69ce 0x2 os_dbg.o [1] + .rodata const 0x800'69d0 0x2 os_dbg.o [1] + .rodata const 0x800'69d2 0x2 os_dbg.o [1] + .rodata const 0x800'69d4 0x2 os_dbg.o [1] + .rodata const 0x800'69d6 0x2 os_dbg.o [1] + .rodata const 0x800'69d8 0x2 os_dbg.o [1] + .rodata const 0x800'69da 0x2 os_dbg.o [1] + .rodata const 0x800'69dc 0x2 os_dbg.o [1] + .rodata const 0x800'69de 0x2 os_dbg.o [1] + .rodata const 0x800'69e0 0x2 os_dbg.o [1] + .rodata const 0x800'69e2 0x2 os_dbg.o [1] + .rodata const 0x800'69e4 0x2 os_dbg.o [1] + .rodata const 0x800'69e6 0x2 os_dbg.o [1] + .rodata const 0x800'69e8 0x2 os_dbg.o [1] + .rodata const 0x800'69ea 0x2 os_dbg.o [1] + .rodata const 0x800'69ec 0x2 os_dbg.o [1] + .rodata const 0x800'69ee 0x2 os_dbg.o [1] + .rodata const 0x800'69f0 0x2 os_dbg.o [1] + .rodata const 0x800'69f2 0x2 os_dbg.o [1] + .rodata const 0x800'69f4 0x2 os_dbg.o [1] + .rodata const 0x800'69f6 0x2 os_dbg.o [1] + .rodata const 0x800'69f8 0x2 os_dbg.o [1] + .rodata const 0x800'69fa 0x2 os_dbg.o [1] + .rodata const 0x800'69fc 0x2 os_dbg.o [1] + .rodata const 0x800'69fe 0x2 os_dbg.o [1] + .rodata const 0x800'6a00 0x0 zero_init3.o [4] + .rodata const 0x800'6a00 0x0 copy_init3.o [4] + - 0x800'6a00 0x6878 "P2", part 1 of 3: 0x10 P2-1 0x2000'0000 0x10 @@ -321,7 +321,7 @@ initialize by copy { rw }; .data inited 0x2000'000c 0x4 tim.o [1] - 0x2000'0010 0x10 -"P2", part 2 of 3: 0x7c40 +"P2", part 2 of 3: 0x7c58 .bss zero 0x2000'0010 0x4a04 usart.o [1] .bss zero 0x2000'4a14 0x7e8 ucos_ii.o [1] .bss zero 0x2000'51fc 0x400 main.o [1] @@ -333,41 +333,37 @@ initialize by copy { rw }; .bss zero 0x2000'69fc 0x280 ucos_ii.o [1] .bss zero 0x2000'6c7c 0x200 os_cpu_c.o [1] .bss zero 0x2000'6e7c 0x200 ucos_ii.o [1] - .bss zero 0x2000'707c 0x194 tim.o [1] - .bss zero 0x2000'7210 0x100 ucos_ii.o [1] - .bss zero 0x2000'7310 0x100 usart.o [1] - .bss zero 0x2000'7410 0x100 usart.o [1] - .bss zero 0x2000'7510 0x100 usart.o [1] - .bss zero 0x2000'7610 0xf0 ucos_ii.o [1] - .bss zero 0x2000'7700 0x78 ucos_ii.o [1] - .bss zero 0x2000'7778 0x60 flash_save.o [1] - .bss zero 0x2000'77d8 0x60 ucos_ii.o [1] - .bss zero 0x2000'7838 0x60 usart.o [1] - .bss zero 0x2000'7898 0x60 usart.o [1] - .bss zero 0x2000'78f8 0x50 ucos_ii.o [1] - .bss zero 0x2000'7948 0x48 stm32f4xx_hal_timebase_tim.o [1] - .bss zero 0x2000'7990 0x48 tim.o [1] - .bss zero 0x2000'79d8 0x48 tim.o [1] - .bss zero 0x2000'7a20 0x48 tim.o [1] - .bss zero 0x2000'7a68 0x48 tim.o [1] - .bss zero 0x2000'7ab0 0x48 tim.o [1] - .bss zero 0x2000'7af8 0x48 tim.o [1] - .bss zero 0x2000'7b40 0x48 usart.o [1] - .bss zero 0x2000'7b88 0x40 ucos_ii.o [1] - .bss zero 0x2000'7bc8 0x8 ucos_ii.o [1] - .bss zero 0x2000'7bd0 0x4 os_cpu_c.o [1] - .bss zero 0x2000'7bd4 0x4 stm32f4xx_hal.o [1] - .bss zero 0x2000'7bd8 0x4 tim.o [1] - .bss zero 0x2000'7bdc 0x4 tim.o [1] - .bss zero 0x2000'7be0 0x4 tim.o [1] - .bss zero 0x2000'7be4 0x4 tim.o [1] + .bss zero 0x2000'707c 0x1a4 tim.o [1] + .bss zero 0x2000'7220 0x100 ucos_ii.o [1] + .bss zero 0x2000'7320 0x100 usart.o [1] + .bss zero 0x2000'7420 0x100 usart.o [1] + .bss zero 0x2000'7520 0x100 usart.o [1] + .bss zero 0x2000'7620 0xf0 ucos_ii.o [1] + .bss zero 0x2000'7710 0x78 ucos_ii.o [1] + .bss zero 0x2000'7788 0x60 flash_save.o [1] + .bss zero 0x2000'77e8 0x60 ucos_ii.o [1] + .bss zero 0x2000'7848 0x60 usart.o [1] + .bss zero 0x2000'78a8 0x60 usart.o [1] + .bss zero 0x2000'7908 0x50 ucos_ii.o [1] + .bss zero 0x2000'7958 0x48 stm32f4xx_hal_timebase_tim.o [1] + .bss zero 0x2000'79a0 0x48 tim.o [1] + .bss zero 0x2000'79e8 0x48 tim.o [1] + .bss zero 0x2000'7a30 0x48 tim.o [1] + .bss zero 0x2000'7a78 0x48 tim.o [1] + .bss zero 0x2000'7ac0 0x48 tim.o [1] + .bss zero 0x2000'7b08 0x48 tim.o [1] + .bss zero 0x2000'7b50 0x48 usart.o [1] + .bss zero 0x2000'7b98 0x40 ucos_ii.o [1] + .bss zero 0x2000'7bd8 0x8 ucos_ii.o [1] + .bss zero 0x2000'7be0 0x4 os_cpu_c.o [1] + .bss zero 0x2000'7be4 0x4 stm32f4xx_hal.o [1] .bss zero 0x2000'7be8 0x4 tim.o [1] - .bss zero 0x2000'7bec 0x4 ucos_ii.o [1] - .bss zero 0x2000'7bf0 0x4 ucos_ii.o [1] - .bss zero 0x2000'7bf4 0x4 ucos_ii.o [1] - .bss zero 0x2000'7bf8 0x4 ucos_ii.o [1] - .bss zero 0x2000'7bfc 0x4 ucos_ii.o [1] - .bss zero 0x2000'7c00 0x4 ucos_ii.o [1] + .bss zero 0x2000'7bec 0x4 tim.o [1] + .bss zero 0x2000'7bf0 0x4 tim.o [1] + .bss zero 0x2000'7bf4 0x4 tim.o [1] + .bss zero 0x2000'7bf8 0x4 tim.o [1] + .bss zero 0x2000'7bfc 0x4 tim.o [1] + .bss zero 0x2000'7c00 0x4 tim.o [1] .bss zero 0x2000'7c04 0x4 ucos_ii.o [1] .bss zero 0x2000'7c08 0x4 ucos_ii.o [1] .bss zero 0x2000'7c0c 0x4 ucos_ii.o [1] @@ -379,43 +375,49 @@ initialize by copy { rw }; .bss zero 0x2000'7c24 0x4 ucos_ii.o [1] .bss zero 0x2000'7c28 0x4 ucos_ii.o [1] .bss zero 0x2000'7c2c 0x4 ucos_ii.o [1] - .bss zero 0x2000'7c30 0x2 modbus_log.o [1] - .bss zero 0x2000'7c32 0x2 os_cpu_c.o [1] - .bss zero 0x2000'7c34 0x2 ucos_ii.o [1] - .bss zero 0x2000'7c36 0x2 ucos_ii.o [1] - .bss zero 0x2000'7c38 0x2 usart.o [1] - .bss zero 0x2000'7c3a 0x2 usart.o [1] - .bss zero 0x2000'7c3c 0x2 usart.o [1] - .bss zero 0x2000'7c3e 0x2 usart.o [1] - .bss zero 0x2000'7c40 0x1 flash_save.o [1] - .bss zero 0x2000'7c41 0x1 tim.o [1] - .bss zero 0x2000'7c42 0x1 tim.o [1] - .bss zero 0x2000'7c43 0x1 tim.o [1] - .bss zero 0x2000'7c44 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c45 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c46 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c47 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c48 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c49 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4a 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4b 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4c 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4d 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4e 0x1 ucos_ii.o [1] - .bss zero 0x2000'7c4f 0x1 usart.o [1] - - 0x2000'7c50 0x7c40 + .bss zero 0x2000'7c30 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c34 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c38 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c3c 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c40 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c44 0x4 ucos_ii.o [1] + .bss zero 0x2000'7c48 0x2 modbus_log.o [1] + .bss zero 0x2000'7c4a 0x2 os_cpu_c.o [1] + .bss zero 0x2000'7c4c 0x2 ucos_ii.o [1] + .bss zero 0x2000'7c4e 0x2 ucos_ii.o [1] + .bss zero 0x2000'7c50 0x2 usart.o [1] + .bss zero 0x2000'7c52 0x2 usart.o [1] + .bss zero 0x2000'7c54 0x2 usart.o [1] + .bss zero 0x2000'7c56 0x2 usart.o [1] + .bss zero 0x2000'7c58 0x1 flash_save.o [1] + .bss zero 0x2000'7c59 0x1 tim.o [1] + .bss zero 0x2000'7c5a 0x1 tim.o [1] + .bss zero 0x2000'7c5b 0x1 tim.o [1] + .bss zero 0x2000'7c5c 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c5d 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c5e 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c5f 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c60 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c61 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c62 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c63 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c64 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c65 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c66 0x1 ucos_ii.o [1] + .bss zero 0x2000'7c67 0x1 usart.o [1] + - 0x2000'7c68 0x7c58 "P2", part 3 of 3: 0x1000 - CSTACK 0x2000'7c50 0x1000 - CSTACK uninit 0x2000'7c50 0x1000 - - 0x2000'8c50 0x1000 + CSTACK 0x2000'7c68 0x1000 + CSTACK uninit 0x2000'7c68 0x1000 + - 0x2000'8c68 0x1000 Unused ranges: From To Size ---- -- ---- - 0x800'69cc 0x80f'ffff 0xf'9634 - 0x2000'8c50 0x2001'ffff 0x1'73b0 + 0x800'6a00 0x80f'ffff 0xf'9600 + 0x2000'8c68 0x2001'ffff 0x1'7398 ******************************************************************************* @@ -425,12 +427,12 @@ Unused ranges: Address Size ------- ---- Zero (__iar_zero_init3) - 1 destination range, total size 0x7c40: - 0x2000'0010 0x7c40 + 1 destination range, total size 0x7c58: + 0x2000'0010 0x7c58 Copy (__iar_copy_init3) 1 source range, total size 0x10: - 0x800'6814 0x10 + 0x800'6848 0x10 1 destination range, total size 0x10: 0x2000'0000 0x10 @@ -466,17 +468,17 @@ e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\test.1\Obj: [1] stm32f4xx_hal_pwr.o 28 stm32f4xx_hal_pwr_ex.o 56 stm32f4xx_hal_rcc.o 1'612 - stm32f4xx_hal_tim.o 2'744 + stm32f4xx_hal_tim.o 2'696 stm32f4xx_hal_tim_ex.o 176 stm32f4xx_hal_timebase_tim.o 192 72 stm32f4xx_hal_uart.o 3'182 stm32f4xx_it.o 176 system_stm32f4xx.o 16 28 4 - tim.o 3'516 4 863 + tim.o 3'616 4 887 ucos_ii.o 5'596 344 6'171 usart.o 1'992 19'989 ------------------------------------------------------- - Total: 24'918 1'018 31'824 + Total: 24'970 1'018 31'848 dl7M_tlf.a: [2] exit.o 4 @@ -512,7 +514,7 @@ shb_l.a: [5] Gaps 2 2 Linker created 36 4'096 ----------------------------------------------------------- - Grand Total: 26'028 1'056 35'920 + Grand Total: 26'080 1'056 35'944 ******************************************************************************* @@ -521,12 +523,12 @@ shb_l.a: [5] Entry Address Size Type Object ----- ------- ---- ---- ------ -.iar.init_table$$Base 0x800'671c -- Gb - Linker created - -.iar.init_table$$Limit 0x800'6740 -- Gb - Linker created - -?main 0x800'6745 Code Gb cmain.o [4] -AHBPrescTable 0x800'67b4 0x10 Data Gb system_stm32f4xx.o [1] -APBPrescTable 0x800'6838 0x8 Data Gb system_stm32f4xx.o [1] -AllPluse 0x2000'7be8 0x4 Data Lc tim.o [1] +.iar.init_table$$Base 0x800'6750 -- Gb - Linker created - +.iar.init_table$$Limit 0x800'6774 -- Gb - Linker created - +?main 0x800'6779 Code Gb cmain.o [4] +AHBPrescTable 0x800'67e8 0x10 Data Gb system_stm32f4xx.o [1] +APBPrescTable 0x800'686c 0x8 Data Gb system_stm32f4xx.o [1] +AllPluse 0x2000'7bfc 0x4 Data Lc tim.o [1] App_TCBInitHook 0x800'1b85 0x2 Code Gb app_hooks.o [1] App_TaskCreateHook 0x800'1b79 0x2 Code Gb app_hooks.o [1] App_TaskDelHook 0x800'1b7b 0x2 Code Gb app_hooks.o [1] @@ -535,261 +537,260 @@ App_TaskReturnHook 0x800'1b81 0x2 Code Gb app_hooks.o [1] App_TaskStatHook 0x800'1b7f 0x2 Code Gb app_hooks.o [1] App_TaskSwHook 0x800'1b83 0x2 Code Gb app_hooks.o [1] App_TimeTickHook 0x800'1b87 0x2 Code Gb app_hooks.o [1] -BackupSRAM_Init 0x800'3c0d 0x48 Code Gb flash_save.o [1] -BackupSRAM_RestoreData 0x800'3c9f 0x5e Code Gb flash_save.o [1] -BackupSRAM_SaveRegData 0x800'3c55 0x4a Code Gb flash_save.o [1] -BusFault_Handler 0x800'6627 0x2 Code Gb stm32f4xx_it.o [1] -CSTACK$$Base 0x2000'7c50 -- Gb - Linker created - -CSTACK$$Limit 0x2000'8c50 -- Gb - Linker created - +BackupSRAM_Init 0x800'3c41 0x48 Code Gb flash_save.o [1] +BackupSRAM_RestoreData 0x800'3cd3 0x5e Code Gb flash_save.o [1] +BackupSRAM_SaveRegData 0x800'3c89 0x4a Code Gb flash_save.o [1] +BusFault_Handler 0x800'665b 0x2 Code Gb stm32f4xx_it.o [1] +CSTACK$$Base 0x2000'7c68 -- Gb - Linker created - +CSTACK$$Limit 0x2000'8c68 -- Gb - Linker created - DMA2_Stream0_IRQHandler - 0x800'669d 0x12 Code Gb stm32f4xx_it.o [1] + 0x800'66d1 0x12 Code Gb stm32f4xx_it.o [1] DMA2_Stream2_IRQHandler - 0x800'6679 0x12 Code Gb stm32f4xx_it.o [1] + 0x800'66ad 0x12 Code Gb stm32f4xx_it.o [1] DMA2_Stream7_IRQHandler - 0x800'668b 0x12 Code Gb stm32f4xx_it.o [1] -DMA_Backup_Init 0x800'3b1d 0x78 Code Gb flash_save.o [1] + 0x800'66bf 0x12 Code Gb stm32f4xx_it.o [1] +DMA_Backup_Init 0x800'3b51 0x78 Code Gb flash_save.o [1] DMA_CalcBaseAndBitshift - 0x800'534d 0x30 Code Lc stm32f4xx_hal_dma.o [1] + 0x800'5381 0x30 Code Lc stm32f4xx_hal_dma.o [1] DMA_CalcBaseAndBitshift::flagBitshiftOffset - 0x800'6830 0x8 Data Lc stm32f4xx_hal_dma.o [1] -DMA_CheckFifoParam 0x800'538d 0x9c Code Lc stm32f4xx_hal_dma.o [1] -DMA_SetConfig 0x800'531f 0x2e Code Lc stm32f4xx_hal_dma.o [1] + 0x800'6864 0x8 Data Lc stm32f4xx_hal_dma.o [1] +DMA_CheckFifoParam 0x800'53c1 0x9c Code Lc stm32f4xx_hal_dma.o [1] +DMA_SetConfig 0x800'5353 0x2e Code Lc stm32f4xx_hal_dma.o [1] DMA_Start_CopyFromBKPSRAM - 0x800'3bd1 0x3c Code Gb flash_save.o [1] + 0x800'3c05 0x3c Code Gb flash_save.o [1] DMA_Start_CopyToBKPSRAM - 0x800'3b95 0x3c Code Gb flash_save.o [1] -DebugMon_Handler 0x800'662d 0x2 Code Gb stm32f4xx_it.o [1] -EnableBackupDomain 0x800'3afd 0x20 Code Gb flash_save.o [1] -Error_Handler 0x800'36c5 0x4 Code Gb main.o [1] -HAL_DMA_Abort 0x800'5053 0x9c Code Gb stm32f4xx_hal_dma.o [1] -HAL_DMA_Abort_IT 0x800'50ef 0x28 Code Gb stm32f4xx_hal_dma.o [1] -HAL_DMA_IRQHandler 0x800'5117 0x208 Code Gb stm32f4xx_hal_dma.o [1] -HAL_DMA_Init 0x800'4ee5 0xe2 Code Gb stm32f4xx_hal_dma.o [1] -HAL_DMA_Start_IT 0x800'4fc7 0x8c Code Gb stm32f4xx_hal_dma.o [1] -HAL_GPIO_Init 0x800'3775 0x222 Code Gb stm32f4xx_hal_gpio.o [1] -HAL_GPIO_WritePin 0x800'3997 0x1a Code Gb stm32f4xx_hal_gpio.o [1] -HAL_GetTick 0x800'6309 0xc Code Wk stm32f4xx_hal.o [1] -HAL_Init 0x800'3f5d 0x30 Code Gb stm32f4xx_hal.o [1] -HAL_InitTick 0x800'5465 0xac Code Gb stm32f4xx_hal_timebase_tim.o [1] -HAL_MspInit 0x800'5525 0x48 Code Gb stm32f4xx_hal_msp.o [1] -HAL_NVIC_EnableIRQ 0x800'3adb 0xe Code Gb stm32f4xx_hal_cortex.o [1] -HAL_NVIC_SetPriority 0x800'3ab1 0x2a Code Gb stm32f4xx_hal_cortex.o [1] + 0x800'3bc9 0x3c Code Gb flash_save.o [1] +DebugMon_Handler 0x800'6661 0x2 Code Gb stm32f4xx_it.o [1] +EnableBackupDomain 0x800'3b31 0x20 Code Gb flash_save.o [1] +Error_Handler 0x800'36f9 0x4 Code Gb main.o [1] +HAL_DMA_Abort 0x800'5087 0x9c Code Gb stm32f4xx_hal_dma.o [1] +HAL_DMA_Abort_IT 0x800'5123 0x28 Code Gb stm32f4xx_hal_dma.o [1] +HAL_DMA_IRQHandler 0x800'514b 0x208 Code Gb stm32f4xx_hal_dma.o [1] +HAL_DMA_Init 0x800'4f19 0xe2 Code Gb stm32f4xx_hal_dma.o [1] +HAL_DMA_Start_IT 0x800'4ffb 0x8c Code Gb stm32f4xx_hal_dma.o [1] +HAL_GPIO_Init 0x800'37a9 0x222 Code Gb stm32f4xx_hal_gpio.o [1] +HAL_GPIO_WritePin 0x800'39cb 0x1a Code Gb stm32f4xx_hal_gpio.o [1] +HAL_GetTick 0x800'633d 0xc Code Wk stm32f4xx_hal.o [1] +HAL_Init 0x800'3f91 0x30 Code Gb stm32f4xx_hal.o [1] +HAL_InitTick 0x800'5499 0xac Code Gb stm32f4xx_hal_timebase_tim.o [1] +HAL_MspInit 0x800'5559 0x48 Code Gb stm32f4xx_hal_msp.o [1] +HAL_NVIC_EnableIRQ 0x800'3b0f 0xe Code Gb stm32f4xx_hal_cortex.o [1] +HAL_NVIC_SetPriority 0x800'3ae5 0x2a Code Gb stm32f4xx_hal_cortex.o [1] HAL_NVIC_SetPriorityGrouping - 0x800'3aa5 0xc Code Gb stm32f4xx_hal_cortex.o [1] + 0x800'3ad9 0xc Code Gb stm32f4xx_hal_cortex.o [1] HAL_PWREx_EnableBkUpReg - 0x800'5429 0x2e Code Gb stm32f4xx_hal_pwr_ex.o [1] + 0x800'545d 0x2e Code Gb stm32f4xx_hal_pwr_ex.o [1] HAL_PWR_EnableBkUpAccess - 0x800'4ec9 0x14 Code Gb stm32f4xx_hal_pwr.o [1] -HAL_RCC_ClockConfig 0x800'4c69 0x140 Code Gb stm32f4xx_hal_rcc.o [1] -HAL_RCC_GetClockConfig 0x800'4ddb 0x34 Code Gb stm32f4xx_hal_rcc.o [1] -HAL_RCC_GetHCLKFreq 0x800'4da9 0x6 Code Gb stm32f4xx_hal_rcc.o [1] -HAL_RCC_GetPCLK1Freq 0x800'4daf 0x16 Code Gb stm32f4xx_hal_rcc.o [1] -HAL_RCC_GetPCLK2Freq 0x800'4dc5 0x16 Code Gb stm32f4xx_hal_rcc.o [1] -HAL_RCC_OscConfig 0x800'487d 0x3ec Code Wk stm32f4xx_hal_rcc.o [1] + 0x800'4efd 0x14 Code Gb stm32f4xx_hal_pwr.o [1] +HAL_RCC_ClockConfig 0x800'4c9d 0x140 Code Gb stm32f4xx_hal_rcc.o [1] +HAL_RCC_GetClockConfig 0x800'4e0f 0x34 Code Gb stm32f4xx_hal_rcc.o [1] +HAL_RCC_GetHCLKFreq 0x800'4ddd 0x6 Code Gb stm32f4xx_hal_rcc.o [1] +HAL_RCC_GetPCLK1Freq 0x800'4de3 0x16 Code Gb stm32f4xx_hal_rcc.o [1] +HAL_RCC_GetPCLK2Freq 0x800'4df9 0x16 Code Gb stm32f4xx_hal_rcc.o [1] +HAL_RCC_OscConfig 0x800'48b1 0x3ec Code Wk stm32f4xx_hal_rcc.o [1] HAL_TIMEx_BreakCallback - 0x800'3f55 0x2 Code Wk stm32f4xx_hal_tim_ex.o [1] + 0x800'3f89 0x2 Code Wk stm32f4xx_hal_tim_ex.o [1] HAL_TIMEx_CommutCallback - 0x800'3f59 0x2 Code Wk stm32f4xx_hal_tim_ex.o [1] + 0x800'3f8d 0x2 Code Wk stm32f4xx_hal_tim_ex.o [1] HAL_TIMEx_MasterConfigSynchronization - 0x800'36c9 0x8e Code Gb stm32f4xx_hal_tim_ex.o [1] -HAL_TIM_Base_Init 0x800'29e5 0x6e Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_Base_MspInit 0x800'1eff 0x15e Code Gb tim.o [1] -HAL_TIM_Base_Start_IT 0x800'2a83 0x9a Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_Base_Stop 0x800'2a53 0x30 Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_Base_Stop_IT 0x800'2b1d 0x3c Code Gb stm32f4xx_hal_tim.o [1] + 0x800'36fd 0x8e Code Gb stm32f4xx_hal_tim_ex.o [1] +HAL_TIM_Base_Init 0x800'2a49 0x6e Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_Base_MspInit 0x800'1f01 0x15e Code Gb tim.o [1] +HAL_TIM_Base_Start_IT 0x800'2ab7 0x9a Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_Base_Stop_IT 0x800'2b51 0x3c Code Gb stm32f4xx_hal_tim.o [1] HAL_TIM_ConfigClockSource - 0x800'3081 0xf4 Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_GenerateEvent 0x800'3053 0x2e Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_IRQHandler 0x800'2e19 0x13e Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_MspPostInit 0x800'205d 0x128 Code Gb tim.o [1] + 0x800'30b5 0xf4 Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_GenerateEvent 0x800'3087 0x2e Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_IRQHandler 0x800'2e4d 0x13e Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_MspPostInit 0x800'205f 0x128 Code Gb tim.o [1] HAL_TIM_PWM_ConfigChannel - 0x800'2f57 0xfc Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_PWM_Init 0x800'2b75 0x6e Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_PWM_Start_IT 0x800'2c91 0x16a Code Gb stm32f4xx_hal_tim.o [1] -HAL_TIM_PWM_Stop 0x800'2be3 0xae Code Gb stm32f4xx_hal_tim.o [1] + 0x800'2f8b 0xfc Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_PWM_Init 0x800'2ba9 0x6e Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_PWM_Start_IT 0x800'2cc5 0x16a Code Gb stm32f4xx_hal_tim.o [1] +HAL_TIM_PWM_Stop 0x800'2c17 0xae Code Gb stm32f4xx_hal_tim.o [1] HAL_TIM_PeriodElapsedCallback - 0x800'23a7 0x148 Code Gb tim.o [1] -HAL_UART_DMAStop 0x800'56d7 0x92 Code Gb stm32f4xx_hal_uart.o [1] -HAL_UART_IRQHandler 0x800'5769 0x2f6 Code Gb stm32f4xx_hal_uart.o [1] -HAL_UART_Init 0x800'5581 0x7a Code Gb stm32f4xx_hal_uart.o [1] -HAL_UART_MspInit 0x800'40d3 0x13c Code Gb usart.o [1] -HAL_UART_Receive_DMA 0x800'56a1 0x36 Code Gb stm32f4xx_hal_uart.o [1] -HAL_UART_Transmit_DMA 0x800'55fb 0x9a Code Gb stm32f4xx_hal_uart.o [1] + 0x800'23e9 0x176 Code Gb tim.o [1] +HAL_UART_DMAStop 0x800'570b 0x92 Code Gb stm32f4xx_hal_uart.o [1] +HAL_UART_IRQHandler 0x800'579d 0x2f6 Code Gb stm32f4xx_hal_uart.o [1] +HAL_UART_Init 0x800'55b5 0x7a Code Gb stm32f4xx_hal_uart.o [1] +HAL_UART_MspInit 0x800'4107 0x13c Code Gb usart.o [1] +HAL_UART_Receive_DMA 0x800'56d5 0x36 Code Gb stm32f4xx_hal_uart.o [1] +HAL_UART_Transmit_DMA 0x800'562f 0x9a Code Gb stm32f4xx_hal_uart.o [1] HAL_UART_TxCpltCallback - 0x800'431b 0x14 Code Gb usart.o [1] -HardFault_Handler 0x800'6623 0x2 Code Gb stm32f4xx_it.o [1] -KeyTask 0x800'365d 0x46 Code Lc main.o [1] + 0x800'434f 0x14 Code Gb usart.o [1] +HardFault_Handler 0x800'6657 0x2 Code Gb stm32f4xx_it.o [1] +KeyTask 0x800'3689 0x50 Code Lc main.o [1] KeyTaskStk 0x2000'59fc 0x400 Data Lc main.o [1] -MODBUSTask 0x800'3645 0x18 Code Lc main.o [1] +MODBUSTask 0x800'3671 0x16 Code Lc main.o [1] MODBUSTaskStk 0x2000'55fc 0x400 Data Lc main.o [1] -MX_DMA_Init 0x800'483d 0x40 Code Gb dma.o [1] -MX_GPIO_Init 0x800'3f91 0xe4 Code Gb gpio.o [1] -MX_TIM10_Init 0x800'1d19 0x7e Code Gb tim.o [1] -MX_TIM11_Init 0x800'1d97 0x78 Code Gb tim.o [1] -MX_TIM13_Init 0x800'1e0f 0x78 Code Gb tim.o [1] -MX_TIM14_Init 0x800'1e87 0x78 Code Gb tim.o [1] -MX_TIM2_Init 0x800'1c3f 0x88 Code Gb tim.o [1] -MX_TIM6_Init 0x800'1cc7 0x52 Code Gb tim.o [1] -MX_USART1_UART_Init 0x800'4075 0x5e Code Gb usart.o [1] -MemManage_Handler 0x800'6625 0x2 Code Gb stm32f4xx_it.o [1] +MX_DMA_Init 0x800'4871 0x40 Code Gb dma.o [1] +MX_GPIO_Init 0x800'3fc5 0xe4 Code Gb gpio.o [1] +MX_TIM10_Init 0x800'1d1b 0x7e Code Gb tim.o [1] +MX_TIM11_Init 0x800'1d99 0x78 Code Gb tim.o [1] +MX_TIM13_Init 0x800'1e11 0x78 Code Gb tim.o [1] +MX_TIM14_Init 0x800'1e89 0x78 Code Gb tim.o [1] +MX_TIM2_Init 0x800'1c3f 0x8a Code Gb tim.o [1] +MX_TIM6_Init 0x800'1cc9 0x52 Code Gb tim.o [1] +MX_USART1_UART_Init 0x800'40a9 0x5e Code Gb usart.o [1] +MemManage_Handler 0x800'6659 0x2 Code Gb stm32f4xx_it.o [1] ModbusSlave 0x2000'0010 0x4a04 Data Gb usart.o [1] -Modbus_CRC16 0x800'628d 0x34 Code Gb modbus_crc.o [1] -Modbus_Handle_SendLog 0x800'4435 0x11c Code Gb usart.o [1] -Modbus_Init 0x800'432f 0x1e Code Gb usart.o [1] -Modbus_Log 0x800'62c5 0x44 Code Gb modbus_log.o [1] -Modbus_Process 0x800'434d 0xe8 Code Gb usart.o [1] +Modbus_CRC16 0x800'62c1 0x34 Code Gb modbus_crc.o [1] +Modbus_Handle_SendLog 0x800'4469 0x11c Code Gb usart.o [1] +Modbus_Init 0x800'4363 0x1e Code Gb usart.o [1] +Modbus_Log 0x800'62f9 0x44 Code Gb modbus_log.o [1] +Modbus_Process 0x800'4381 0xe8 Code Gb usart.o [1] Modbus_Process_Read_Holding_Regs - 0x800'4551 0xc8 Code Lc usart.o [1] + 0x800'4585 0xc8 Code Lc usart.o [1] Modbus_Process_Write_Multiple_Regs - 0x800'46ad 0xd4 Code Lc usart.o [1] + 0x800'46e1 0xd4 Code Lc usart.o [1] Modbus_Process_Write_Reg - 0x800'4619 0x94 Code Lc usart.o [1] -Modbus_Send_Exception 0x800'47b3 0x3e Code Lc usart.o [1] -Modbus_Send_Response 0x800'4781 0x32 Code Lc usart.o [1] -NMI_Handler 0x800'6621 0x2 Code Gb stm32f4xx_it.o [1] -NVIC_EncodePriority 0x800'3a65 0x40 Code Lc stm32f4xx_hal_cortex.o [1] -OSCPUUsage 0x2000'7c44 0x1 Data Gb ucos_ii.o [1] + 0x800'464d 0x94 Code Lc usart.o [1] +Modbus_Send_Exception 0x800'47e7 0x3e Code Lc usart.o [1] +Modbus_Send_Response 0x800'47b5 0x32 Code Lc usart.o [1] +NMI_Handler 0x800'6655 0x2 Code Gb stm32f4xx_it.o [1] +NVIC_EncodePriority 0x800'3a99 0x40 Code Lc stm32f4xx_hal_cortex.o [1] +OSCPUUsage 0x2000'7c5c 0x1 Data Gb ucos_ii.o [1] OSCtxSw 0x800'179b Code Gb os_cpu_a.o [1] -OSCtxSwCtr 0x2000'7bec 0x4 Data Gb ucos_ii.o [1] -OSDataSize 0x800'69ca 0x2 Data Gb os_dbg.o [1] -OSDebugEn 0x800'3f5a 0x2 Data Gb os_dbg.o [1] +OSCtxSwCtr 0x2000'7c04 0x4 Data Gb ucos_ii.o [1] +OSDataSize 0x800'69fe 0x2 Data Gb os_dbg.o [1] +OSDebugEn 0x800'3f8e 0x2 Data Gb os_dbg.o [1] OSDebugInit 0x800'19b9 0x1c0 Code Gb os_dbg.o [1] -OSEndiannessTest 0x800'6840 0x4 Data Gb os_dbg.o [1] -OSEventEn 0x800'5462 0x2 Data Gb os_dbg.o [1] -OSEventFreeList 0x2000'7bf0 0x4 Data Gb ucos_ii.o [1] -OSEventMax 0x800'628a 0x2 Data Gb os_dbg.o [1] -OSEventMultiEn 0x800'6776 0x2 Data Gb os_dbg.o [1] -OSEventNameEn 0x800'631e 0x2 Data Gb os_dbg.o [1] +OSEndiannessTest 0x800'6874 0x4 Data Gb os_dbg.o [1] +OSEventEn 0x800'5496 0x2 Data Gb os_dbg.o [1] +OSEventFreeList 0x2000'7c08 0x4 Data Gb ucos_ii.o [1] +OSEventMax 0x800'62be 0x2 Data Gb os_dbg.o [1] +OSEventMultiEn 0x800'67aa 0x2 Data Gb os_dbg.o [1] +OSEventNameEn 0x800'6352 0x2 Data Gb os_dbg.o [1] OSEventNameSet 0x800'0189 0x54 Code Gb ucos_ii.o [1] -OSEventSize 0x800'6740 0x2 Data Gb os_dbg.o [1] -OSEventTbl 0x2000'7610 0xf0 Data Gb ucos_ii.o [1] -OSEventTblSize 0x800'676a 0x2 Data Gb os_dbg.o [1] -OSFlagEn 0x800'696c 0x2 Data Gb os_dbg.o [1] -OSFlagFreeList 0x2000'7bf4 0x4 Data Gb ucos_ii.o [1] -OSFlagGrpSize 0x800'696e 0x2 Data Gb os_dbg.o [1] -OSFlagMax 0x800'6974 0x2 Data Gb os_dbg.o [1] -OSFlagNameEn 0x800'6976 0x2 Data Gb os_dbg.o [1] -OSFlagNodeSize 0x800'6970 0x2 Data Gb os_dbg.o [1] -OSFlagTbl 0x2000'78f8 0x50 Data Gb ucos_ii.o [1] -OSFlagWidth 0x800'6972 0x2 Data Gb os_dbg.o [1] -OSIdleCtr 0x2000'7c00 0x4 Data Gb ucos_ii.o [1] -OSIdleCtrMax 0x2000'7bf8 0x4 Data Gb ucos_ii.o [1] -OSIdleCtrRun 0x2000'7bfc 0x4 Data Gb ucos_ii.o [1] +OSEventSize 0x800'6774 0x2 Data Gb os_dbg.o [1] +OSEventTbl 0x2000'7620 0xf0 Data Gb ucos_ii.o [1] +OSEventTblSize 0x800'679e 0x2 Data Gb os_dbg.o [1] +OSFlagEn 0x800'69a0 0x2 Data Gb os_dbg.o [1] +OSFlagFreeList 0x2000'7c0c 0x4 Data Gb ucos_ii.o [1] +OSFlagGrpSize 0x800'69a2 0x2 Data Gb os_dbg.o [1] +OSFlagMax 0x800'69a8 0x2 Data Gb os_dbg.o [1] +OSFlagNameEn 0x800'69aa 0x2 Data Gb os_dbg.o [1] +OSFlagNodeSize 0x800'69a4 0x2 Data Gb os_dbg.o [1] +OSFlagTbl 0x2000'7908 0x50 Data Gb ucos_ii.o [1] +OSFlagWidth 0x800'69a6 0x2 Data Gb os_dbg.o [1] +OSIdleCtr 0x2000'7c18 0x4 Data Gb ucos_ii.o [1] +OSIdleCtrMax 0x2000'7c10 0x4 Data Gb ucos_ii.o [1] +OSIdleCtrRun 0x2000'7c14 0x4 Data Gb ucos_ii.o [1] OSInit 0x800'01dd 0x38 Code Gb ucos_ii.o [1] OSInitHookBegin 0x800'1829 0x2c Code Gb os_cpu_c.o [1] OSInitHookEnd 0x800'1855 0x2 Code Gb os_cpu_c.o [1] OSIntCtxSw 0x800'17a3 Code Gb os_cpu_a.o [1] OSIntEnter 0x800'0215 0x1c Code Gb ucos_ii.o [1] OSIntExit 0x800'0231 0x78 Code Gb ucos_ii.o [1] -OSIntNesting 0x2000'7c46 0x1 Data Gb ucos_ii.o [1] -OSLockNesting 0x2000'7c47 0x1 Data Gb ucos_ii.o [1] -OSLowestPrio 0x800'6978 0x2 Data Gb os_dbg.o [1] -OSMboxEn 0x800'697a 0x2 Data Gb os_dbg.o [1] -OSMemEn 0x800'697c 0x2 Data Gb os_dbg.o [1] -OSMemFreeList 0x2000'7c14 0x4 Data Gb ucos_ii.o [1] -OSMemMax 0x800'697e 0x2 Data Gb os_dbg.o [1] -OSMemNameEn 0x800'6980 0x2 Data Gb os_dbg.o [1] -OSMemSize 0x800'6982 0x2 Data Gb os_dbg.o [1] -OSMemTbl 0x2000'7700 0x78 Data Gb ucos_ii.o [1] -OSMemTblSize 0x800'6984 0x2 Data Gb os_dbg.o [1] -OSMutexEn 0x800'6986 0x2 Data Gb os_dbg.o [1] -OSPrioCur 0x2000'7c48 0x1 Data Gb ucos_ii.o [1] -OSPrioHighRdy 0x2000'7c49 0x1 Data Gb ucos_ii.o [1] -OSPtrSize 0x800'6988 0x2 Data Gb os_dbg.o [1] -OSQEn 0x800'698a 0x2 Data Gb os_dbg.o [1] -OSQFreeList 0x2000'7c18 0x4 Data Gb ucos_ii.o [1] -OSQMax 0x800'698c 0x2 Data Gb os_dbg.o [1] -OSQSize 0x800'698e 0x2 Data Gb os_dbg.o [1] -OSQTbl 0x2000'77d8 0x60 Data Gb ucos_ii.o [1] -OSRdyGrp 0x2000'7c4a 0x1 Data Gb ucos_ii.o [1] -OSRdyTbl 0x2000'7bc8 0x8 Data Gb ucos_ii.o [1] -OSRdyTblSize 0x800'6990 0x2 Data Gb os_dbg.o [1] -OSRunning 0x2000'7c4b 0x1 Data Gb ucos_ii.o [1] +OSIntNesting 0x2000'7c5e 0x1 Data Gb ucos_ii.o [1] +OSLockNesting 0x2000'7c5f 0x1 Data Gb ucos_ii.o [1] +OSLowestPrio 0x800'69ac 0x2 Data Gb os_dbg.o [1] +OSMboxEn 0x800'69ae 0x2 Data Gb os_dbg.o [1] +OSMemEn 0x800'69b0 0x2 Data Gb os_dbg.o [1] +OSMemFreeList 0x2000'7c2c 0x4 Data Gb ucos_ii.o [1] +OSMemMax 0x800'69b2 0x2 Data Gb os_dbg.o [1] +OSMemNameEn 0x800'69b4 0x2 Data Gb os_dbg.o [1] +OSMemSize 0x800'69b6 0x2 Data Gb os_dbg.o [1] +OSMemTbl 0x2000'7710 0x78 Data Gb ucos_ii.o [1] +OSMemTblSize 0x800'69b8 0x2 Data Gb os_dbg.o [1] +OSMutexEn 0x800'69ba 0x2 Data Gb os_dbg.o [1] +OSPrioCur 0x2000'7c60 0x1 Data Gb ucos_ii.o [1] +OSPrioHighRdy 0x2000'7c61 0x1 Data Gb ucos_ii.o [1] +OSPtrSize 0x800'69bc 0x2 Data Gb os_dbg.o [1] +OSQEn 0x800'69be 0x2 Data Gb os_dbg.o [1] +OSQFreeList 0x2000'7c30 0x4 Data Gb ucos_ii.o [1] +OSQMax 0x800'69c0 0x2 Data Gb os_dbg.o [1] +OSQSize 0x800'69c2 0x2 Data Gb os_dbg.o [1] +OSQTbl 0x2000'77e8 0x60 Data Gb ucos_ii.o [1] +OSRdyGrp 0x2000'7c62 0x1 Data Gb ucos_ii.o [1] +OSRdyTbl 0x2000'7bd8 0x8 Data Gb ucos_ii.o [1] +OSRdyTblSize 0x800'69c4 0x2 Data Gb os_dbg.o [1] +OSRunning 0x2000'7c63 0x1 Data Gb ucos_ii.o [1] OSSchedLock 0x800'02a9 0x36 Code Gb ucos_ii.o [1] OSSchedUnlock 0x800'02df 0x58 Code Gb ucos_ii.o [1] OSSemCreate 0x800'0d33 0x4e Code Gb ucos_ii.o [1] -OSSemEn 0x800'6992 0x2 Data Gb os_dbg.o [1] +OSSemEn 0x800'69c6 0x2 Data Gb os_dbg.o [1] OSSemPend 0x800'0d83 0xe8 Code Gb ucos_ii.o [1] OSSemPost 0x800'0e75 0x62 Code Gb ucos_ii.o [1] OSStart 0x800'0337 0x3a Code Gb ucos_ii.o [1] OSStartHighRdy 0x800'1773 Code Gb os_cpu_a.o [1] OSStatInit 0x800'0371 0x42 Code Gb ucos_ii.o [1] -OSStatRdy 0x2000'7c45 0x1 Data Gb ucos_ii.o [1] -OSStkWidth 0x800'6994 0x2 Data Gb os_dbg.o [1] -OSTCBCur 0x2000'7c04 0x4 Data Gb ucos_ii.o [1] -OSTCBFreeList 0x2000'7c08 0x4 Data Gb ucos_ii.o [1] -OSTCBHighRdy 0x2000'7c0c 0x4 Data Gb ucos_ii.o [1] +OSStatRdy 0x2000'7c5d 0x1 Data Gb ucos_ii.o [1] +OSStkWidth 0x800'69c8 0x2 Data Gb os_dbg.o [1] +OSTCBCur 0x2000'7c1c 0x4 Data Gb ucos_ii.o [1] +OSTCBFreeList 0x2000'7c20 0x4 Data Gb ucos_ii.o [1] +OSTCBHighRdy 0x2000'7c24 0x4 Data Gb ucos_ii.o [1] OSTCBInitHook 0x800'191f 0xc Code Gb os_cpu_c.o [1] -OSTCBList 0x2000'7c10 0x4 Data Gb ucos_ii.o [1] -OSTCBPrioTbl 0x2000'7210 0x100 Data Gb ucos_ii.o [1] -OSTCBPrioTblMax 0x800'69ae 0x2 Data Gb os_dbg.o [1] -OSTCBSize 0x800'69b0 0x2 Data Gb os_dbg.o [1] +OSTCBList 0x2000'7c28 0x4 Data Gb ucos_ii.o [1] +OSTCBPrioTbl 0x2000'7220 0x100 Data Gb ucos_ii.o [1] +OSTCBPrioTblMax 0x800'69e2 0x2 Data Gb os_dbg.o [1] +OSTCBSize 0x800'69e4 0x2 Data Gb os_dbg.o [1] OSTCBTbl 0x2000'4a14 0x7e8 Data Gb ucos_ii.o [1] -OSTaskCreateEn 0x800'6996 0x2 Data Gb os_dbg.o [1] +OSTaskCreateEn 0x800'69ca 0x2 Data Gb os_dbg.o [1] OSTaskCreateExt 0x800'0ee1 0xd4 Code Gb ucos_ii.o [1] -OSTaskCreateExtEn 0x800'6998 0x2 Data Gb os_dbg.o [1] +OSTaskCreateExtEn 0x800'69cc 0x2 Data Gb os_dbg.o [1] OSTaskCreateHook 0x800'1857 0xc Code Gb os_cpu_c.o [1] -OSTaskCtr 0x2000'7c4c 0x1 Data Gb ucos_ii.o [1] +OSTaskCtr 0x2000'7c64 0x1 Data Gb ucos_ii.o [1] OSTaskDel 0x800'0fb5 0x17a Code Gb ucos_ii.o [1] -OSTaskDelEn 0x800'699a 0x2 Data Gb os_dbg.o [1] +OSTaskDelEn 0x800'69ce 0x2 Data Gb os_dbg.o [1] OSTaskDelHook 0x800'1863 0xc Code Gb os_cpu_c.o [1] OSTaskIdleHook 0x800'186f 0x8 Code Gb os_cpu_c.o [1] OSTaskIdleStk 0x2000'6e7c 0x200 Data Gb ucos_ii.o [1] -OSTaskIdleStkSize 0x800'699c 0x2 Data Gb os_dbg.o [1] -OSTaskMax 0x800'69a0 0x2 Data Gb os_dbg.o [1] -OSTaskNameEn 0x800'69a2 0x2 Data Gb os_dbg.o [1] +OSTaskIdleStkSize 0x800'69d0 0x2 Data Gb os_dbg.o [1] +OSTaskMax 0x800'69d4 0x2 Data Gb os_dbg.o [1] +OSTaskNameEn 0x800'69d6 0x2 Data Gb os_dbg.o [1] OSTaskNameSet 0x800'112f 0x90 Code Gb ucos_ii.o [1] -OSTaskProfileEn 0x800'699e 0x2 Data Gb os_dbg.o [1] -OSTaskRegNextAvailID 0x2000'7c4e 0x1 Data Gb ucos_ii.o [1] -OSTaskRegTblSize 0x800'69ac 0x2 Data Gb os_dbg.o [1] +OSTaskProfileEn 0x800'69d2 0x2 Data Gb os_dbg.o [1] +OSTaskRegNextAvailID 0x2000'7c66 0x1 Data Gb ucos_ii.o [1] +OSTaskRegTblSize 0x800'69e0 0x2 Data Gb os_dbg.o [1] OSTaskReturnHook 0x800'1877 0xc Code Gb os_cpu_c.o [1] -OSTaskStatEn 0x800'69a4 0x2 Data Gb os_dbg.o [1] +OSTaskStatEn 0x800'69d8 0x2 Data Gb os_dbg.o [1] OSTaskStatHook 0x800'1883 0x8 Code Gb os_cpu_c.o [1] OSTaskStatStk 0x2000'61fc 0x400 Data Gb ucos_ii.o [1] -OSTaskStatStkChkEn 0x800'69a8 0x2 Data Gb os_dbg.o [1] -OSTaskStatStkSize 0x800'69a6 0x2 Data Gb os_dbg.o [1] +OSTaskStatStkChkEn 0x800'69dc 0x2 Data Gb os_dbg.o [1] +OSTaskStatStkSize 0x800'69da 0x2 Data Gb os_dbg.o [1] OSTaskStkChk 0x800'11cd 0xb4 Code Gb ucos_ii.o [1] OSTaskStkInit 0x800'188b 0x8c Code Gb os_cpu_c.o [1] OSTaskSuspend 0x800'1281 0xd6 Code Gb ucos_ii.o [1] OSTaskSwHook 0x800'1917 0x8 Code Gb os_cpu_c.o [1] -OSTaskSwHookEn 0x800'69aa 0x2 Data Gb os_dbg.o [1] -OSTickStepState 0x2000'7c4d 0x1 Data Gb ucos_ii.o [1] -OSTicksPerSec 0x800'69b2 0x2 Data Gb os_dbg.o [1] -OSTime 0x2000'7c1c 0x4 Data Gb ucos_ii.o [1] +OSTaskSwHookEn 0x800'69de 0x2 Data Gb os_dbg.o [1] +OSTickStepState 0x2000'7c65 0x1 Data Gb ucos_ii.o [1] +OSTicksPerSec 0x800'69e6 0x2 Data Gb os_dbg.o [1] +OSTime 0x2000'7c34 0x4 Data Gb ucos_ii.o [1] OSTimeDly 0x800'1387 0x6e Code Gb ucos_ii.o [1] OSTimeDlyHMSM 0x800'1401 0xb0 Code Gb ucos_ii.o [1] OSTimeTick 0x800'03b3 0xe4 Code Gb ucos_ii.o [1] OSTimeTickHook 0x800'192b 0x1e Code Gb os_cpu_c.o [1] -OSTimeTickHookEn 0x800'69b4 0x2 Data Gb os_dbg.o [1] -OSTmrCfgMax 0x800'69ba 0x2 Data Gb os_dbg.o [1] -OSTmrCfgNameEn 0x800'69bc 0x2 Data Gb os_dbg.o [1] -OSTmrCfgTicksPerSec 0x800'69c0 0x2 Data Gb os_dbg.o [1] -OSTmrCfgWheelSize 0x800'69be 0x2 Data Gb os_dbg.o [1] -OSTmrCtr 0x2000'7c32 0x2 Data Lc os_cpu_c.o [1] -OSTmrEn 0x800'69b8 0x2 Data Gb os_dbg.o [1] -OSTmrFree 0x2000'7c34 0x2 Data Gb ucos_ii.o [1] -OSTmrFreeList 0x2000'7c2c 0x4 Data Gb ucos_ii.o [1] -OSTmrSem 0x2000'7c24 0x4 Data Gb ucos_ii.o [1] -OSTmrSemSignal 0x2000'7c28 0x4 Data Gb ucos_ii.o [1] +OSTimeTickHookEn 0x800'69e8 0x2 Data Gb os_dbg.o [1] +OSTmrCfgMax 0x800'69ee 0x2 Data Gb os_dbg.o [1] +OSTmrCfgNameEn 0x800'69f0 0x2 Data Gb os_dbg.o [1] +OSTmrCfgTicksPerSec 0x800'69f4 0x2 Data Gb os_dbg.o [1] +OSTmrCfgWheelSize 0x800'69f2 0x2 Data Gb os_dbg.o [1] +OSTmrCtr 0x2000'7c4a 0x2 Data Lc os_cpu_c.o [1] +OSTmrEn 0x800'69ec 0x2 Data Gb os_dbg.o [1] +OSTmrFree 0x2000'7c4c 0x2 Data Gb ucos_ii.o [1] +OSTmrFreeList 0x2000'7c44 0x4 Data Gb ucos_ii.o [1] +OSTmrSem 0x2000'7c3c 0x4 Data Gb ucos_ii.o [1] +OSTmrSemSignal 0x2000'7c40 0x4 Data Gb ucos_ii.o [1] OSTmrSignal 0x800'14c9 0xe Code Gb ucos_ii.o [1] -OSTmrSize 0x800'69c2 0x2 Data Gb os_dbg.o [1] +OSTmrSize 0x800'69f6 0x2 Data Gb os_dbg.o [1] OSTmrTaskStk 0x2000'65fc 0x400 Data Gb ucos_ii.o [1] OSTmrTbl 0x2000'69fc 0x280 Data Gb ucos_ii.o [1] -OSTmrTblSize 0x800'69c4 0x2 Data Gb os_dbg.o [1] -OSTmrTime 0x2000'7c20 0x4 Data Gb ucos_ii.o [1] -OSTmrUsed 0x2000'7c36 0x2 Data Gb ucos_ii.o [1] -OSTmrWheelSize 0x800'69c6 0x2 Data Gb os_dbg.o [1] -OSTmrWheelTbl 0x2000'7b88 0x40 Data Gb ucos_ii.o [1] -OSTmrWheelTblSize 0x800'69c8 0x2 Data Gb os_dbg.o [1] +OSTmrTblSize 0x800'69f8 0x2 Data Gb os_dbg.o [1] +OSTmrTime 0x2000'7c38 0x4 Data Gb ucos_ii.o [1] +OSTmrUsed 0x2000'7c4e 0x2 Data Gb ucos_ii.o [1] +OSTmrWheelSize 0x800'69fa 0x2 Data Gb os_dbg.o [1] +OSTmrWheelTbl 0x2000'7b98 0x40 Data Gb ucos_ii.o [1] +OSTmrWheelTblSize 0x800'69fc 0x2 Data Gb os_dbg.o [1] OSTmr_Init 0x800'14d7 0xcc Code Gb ucos_ii.o [1] OSTmr_InitTask 0x800'15a3 0x3a Code Lc ucos_ii.o [1] OSTmr_Link 0x800'15dd 0x72 Code Lc ucos_ii.o [1] OSTmr_Task 0x800'169d 0x88 Code Lc ucos_ii.o [1] OSTmr_Unlink 0x800'164f 0x4c Code Lc ucos_ii.o [1] -OSUnMapTbl 0x800'6520 0x100 Data Gb ucos_ii.o [1] -OSVersionNbr 0x800'69b6 0x2 Data Gb os_dbg.o [1] +OSUnMapTbl 0x800'6554 0x100 Data Gb ucos_ii.o [1] +OSVersionNbr 0x800'69ea 0x2 Data Gb os_dbg.o [1] OS_CPU_ExceptStk 0x2000'6c7c 0x200 Data Gb os_cpu_c.o [1] -OS_CPU_ExceptStkBase 0x2000'7bd0 0x4 Data Gb os_cpu_c.o [1] +OS_CPU_ExceptStkBase 0x2000'7be0 0x4 Data Gb os_cpu_c.o [1] OS_CPU_PendSVHandler 0x800'17ab Code Gb os_cpu_a.o [1] OS_CPU_SR_Restore 0x800'176d Code Gb os_cpu_a.o [1] OS_CPU_SR_Save 0x800'1765 Code Gb os_cpu_a.o [1] @@ -822,143 +823,142 @@ OS_TaskReturn 0x800'135d 0x12 Code Gb ucos_ii.o [1] OS_TaskStat 0x800'0905 0xca Code Gb ucos_ii.o [1] OS_TaskStatStkChk 0x800'09cf 0x48 Code Gb ucos_ii.o [1] OS_TaskStkClr 0x800'136f 0x18 Code Gb ucos_ii.o [1] -PLSR_Accel_CalculateSteps - 0x800'27ad 0x94 Code Lc tim.o [1] -PLSR_Accel_Process 0x800'2855 0xc Code Gb tim.o [1] +PLSR_Accel_Process 0x800'2819 0xca Code Gb tim.o [1] +PLSR_Accel_UpdateRates 0x800'28e9 0x32 Code Gb tim.o [1] PLSR_CalculateTimerParams - 0x800'21dd 0x112 Code Lc tim.o [1] -PLSR_PWM_Init 0x800'2185 0x2a Code Gb tim.o [1] -PLSR_PWM_SetFrequency 0x800'22ef 0x46 Code Gb tim.o [1] -PLSR_PWM_Start 0x800'21af 0x18 Code Gb tim.o [1] -PLSR_PWM_Stop 0x800'21c7 0x16 Code Gb tim.o [1] -PLSR_Route_Init 0x800'25f5 0x48 Code Gb tim.o [1] -PLSR_Route_Set 0x800'24ef 0xf4 Code Gb tim.o [1] -PLSR_Route_Start 0x800'263d 0x78 Code Gb tim.o [1] -PLSR_Route_Stop 0x800'26b9 0x4a Code Gb tim.o [1] -PLSR_Section_CalculateConstPulse - 0x800'2795 0x6 Code Gb tim.o [1] -PLSR_Section_CheckPulseComplete - 0x800'2861 0x44 Code Gb tim.o [1] + 0x800'21d7 0x12a Code Lc tim.o [1] +PLSR_PWM_Init 0x800'2187 0x2a Code Gb tim.o [1] +PLSR_PWM_SetFrequency 0x800'2301 0x46 Code Gb tim.o [1] +PLSR_PWM_Start 0x800'21b1 0x18 Code Gb tim.o [1] +PLSR_PWM_Stop 0x800'21c9 0xe Code Gb tim.o [1] +PLSR_Route_Init 0x800'268d 0x50 Code Gb tim.o [1] +PLSR_Route_Set 0x800'2575 0x102 Code Gb tim.o [1] +PLSR_Route_Start 0x800'26dd 0xaa Code Gb tim.o [1] +PLSR_Route_Stop 0x800'2787 0x38 Code Gb tim.o [1] PLSR_Section_CheckWaitCondition - 0x800'28a5 0x64 Code Gb tim.o [1] -PLSR_Section_Process 0x800'270d 0x2e Code Gb tim.o [1] + 0x800'291b 0x60 Code Gb tim.o [1] PLSR_Section_StartNewSection - 0x800'273b 0x5a Code Gb tim.o [1] + 0x800'27d9 0x40 Code Gb tim.o [1] PLSR_TIM6_SetUpdateFreq - 0x800'2335 0x5a Code Gb tim.o [1] -PLSR_TIM6_Start 0x800'238f 0xc Code Gb tim.o [1] -PLSR_TIM6_Stop 0x800'239b 0xc Code Gb tim.o [1] + 0x800'2347 0x5a Code Gb tim.o [1] +PLSR_TIM6_Start 0x800'23a1 0xc Code Gb tim.o [1] +PLSR_TIM6_Stop 0x800'23ad 0xc Code Gb tim.o [1] +PLSR_UpdateModbusPulseCount + 0x800'23b9 0x16 Code Lc tim.o [1] PLSR_Wait_CheckExtEvent 0x800'1c11 0x2e Code Gb tim.o [1] PLSR_Wait_CheckTime 0x800'1be9 0x28 Code Gb tim.o [1] PLSR_Wait_StartTimer 0x800'1b89 0x60 Code Gb tim.o [1] -PendSV_Handler 0x800'662f 0x8 Code Gb stm32f4xx_it.o [1] -Region$$Table$$Base 0x800'671c -- Gb - Linker created - -Region$$Table$$Limit 0x800'6740 -- Gb - Linker created - -SVC_Handler 0x800'662b 0x2 Code Gb stm32f4xx_it.o [1] -StartupTask 0x800'35c5 0x80 Code Lc main.o [1] +PendSV_Handler 0x800'6663 0x8 Code Gb stm32f4xx_it.o [1] +Region$$Table$$Base 0x800'6750 -- Gb - Linker created - +Region$$Table$$Limit 0x800'6774 -- Gb - Linker created - +SVC_Handler 0x800'665f 0x2 Code Gb stm32f4xx_it.o [1] +StartupTask 0x800'35f9 0x76 Code Lc main.o [1] StartupTaskStk 0x2000'51fc 0x400 Data Lc main.o [1] -SysTick_Handler 0x800'6637 0x8 Code Gb stm32f4xx_it.o [1] -SystemClock_Config 0x800'3519 0xaa Code Gb main.o [1] +SysTick_Handler 0x800'666b 0x8 Code Gb stm32f4xx_it.o [1] +SystemClock_Config 0x800'354d 0xaa Code Gb main.o [1] SystemCoreClock 0x2000'0008 0x4 Data Gb system_stm32f4xx.o [1] -SystemInit 0x800'6805 0xc Code Gb system_stm32f4xx.o [1] +SystemInit 0x800'6839 0xc Code Gb system_stm32f4xx.o [1] TIM1_UP_TIM10_IRQHandler - 0x800'663f 0x10 Code Gb stm32f4xx_it.o [1] -TIM2_IRQHandler 0x800'6665 0xa Code Gb stm32f4xx_it.o [1] -TIM6_DAC_IRQHandler 0x800'666f 0xa Code Gb stm32f4xx_it.o [1] -TIM_Base_SetConfig 0x800'3175 0xcc Code Gb stm32f4xx_hal_tim.o [1] -TIM_CCxChannelCmd 0x800'346f 0x24 Code Gb stm32f4xx_hal_tim.o [1] -TIM_ETR_SetConfig 0x800'3457 0x18 Code Gb stm32f4xx_hal_tim.o [1] -TIM_ITRx_SetConfig 0x800'3447 0x10 Code Lc stm32f4xx_hal_tim.o [1] -TIM_OC1_SetConfig 0x800'3243 0x64 Code Lc stm32f4xx_hal_tim.o [1] -TIM_OC2_SetConfig 0x800'32a7 0x6e Code Gb stm32f4xx_hal_tim.o [1] -TIM_OC3_SetConfig 0x800'3317 0x6c Code Lc stm32f4xx_hal_tim.o [1] -TIM_OC4_SetConfig 0x800'3383 0x4c Code Lc stm32f4xx_hal_tim.o [1] + 0x800'6673 0x10 Code Gb stm32f4xx_it.o [1] +TIM2_IRQHandler 0x800'6699 0xa Code Gb stm32f4xx_it.o [1] +TIM6_DAC_IRQHandler 0x800'66a3 0xa Code Gb stm32f4xx_it.o [1] +TIM_Base_SetConfig 0x800'31a9 0xcc Code Gb stm32f4xx_hal_tim.o [1] +TIM_CCxChannelCmd 0x800'34a3 0x24 Code Gb stm32f4xx_hal_tim.o [1] +TIM_ETR_SetConfig 0x800'348b 0x18 Code Gb stm32f4xx_hal_tim.o [1] +TIM_ITRx_SetConfig 0x800'347b 0x10 Code Lc stm32f4xx_hal_tim.o [1] +TIM_OC1_SetConfig 0x800'3277 0x64 Code Lc stm32f4xx_hal_tim.o [1] +TIM_OC2_SetConfig 0x800'32db 0x6e Code Gb stm32f4xx_hal_tim.o [1] +TIM_OC3_SetConfig 0x800'334b 0x6c Code Lc stm32f4xx_hal_tim.o [1] +TIM_OC4_SetConfig 0x800'33b7 0x4c Code Lc stm32f4xx_hal_tim.o [1] TIM_TI1_ConfigInputStage - 0x800'33fd 0x24 Code Lc stm32f4xx_hal_tim.o [1] + 0x800'3431 0x24 Code Lc stm32f4xx_hal_tim.o [1] TIM_TI2_ConfigInputStage - 0x800'3421 0x26 Code Lc stm32f4xx_hal_tim.o [1] -UART_DMAAbortOnError 0x800'5d3d 0x12 Code Lc stm32f4xx_hal_uart.o [1] -UART_DMAError 0x800'5b91 0x58 Code Lc stm32f4xx_hal_uart.o [1] -UART_DMAReceiveCplt 0x800'5ac1 0xaa Code Lc stm32f4xx_hal_uart.o [1] -UART_DMARxHalfCplt 0x800'5b6b 0x26 Code Lc stm32f4xx_hal_uart.o [1] -UART_DMATransmitCplt 0x800'5a5f 0x54 Code Lc stm32f4xx_hal_uart.o [1] -UART_DMATxHalfCplt 0x800'5ab3 0xe Code Lc stm32f4xx_hal_uart.o [1] -UART_EndRxTransfer 0x800'5cd5 0x66 Code Lc stm32f4xx_hal_uart.o [1] -UART_EndTransmit_IT 0x800'5db7 0x20 Code Lc stm32f4xx_hal_uart.o [1] -UART_EndTxTransfer 0x800'5cb1 0x24 Code Lc stm32f4xx_hal_uart.o [1] -UART_Receive_IT 0x800'5dd7 0xfa Code Lc stm32f4xx_hal_uart.o [1] -UART_SetConfig 0x800'5ed1 0x2fc Code Lc stm32f4xx_hal_uart.o [1] -UART_Start_Receive_DMA 0x800'5be9 0xc8 Code Gb stm32f4xx_hal_uart.o [1] -UART_Transmit_IT 0x800'5d51 0x66 Code Lc stm32f4xx_hal_uart.o [1] -USART1_IDLE_IRQHandler 0x800'420f 0x96 Code Gb usart.o [1] -USART1_IRQHandler 0x800'664f 0x16 Code Gb stm32f4xx_it.o [1] -USART1_SendData 0x800'4305 0x16 Code Gb usart.o [1] -USART1_SendData_DMA 0x800'42a5 0x60 Code Gb usart.o [1] -UsageFault_Handler 0x800'6629 0x2 Code Gb stm32f4xx_it.o [1] -Usart1_Rx_Count 0x2000'7c3c 0x2 Data Gb usart.o [1] -__NVIC_EnableIRQ 0x800'3a19 0x20 Code Lc stm32f4xx_hal_cortex.o [1] + 0x800'3455 0x26 Code Lc stm32f4xx_hal_tim.o [1] +UART_DMAAbortOnError 0x800'5d71 0x12 Code Lc stm32f4xx_hal_uart.o [1] +UART_DMAError 0x800'5bc5 0x58 Code Lc stm32f4xx_hal_uart.o [1] +UART_DMAReceiveCplt 0x800'5af5 0xaa Code Lc stm32f4xx_hal_uart.o [1] +UART_DMARxHalfCplt 0x800'5b9f 0x26 Code Lc stm32f4xx_hal_uart.o [1] +UART_DMATransmitCplt 0x800'5a93 0x54 Code Lc stm32f4xx_hal_uart.o [1] +UART_DMATxHalfCplt 0x800'5ae7 0xe Code Lc stm32f4xx_hal_uart.o [1] +UART_EndRxTransfer 0x800'5d09 0x66 Code Lc stm32f4xx_hal_uart.o [1] +UART_EndTransmit_IT 0x800'5deb 0x20 Code Lc stm32f4xx_hal_uart.o [1] +UART_EndTxTransfer 0x800'5ce5 0x24 Code Lc stm32f4xx_hal_uart.o [1] +UART_Receive_IT 0x800'5e0b 0xfa Code Lc stm32f4xx_hal_uart.o [1] +UART_SetConfig 0x800'5f05 0x2fc Code Lc stm32f4xx_hal_uart.o [1] +UART_Start_Receive_DMA 0x800'5c1d 0xc8 Code Gb stm32f4xx_hal_uart.o [1] +UART_Transmit_IT 0x800'5d85 0x66 Code Lc stm32f4xx_hal_uart.o [1] +USART1_IDLE_IRQHandler 0x800'4243 0x96 Code Gb usart.o [1] +USART1_IRQHandler 0x800'6683 0x16 Code Gb stm32f4xx_it.o [1] +USART1_SendData 0x800'4339 0x16 Code Gb usart.o [1] +USART1_SendData_DMA 0x800'42d9 0x60 Code Gb usart.o [1] +UsageFault_Handler 0x800'665d 0x2 Code Gb stm32f4xx_it.o [1] +Usart1_Rx_Count 0x2000'7c54 0x2 Data Gb usart.o [1] +__NVIC_EnableIRQ 0x800'3a4d 0x20 Code Lc stm32f4xx_hal_cortex.o [1] __NVIC_GetPriorityGrouping - 0x800'3a0b 0xc Code Lc stm32f4xx_hal_cortex.o [1] -__NVIC_SetPriority 0x800'3a39 0x2c Code Lc stm32f4xx_hal_cortex.o [1] + 0x800'3a3f 0xc Code Lc stm32f4xx_hal_cortex.o [1] +__NVIC_SetPriority 0x800'3a6d 0x2c Code Lc stm32f4xx_hal_cortex.o [1] __NVIC_SetPriorityGrouping - 0x800'39e9 0x22 Code Lc stm32f4xx_hal_cortex.o [1] -__aeabi_ldiv0 0x800'5461 Code Gb I64DivZer.o [4] -__aeabi_memcpy 0x800'61e5 Code Gb ABImemcpy.o [4] -__aeabi_memcpy4 0x800'6205 Code Gb ABImemcpy.o [4] -__aeabi_memcpy8 0x800'6205 Code Gb ABImemcpy.o [4] -__aeabi_memset 0x800'2945 Code Gb ABImemset.o [4] -__aeabi_uldivmod 0x800'3d1d Code Gb I64DivMod.o [4] -__cmain 0x800'6745 Code Gb cmain.o [4] -__exit 0x800'6779 0x14 Code Gb exit.o [5] -__iar_Memset 0x800'2945 Code Gb ABImemset.o [4] -__iar_Memset_word 0x800'294d Code Gb ABImemset.o [4] -__iar_copy_init3 0x800'3493 0x2e Code Gb copy_init3.o [4] -__iar_data_init3 0x800'66d1 0x28 Code Gb data_init.o [4] -__iar_init_vfp 0x800'66f9 Code Gb fpinit_M.o [3] -__iar_program_start 0x800'6825 Code Gb cstartup_M.o [4] -__iar_zero_init3 0x800'29ab 0x3a Code Gb zero_init3.o [4] -__low_level_init 0x800'6763 0x4 Code Gb low_level_init.o [2] + 0x800'3a1d 0x22 Code Lc stm32f4xx_hal_cortex.o [1] +__aeabi_ldiv0 0x800'5495 Code Gb I64DivZer.o [4] +__aeabi_memcpy 0x800'6219 Code Gb ABImemcpy.o [4] +__aeabi_memcpy4 0x800'6239 Code Gb ABImemcpy.o [4] +__aeabi_memcpy8 0x800'6239 Code Gb ABImemcpy.o [4] +__aeabi_memset 0x800'29a9 Code Gb ABImemset.o [4] +__aeabi_uldivmod 0x800'3d51 Code Gb I64DivMod.o [4] +__cmain 0x800'6779 Code Gb cmain.o [4] +__exit 0x800'67ad 0x14 Code Gb exit.o [5] +__iar_Memset 0x800'29a9 Code Gb ABImemset.o [4] +__iar_Memset_word 0x800'29b1 Code Gb ABImemset.o [4] +__iar_copy_init3 0x800'34c7 0x2e Code Gb copy_init3.o [4] +__iar_data_init3 0x800'6705 0x28 Code Gb data_init.o [4] +__iar_init_vfp 0x800'672d Code Gb fpinit_M.o [3] +__iar_program_start 0x800'6859 Code Gb cstartup_M.o [4] +__iar_zero_init3 0x800'2a0f 0x3a Code Gb zero_init3.o [4] +__low_level_init 0x800'6797 0x4 Code Gb low_level_init.o [2] __vector_table 0x800'0000 Data Gb startup_stm32f407xx.o [1] -_call_main 0x800'6751 Code Gb cmain.o [4] -_exit 0x800'676d Code Gb cexit.o [4] -_main 0x800'675f Code Gb cmain.o [4] +_call_main 0x800'6785 Code Gb cmain.o [4] +_exit 0x800'67a1 Code Gb cexit.o [4] +_main 0x800'6793 Code Gb cmain.o [4] backup_data 0x2000'0000 0x4 Data Lc flash_save.o [1] -crc_table 0x800'6320 0x200 Data Lc modbus_crc.o [1] -dma_bkpsram_done_flag 0x2000'7c40 0x1 Data Gb flash_save.o [1] -exit 0x800'6767 0x4 Code Gb exit.o [2] -g_plsr_ext_event_flag 0x2000'7c41 0x1 Data Gb tim.o [1] -g_plsr_route 0x2000'707c 0x194 Data Gb tim.o [1] -hdma_backup 0x2000'7778 0x60 Data Gb flash_save.o [1] -hdma_usart1_rx 0x2000'7838 0x60 Data Gb usart.o [1] -hdma_usart1_tx 0x2000'7898 0x60 Data Gb usart.o [1] -htim1 0x2000'7948 0x48 Data Gb stm32f4xx_hal_timebase_tim.o [1] -htim10 0x2000'7a20 0x48 Data Gb tim.o [1] -htim11 0x2000'7a68 0x48 Data Gb tim.o [1] -htim13 0x2000'7ab0 0x48 Data Gb tim.o [1] -htim14 0x2000'7af8 0x48 Data Gb tim.o [1] -htim2 0x2000'7990 0x48 Data Gb tim.o [1] -htim6 0x2000'79d8 0x48 Data Gb tim.o [1] -huart1 0x2000'7b40 0x48 Data Gb usart.o [1] -log_write_index 0x2000'7c30 0x2 Data Gb modbus_log.o [1] -main 0x800'34c1 0x58 Code Gb main.o [1] -memset 0x800'556d 0x14 Code Gb memset.o [4] +crc_table 0x800'6354 0x200 Data Lc modbus_crc.o [1] +dma_bkpsram_done_flag 0x2000'7c58 0x1 Data Gb flash_save.o [1] +exit 0x800'679b 0x4 Code Gb exit.o [2] +g_plsr_ext_event_flag 0x2000'7c59 0x1 Data Gb tim.o [1] +g_plsr_route 0x2000'707c 0x1a4 Data Gb tim.o [1] +g_plsr_total_pulse_count + 0x2000'7be8 0x4 Data Gb tim.o [1] +hdma_backup 0x2000'7788 0x60 Data Gb flash_save.o [1] +hdma_usart1_rx 0x2000'7848 0x60 Data Gb usart.o [1] +hdma_usart1_tx 0x2000'78a8 0x60 Data Gb usart.o [1] +htim1 0x2000'7958 0x48 Data Gb stm32f4xx_hal_timebase_tim.o [1] +htim10 0x2000'7a30 0x48 Data Gb tim.o [1] +htim11 0x2000'7a78 0x48 Data Gb tim.o [1] +htim13 0x2000'7ac0 0x48 Data Gb tim.o [1] +htim14 0x2000'7b08 0x48 Data Gb tim.o [1] +htim2 0x2000'79a0 0x48 Data Gb tim.o [1] +htim6 0x2000'79e8 0x48 Data Gb tim.o [1] +huart1 0x2000'7b50 0x48 Data Gb usart.o [1] +log_write_index 0x2000'7c48 0x2 Data Gb modbus_log.o [1] +main 0x800'34f5 0x58 Code Gb main.o [1] +memset 0x800'55a1 0x14 Code Gb memset.o [4] modbus_logs 0x2000'5dfc 0x400 Data Gb modbus_log.o [1] -s_act_time_counter 0x2000'7be0 0x4 Data Lc tim.o [1] -s_act_time_flag 0x2000'7c43 0x1 Data Lc tim.o [1] -s_act_time_target 0x2000'7be4 0x4 Data Lc tim.o [1] +s_act_time_counter 0x2000'7bf4 0x4 Data Lc tim.o [1] +s_act_time_flag 0x2000'7c5b 0x1 Data Lc tim.o [1] +s_act_time_target 0x2000'7bf8 0x4 Data Lc tim.o [1] +s_last_total_pulse 0x2000'7c00 0x4 Data Lc tim.o [1] s_tim6_update_freq_us 0x2000'000c 0x4 Data Lc tim.o [1] -s_wait_time_counter 0x2000'7bd8 0x4 Data Lc tim.o [1] -s_wait_time_flag 0x2000'7c42 0x1 Data Lc tim.o [1] -s_wait_time_target 0x2000'7bdc 0x4 Data Lc tim.o [1] -usart1_dma_rx_buffer 0x2000'7410 0x100 Data Gb usart.o [1] -usart1_dma_rx_len 0x2000'7c3e 0x2 Data Gb usart.o [1] -usart1_dma_tx_buffer 0x2000'7510 0x100 Data Gb usart.o [1] -usart1_rx_buffer 0x2000'7310 0x100 Data Gb usart.o [1] -usart1_rx_head 0x2000'7c38 0x2 Data Gb usart.o [1] -usart1_rx_tail 0x2000'7c3a 0x2 Data Gb usart.o [1] -usart1_tx_busy 0x2000'7c4f 0x1 Data Gb usart.o [1] -uwTick 0x2000'7bd4 0x4 Data Gb stm32f4xx_hal.o [1] +s_wait_time_counter 0x2000'7bec 0x4 Data Lc tim.o [1] +s_wait_time_flag 0x2000'7c5a 0x1 Data Lc tim.o [1] +s_wait_time_target 0x2000'7bf0 0x4 Data Lc tim.o [1] +usart1_dma_rx_buffer 0x2000'7420 0x100 Data Gb usart.o [1] +usart1_dma_rx_len 0x2000'7c56 0x2 Data Gb usart.o [1] +usart1_dma_tx_buffer 0x2000'7520 0x100 Data Gb usart.o [1] +usart1_rx_buffer 0x2000'7320 0x100 Data Gb usart.o [1] +usart1_rx_head 0x2000'7c50 0x2 Data Gb usart.o [1] +usart1_rx_tail 0x2000'7c52 0x2 Data Gb usart.o [1] +usart1_tx_busy 0x2000'7c67 0x1 Data Gb usart.o [1] +uwTick 0x2000'7be4 0x4 Data Gb stm32f4xx_hal.o [1] uwTickPrio 0x2000'0004 0x4 Data Gb stm32f4xx_hal.o [1] @@ -968,9 +968,9 @@ uwTickPrio 0x2000'0004 0x4 Data Gb stm32f4xx_hal.o [1] [4] = rt7M_tl.a [5] = shb_l.a - 26'028 bytes of readonly code memory + 26'080 bytes of readonly code memory 1'056 bytes of readonly data memory - 35'920 bytes of readwrite data memory + 35'944 bytes of readwrite data memory Errors: none Warnings: none diff --git a/PLSR/PLSR/EWARM/test.1/Obj/.ninja_log b/PLSR/PLSR/EWARM/test.1/Obj/.ninja_log index d1f0d74..7bf02c6 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/.ninja_log +++ b/PLSR/PLSR/EWARM/test.1/Obj/.ninja_log @@ -1,63 +1,189 @@ # ninja log v5 -2386 2550 7765944093266374 stm32f4xx_ll_rng.pbi 5e12b9ea00d0b826 -2623 2823 7765944095613336 stm32f4xx_ll_gpio.pbi df8b54563945d41d -1380 1740 7765944085304247 stm32f4xx_hal_flash_ex.pbi ac2d035774fe6a2e -2290 2697 7765944094956311 stm32f4xx_hal_pwr.pbi b347497fce55b6a8 -2592 2622 7765944094204558 stm32f4xx_ll_pwr.pbi 952cb4e4f4edb65b -1740 1773 7765944085671831 stm32f4xx_ll_tim.pbi b88554c6464192f5 -1353 1385 7765944081838449 test.1_part7.pbi 67c64030b23c9b51 -2898 3414 7765944102128366 test.1_part3.pbi 2c7780fc3f88c160 -1304 1667 7765944084550493 stm32f4xx_hal_rcc_ex.pbi c1d751d24d77a2df -2101 2274 7765944090683100 app_hooks.pbi ffd399489d189d5a -2103 2189 7765944089538184 os_cpu_c.pbi eb75b848b406ea34 -2614 2898 7765944096933757 stm32f4xx_hal_pwr_ex.pbi b84426bf5a4ce0cf -2868 3348 7765944101394896 test.1_part4.pbi b15d70d6e2dea5ca -2310 2613 7765944094111527 stm32f4xx_hal_rcc.pbi 50976e6b18f3b8bc -1385 1737 7765944085161127 stm32f4xx_hal_usart.pbi b368fafd8b8b8bb9 -2369 2868 7765944096522356 stm32f4xx_hal_tim.pbi 71840baae88d57c4 -2501 2553 7765944093276625 stm32f4xx_ll_dac.pbi 7dfc4be0933cdfaf +4767 4926 7767835434958052 stm32f4xx_ll_rng.pbi 5e12b9ea00d0b826 +4555 4667 7767835432804228 stm32f4xx_ll_gpio.pbi df8b54563945d41d +1234 2065 7767835406698751 stm32f4xx_hal_flash_ex.pbi ac2d035774fe6a2e +1787 2579 7767835411767872 stm32f4xx_hal_pwr.pbi b347497fce55b6a8 +4999 5079 7767835437182687 stm32f4xx_ll_pwr.pbi 952cb4e4f4edb65b +4771 4948 7767835434863716 stm32f4xx_ll_tim.pbi b88554c6464192f5 +44 76 7767844460870080 test.1_part7.pbi 67c64030b23c9b51 +5088 5838 7767835443706126 test.1_part3.pbi 2c7780fc3f88c160 +1905 2614 7767835412473011 stm32f4xx_hal_rcc_ex.pbi c1d751d24d77a2df +4976 5091 7767835437419526 app_hooks.pbi ffd399489d189d5a +4667 4774 7767835434305012 os_cpu_c.pbi eb75b848b406ea34 +4058 4770 7767835434205007 stm32f4xx_hal_pwr_ex.pbi b84426bf5a4ce0cf +5100 5839 7767835443403395 test.1_part4.pbi b15d70d6e2dea5ca +1934 2588 7767835412443012 stm32f4xx_hal_rcc.pbi 50976e6b18f3b8bc +1238 2096 7767835406598753 stm32f4xx_hal_usart.pbi b368fafd8b8b8bb9 +4303 5042 7767835436884442 stm32f4xx_hal_tim.pbi 71840baae88d57c4 +1023 1210 7767835398409615 stm32f4xx_ll_dac.pbi 7dfc4be0933cdfaf 2014 2487 7762488664073707 uart.pbi 5ce52444157923c9 -3862 5441 7765944122073337 test.1.pbw f11e09b552b4c82f -2274 2310 7765944091071942 stm32f4xx_ll_crc.pbi dcf41d4b97590765 -1737 1771 7765944085641834 stm32f4xx_ll_rcc.pbi fb9ace481decf8ab -2189 2249 7765944090156714 stm32f4xx_ll_spi.pbi ce805017b70a4f43 -422 906 7765944076954791 stm32f4xx_hal_msp.pbi 8144db72f01a260b -1771 1964 7765944087093658 stm32f4xx_ll_usart.pbi 783190689e783d9 -2249 2324 7765944091181946 os_dbg.pbi f7287a072fe86a55 -2324 2500 7765944092643679 stm32f4xx_ll_dma.pbi f9e6142ede2883b4 -45 424 7765944071933926 stm32f4xx_hal_crc.pbi 881b29e4c80746b3 -2553 2595 7765944093801880 stm32f4xx_ll_exti.pbi 883a2fd463949e02 -1213 1352 7765944081467551 ucos_ii.pbi 4e0ab25e0060431e -2823 2852 7765944096324667 test.1_part5.pbi 41f12be61ce67c27 -2141 2277 7765944090752286 stm32f4xx_ll_i2c.pbi 7f1151d8874c40c9 -39 518 7765944073106678 stm32f4xx_hal.pbi a073c739b6b34173 -1774 2103 7765944088941230 stm32f4xx_hal_sram.pbi 4652c5af4efd4e19 -2550 2592 7765944093722798 test.1_part6.pbi b9d684e502f25afa -2595 2999 7765944097872088 stm32f4xx_hal_flash.pbi eccf13860e1d0c6a -1965 2369 7765944091278927 stm32f4xx_hal_tim_ex.pbi 3c68a2e86514987f -1667 2100 7765944088871009 stm32f4xx_hal_wwdg.pbi fca2b44f67349f99 -2043 2386 7765944091674121 stm32f4xx_hal_flash_ramfunc.pbi ae498685b336a49c -1307 1797 7765944085944433 stm32f4xx_hal_uart.pbi e7ca7ebbb4330340 +1289 2915 7767844533652075 test.1.pbw f11e09b552b4c82f +2589 2685 7767835413303006 stm32f4xx_ll_crc.pbi dcf41d4b97590765 +4949 4994 7767835436513283 stm32f4xx_ll_rcc.pbi fb9ace481decf8ab +4942 4998 7767835436523288 stm32f4xx_ll_spi.pbi ce805017b70a4f43 +2689 3355 7767835419967099 stm32f4xx_hal_msp.pbi 8144db72f01a260b +4994 5087 7767835437152692 stm32f4xx_ll_usart.pbi 783190689e783d9 +4774 4976 7767835435913382 os_dbg.pbi f7287a072fe86a55 +4660 4759 7767835433865005 stm32f4xx_ll_dma.pbi f9e6142ede2883b4 +3361 4321 7767835429411355 stm32f4xx_hal_crc.pbi 881b29e4c80746b3 +4425 4558 7767835431854223 stm32f4xx_ll_exti.pbi 883a2fd463949e02 +5042 5231 7767835438875219 ucos_ii.pbi 4e0ab25e0060431e +5079 5100 7767835437589708 test.1_part5.pbi 41f12be61ce67c27 +4559 4660 7767835432874226 stm32f4xx_ll_i2c.pbi 7f1151d8874c40c9 +4321 5004 7767835436058771 stm32f4xx_hal.pbi a073c739b6b34173 +1774 2487 7767835410992837 stm32f4xx_hal_sram.pbi 4652c5af4efd4e19 +5092 5132 7767835437946959 test.1_part6.pbi b9d684e502f25afa +5005 5478 7767835440883301 stm32f4xx_hal_flash.pbi eccf13860e1d0c6a +1928 2817 7767835413863004 stm32f4xx_hal_tim_ex.pbi 3c68a2e86514987f +2580 3290 7767835419165045 stm32f4xx_hal_wwdg.pbi fca2b44f67349f99 +3371 4302 7767835429421351 stm32f4xx_hal_flash_ramfunc.pbi ae498685b336a49c +4392 5083 7767835437212689 stm32f4xx_hal_uart.pbi e7ca7ebbb4330340 35 454 7762489045860992 timer.pbi 8f8acc6a162957f -2278 2682 7765944094792178 stm32f4xx_hal_i2c.pbi 74395538aa12fa10 -34 421 7765944071873918 stm32f4xx_hal_dma.pbi 2d6aa8f3983bf80a -43 533 7765944073230826 stm32f4xx_hal_timebase_tim.pbi b6f5ce0feaca8054 -1968 2290 7765944090871643 stm32f4xx_hal_i2c_ex.pbi 7798e48f8e6ef374 -425 808 7765944076026173 stm32f4xx_hal_dma_ex.pbi 1960c5ab56ffede7 -591 1022 7765944078180586 main.pbi 9c0a6aa02351636a -518 889 7765944076803026 stm32f4xx_hal_exti.pbi 373789209d565f00 -37 591 7765944073639492 stm32f4xx_it.pbi d01766022cb163bc -1023 1380 7765944081780211 stm32f4xx_hal_cortex.pbi 2c6d2473a153fb5a -929 1307 7765944080920020 system_stm32f4xx.pbi f50e519d7e78a5de -539 925 7765944077106476 gpio.pbi a088b5271f02118a -1797 2140 7765944089172990 stm32f4xx_hal_gpio.pbi 53b438f48be9a8d0 -1371 1968 7765944087547595 test.1_part0.pbi 60db414ccd7a80f4 -3523 3861 7765944106600045 test.1.pbd 363d5d355a216cdf -1441 2042 7765944088290296 test.1_part1.pbi 72148e63fe682e2f -3000 3523 7765944103216549 test.1_part2.pbi 932c7a5b50912170 -41 538 7765944073337308 dma.pbi 4f5ebe00ac67ed57 -925 1440 7765944082259040 tim.pbi f07c6d790a519d93 -906 1303 7765944080900017 usart.pbi 7c2d93866867ab60 -808 1212 7765944079931957 modbus_log.pbi 596603da5f343c45 -534 928 7765944077266980 flash_save.pbi dc7405226be28cc6 -890 1370 7765944081683497 modbus_crc.pbi 9b76681ddf289794 +3603 4555 7767835431904229 stm32f4xx_hal_i2c.pbi 74395538aa12fa10 +4325 4996 7767835436138778 stm32f4xx_hal_dma.pbi 2d6aa8f3983bf80a +4435 5010 7767835436513283 stm32f4xx_hal_timebase_tim.pbi b6f5ce0feaca8054 +2065 2688 7767835413463010 stm32f4xx_hal_i2c_ex.pbi 7798e48f8e6ef374 +4584 5198 7767835438246980 stm32f4xx_hal_dma_ex.pbi 1960c5ab56ffede7 +3815 4779 7767835433525003 main.pbi 9c0a6aa02351636a +4779 5351 7767835439405221 stm32f4xx_hal_exti.pbi 373789209d565f00 +3602 4584 7767835431714228 stm32f4xx_it.pbi d01766022cb163bc +4298 4980 7767835436038769 stm32f4xx_hal_cortex.pbi 2c6d2473a153fb5a +2608 3310 7767835419035049 system_stm32f4xx.pbi f50e519d7e78a5de +3322 4316 7767835428621181 gpio.pbi a088b5271f02118a +3583 4418 7767835430722601 stm32f4xx_hal_gpio.pbi 53b438f48be9a8d0 +39 575 7767844465868878 test.1_part0.pbi 60db414ccd7a80f4 +931 1289 7767844517715003 test.1.pbd 363d5d355a216cdf +413 931 7767844514138860 test.1_part1.pbi 72148e63fe682e2f +5083 5839 7767835443556111 test.1_part2.pbi 932c7a5b50912170 +4997 5478 7767835440883301 dma.pbi 4f5ebe00ac67ed57 +32 412 7767844508935282 tim.pbi f07c6d790a519d93 +4317 5007 7767835436473285 usart.pbi 7c2d93866867ab60 +2706 3396 7767835420017094 modbus_log.pbi 596603da5f343c45 +5008 5479 7767835441013301 flash_save.pbi dc7405226be28cc6 +3356 4391 7767835430536683 modbus_crc.pbi 9b76681ddf289794 +34 375 7767848834862657 tim.pbi f07c6d790a519d93 +375 887 7767848840002783 test.1_part1.pbi 72148e63fe682e2f +888 1233 7767848843454639 test.1.pbd 363d5d355a216cdf +1233 2963 7767848860403029 test.1.pbw f11e09b552b4c82f +37 1824 7767848870287609 test.1.pbw f11e09b552b4c82f +48 502 7767851581061459 tim.pbi f07c6d790a519d93 +503 1097 7767851586974669 test.1_part1.pbi 72148e63fe682e2f +1098 1515 7767851591204373 test.1.pbd 363d5d355a216cdf +1516 3215 7767851607856914 test.1.pbw f11e09b552b4c82f +34 378 7767854717057913 tim.pbi f07c6d790a519d93 +379 998 7767854723263845 test.1_part1.pbi 72148e63fe682e2f +999 1382 7767854727106953 test.1.pbd 363d5d355a216cdf +1383 3042 7767854743344855 test.1.pbw f11e09b552b4c82f +43 502 7767854976396779 tim.pbi f07c6d790a519d93 +503 1027 7767854981666205 test.1_part1.pbi 72148e63fe682e2f +1028 1461 7767854985998680 test.1.pbd 363d5d355a216cdf +1461 3119 7767855002150941 test.1.pbw f11e09b552b4c82f +38 599 7767861913168639 tim.pbi f07c6d790a519d93 +599 1145 7767861918653876 test.1_part1.pbi 72148e63fe682e2f +1146 1578 7767861922963295 test.1.pbd 363d5d355a216cdf +1579 3330 7767861940150154 test.1.pbw f11e09b552b4c82f +34 582 7767862030566359 tim.pbi f07c6d790a519d93 +582 1164 7767862036401525 test.1_part1.pbi 72148e63fe682e2f +1165 1509 7767862039847503 test.1.pbd 363d5d355a216cdf +1510 3113 7767862055544624 test.1.pbw f11e09b552b4c82f +38 415 7767862123121697 tim.pbi f07c6d790a519d93 +415 953 7767862128510888 test.1_part1.pbi 72148e63fe682e2f +954 1348 7767862132441369 test.1.pbd 363d5d355a216cdf +1348 3026 7767862148901230 test.1.pbw f11e09b552b4c82f +42 433 7767862215842590 tim.pbi f07c6d790a519d93 +46 441 7767862215942593 main.pbi 9c0a6aa02351636a +442 1096 7767862222181442 test.1_part0.pbi 60db414ccd7a80f4 +435 1096 7767862222209212 test.1_part1.pbi 72148e63fe682e2f +1097 1471 7767862226252981 test.1.pbd 363d5d355a216cdf +1471 3069 7767862241893293 test.1.pbw f11e09b552b4c82f +38 528 7767862310649184 tim.pbi f07c6d790a519d93 +42 616 7767862311585879 main.pbi 9c0a6aa02351636a +529 1154 7767862316943279 test.1_part1.pbi 72148e63fe682e2f +617 1232 7767862317753646 test.1_part0.pbi 60db414ccd7a80f4 +1233 1623 7767862321653043 test.1.pbd 363d5d355a216cdf +1623 3885 7767862343295112 test.1.pbw f11e09b552b4c82f +34 501 7767864389381869 tim.pbi f07c6d790a519d93 +501 1043 7767864395018608 test.1_part1.pbi 72148e63fe682e2f +1043 1394 7767864398533612 test.1.pbd 363d5d355a216cdf +1395 3032 7767864414574434 test.1.pbw f11e09b552b4c82f +36 530 7767866397883363 tim.pbi f07c6d790a519d93 +531 1089 7767866403489386 test.1_part1.pbi 72148e63fe682e2f +1090 1525 7767866407781365 test.1.pbd 363d5d355a216cdf +1525 3197 7767866424243238 test.1.pbw f11e09b552b4c82f +65 526 7767866863425178 tim.pbi f07c6d790a519d93 +526 1116 7767866869348127 test.1_part1.pbi 72148e63fe682e2f +1117 1488 7767866873053748 test.1.pbd 363d5d355a216cdf +1488 3247 7767866890291338 test.1.pbw f11e09b552b4c82f +34 368 7767871806405189 tim.pbi f07c6d790a519d93 +369 895 7767871811678325 test.1_part1.pbi 72148e63fe682e2f +895 1301 7767871815746609 test.1.pbd 363d5d355a216cdf +1302 3017 7767871832550389 test.1.pbw f11e09b552b4c82f +33 384 7767872331001568 tim.pbi f07c6d790a519d93 +385 895 7767872336116503 test.1_part1.pbi 72148e63fe682e2f +895 1239 7767872339558893 test.1.pbd 363d5d355a216cdf +1240 2836 7767872355208372 test.1.pbw f11e09b552b4c82f +33 519 7767874457100008 tim.pbi f07c6d790a519d93 +519 1051 7767874462426271 test.1_part1.pbi 72148e63fe682e2f +1051 1397 7767874465887342 test.1.pbd 363d5d355a216cdf +1398 3003 7767874481618426 test.1.pbw f11e09b552b4c82f +89 448 7767875825003044 tim.pbi f07c6d790a519d93 +448 1001 7767875830463256 test.1_part1.pbi 72148e63fe682e2f +1001 1379 7767875834310759 test.1.pbd 363d5d355a216cdf +1379 3010 7767875850284017 test.1.pbw f11e09b552b4c82f +37 419 7767875918017364 tim.pbi f07c6d790a519d93 +420 983 7767875923682095 test.1_part1.pbi 72148e63fe682e2f +984 1345 7767875927299835 test.1.pbd 363d5d355a216cdf +1346 3044 7767875943924901 test.1.pbw f11e09b552b4c82f +37 536 7767880075843740 tim.pbi f07c6d790a519d93 +537 1203 7767880082530092 test.1_part1.pbi 72148e63fe682e2f +1203 1662 7767880087051855 test.1.pbd 363d5d355a216cdf +1663 3930 7767880109363208 test.1.pbw f11e09b552b4c82f +35 378 7767880135836352 tim.pbi f07c6d790a519d93 +378 894 7767880141005386 test.1_part1.pbi 72148e63fe682e2f +894 1255 7767880144594346 test.1.pbd 363d5d355a216cdf +1255 2962 7767880161327589 test.1.pbw f11e09b552b4c82f +74 749 7767880420743454 tim.pbi f07c6d790a519d93 +749 1611 7767880429670146 test.1_part1.pbi 72148e63fe682e2f +1612 2209 7767880435419817 test.1.pbd 363d5d355a216cdf +2210 4842 7767880461686164 test.1.pbw f11e09b552b4c82f +53 75 7767880525166885 test.1_part5.pbi 5e6bb6746ac1a79 +42 119 7767880525523636 test.1_part6.pbi 9b20b344c2a6a660 +45 585 7767880529882349 test.1_part4.pbi e782621ef28d0d79 +34 637 7767880530793985 test.1_part3.pbi b2579812bd284519 +49 676 7767880531192810 test.1_part2.pbi 727e15cce45b2bf7 +38 676 7767880531202810 test.1_part1.pbi 987246192c88859e +677 1036 7767880534807624 test.1.pbd dd3dd60110e24e1b +1037 2696 7767880551066013 test.1.pbw f11e09b552b4c82f +37 61 7767881169681325 test.1_part5.pbi 41f12be61ce67c27 +33 65 7767881169801326 test.1_part6.pbi b9d684e502f25afa +51 88 7767881170031324 tim.pbi f07c6d790a519d93 +46 589 7767881174894004 test.1_part4.pbi b15d70d6e2dea5ca +88 590 7767881175000430 test.1_part1.pbi 72148e63fe682e2f +42 616 7767881175325403 test.1_part2.pbi 932c7a5b50912170 +40 617 7767881175315402 test.1_part3.pbi 2c7780fc3f88c160 +618 1047 7767881179015437 test.1.pbd 363d5d355a216cdf +1047 2701 7767881195807140 test.1.pbw f11e09b552b4c82f +33 361 7767881221918304 tim.pbi f07c6d790a519d93 +362 884 7767881227146552 test.1_part1.pbi 72148e63fe682e2f +885 1227 7767881230583622 test.1.pbd 363d5d355a216cdf +1228 2906 7767881247005815 test.1.pbw f11e09b552b4c82f +31 402 7767883021415575 tim.pbi f07c6d790a519d93 +402 967 7767883026832538 test.1_part1.pbi 72148e63fe682e2f +967 1307 7767883030483551 test.1.pbd 363d5d355a216cdf +1308 3147 7767883048508629 test.1.pbw f11e09b552b4c82f +32 370 7767883074669200 tim.pbi f07c6d790a519d93 +370 880 7767883079774832 test.1_part1.pbi 72148e63fe682e2f +881 1225 7767883083229165 test.1.pbd 363d5d355a216cdf +1226 2778 7767883098434294 test.1.pbw f11e09b552b4c82f +35 576 7767890420310004 tim.pbi f07c6d790a519d93 +577 1140 7767890425948977 test.1_part1.pbi 72148e63fe682e2f +1140 1607 7767890430389486 test.1.pbd 363d5d355a216cdf +1608 3556 7767890449659399 test.1.pbw f11e09b552b4c82f +34 484 7767890477240811 tim.pbi f07c6d790a519d93 +485 1001 7767890482412228 test.1_part1.pbi 72148e63fe682e2f +1002 1360 7767890485984522 test.1.pbd 363d5d355a216cdf +1361 2958 7767890501636719 test.1.pbw f11e09b552b4c82f +46 486 7767895482702468 tim.pbi f07c6d790a519d93 +487 1131 7767895489276317 test.1_part1.pbi 72148e63fe682e2f +1132 1494 7767895492915996 test.1.pbd 363d5d355a216cdf +1494 3288 7767895510332329 test.1.pbw f11e09b552b4c82f diff --git a/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.o b/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.o index b8cba46..a2fe6a5 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.o and b/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.pbi b/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.pbi index 0c97fe1..623db97 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/app_hooks.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/dma.o b/PLSR/PLSR/EWARM/test.1/Obj/dma.o index 374ed01..b15bb17 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/dma.o and b/PLSR/PLSR/EWARM/test.1/Obj/dma.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/gpio.o b/PLSR/PLSR/EWARM/test.1/Obj/gpio.o index 6cda1a5..e41a35e 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/gpio.o and b/PLSR/PLSR/EWARM/test.1/Obj/gpio.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/gpio.pbi b/PLSR/PLSR/EWARM/test.1/Obj/gpio.pbi index b4b5c04..0781528 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/gpio.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/gpio.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/main.o b/PLSR/PLSR/EWARM/test.1/Obj/main.o index 8ee809b..4b2e9e0 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/main.o and b/PLSR/PLSR/EWARM/test.1/Obj/main.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/main.pbi b/PLSR/PLSR/EWARM/test.1/Obj/main.pbi index 4549ac4..6819b5a 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/main.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/main.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/main.pbi.dep b/PLSR/PLSR/EWARM/test.1/Obj/main.pbi.dep index c0ab4a4..1ffeecf 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/main.pbi.dep +++ b/PLSR/PLSR/EWARM/test.1/Obj/main.pbi.dep @@ -1,54 +1,60 @@ main.pbi: \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\dma.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\usart.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\modbus_log.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\flash_save.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\modbus_crc.h \ - E:\Software\IAR\arm\inc\c\DLib_Product_stdlib.h \ - E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\stdlib.h \ - E:\Software\IAR\arm\inc\c\ctype.h \ - E:\Software\IAR\arm\inc\c\DLib_Product_string.h \ - E:\Software\IAR\arm\inc\c\string.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\tim.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\os_trace.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Ports\os_cpu.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ - E:\Software\IAR\arm\inc\c\stdio.h E:\Software\IAR\arm\inc\c\stdarg.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\gpio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ - E:\Software\IAR\arm\inc\c\ysizet.h E:\Software\IAR\arm\inc\c\stddef.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\mpu_armv7.h \ - E:\Software\IAR\arm\inc\c\iccarm_builtin.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_iccarm.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_compiler.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_version.h \ - E:\Software\IAR\arm\inc\c\DLib_Product.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Core\Src\main.c \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\main.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\stm32f4xx_hal_conf.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_rcc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include\stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\core_cm4.h \ + E:\Software\IAR\arm\inc\c\stdint.h E:\Software\IAR\arm\inc\c\ycheck.h \ + E:\Software\IAR\arm\inc\c\yvals.h \ E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ - E:\Software\IAR\arm\inc\c\yvals.h E:\Software\IAR\arm\inc\c\stdint.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\core_cm4.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\stm32f4xx_hal_conf.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\main.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Core\Src\main.c + E:\\Software\\IAR\\arm\\inc\\c\\DLib_Config_Full.h \ + E:\Software\IAR\arm\inc\c\DLib_Product.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_version.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_compiler.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\cmsis_iccarm.h \ + E:\Software\IAR\arm\inc\c\iccarm_builtin.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/mpu_armv7.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + E:\Software\IAR\arm\inc\c\stddef.h E:\Software\IAR\arm\inc\c\ysizet.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_gpio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_exti.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_dma.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_cortex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_flash.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_pwr.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_tim.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_uart.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\gpio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/main.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ + E:\Software\IAR\arm\inc\c\stdarg.h E:\Software\IAR\arm\inc\c\stdio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Ports\os_cpu.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source/os_trace.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\tim.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/usart.h \ + E:\Software\IAR\arm\inc\c\string.h \ + E:\Software\IAR\arm\inc\c\DLib_Product_string.h \ + E:\Software\IAR\arm\inc\c\ctype.h E:\Software\IAR\arm\inc\c\stdlib.h \ + E:\Software\IAR\arm\inc\c\DLib_Product_stdlib.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/modbus_crc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/flash_save.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/modbus_log.h \ + E:\Software\IAR\arm\inc\c\math.h \ + E:\Software\IAR\arm\inc\c\DLib_float_setup.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\usart.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\dma.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\flash_save.h diff --git a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_a.o b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_a.o index d3835ed..a3ef6fe 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_a.o and b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_a.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.o b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.o index 19546f6..93c4485 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.o and b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi index 4b6a9db..57dc6ef 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi.dep b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi.dep index f5310bb..9ed5b97 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi.dep +++ b/PLSR/PLSR/EWARM/test.1/Obj/os_cpu_c.pbi.dep @@ -1,13 +1,12 @@ os_cpu_c.pbi: \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\UCOS\Ports\os_cpu_c.c \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ - E:\Software\IAR\arm\inc\c\stdarg.h E:\Software\IAR\arm\inc\c\stdio.h \ - E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\yvals.h \ - E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ - E:\\Software\\IAR\\arm\\inc\\c\\DLib_Config_Full.h \ - E:\Software\IAR\arm\inc\c\DLib_Product.h \ - E:\Software\IAR\arm\inc\c\ysizet.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\os_trace.h \ e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\UCOS\Ports\os_cpu.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source/os_trace.h + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ + E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\ysizet.h \ + E:\Software\IAR\arm\inc\c\DLib_Product.h \ + E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ + E:\Software\IAR\arm\inc\c\yvals.h E:\Software\IAR\arm\inc\c\stdio.h \ + E:\Software\IAR\arm\inc\c\stdarg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\UCOS\Ports\os_cpu_c.c diff --git a/PLSR/PLSR/EWARM/test.1/Obj/os_dbg.o b/PLSR/PLSR/EWARM/test.1/Obj/os_dbg.o index 708b19e..7735ac5 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/os_dbg.o and b/PLSR/PLSR/EWARM/test.1/Obj/os_dbg.o differ diff --git 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diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_crc.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_crc.o index 93c21a1..4edf370 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_crc.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_crc.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma.o index f8ed6e4..79b5c25 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma_ex.o index a27395f..dcfb964 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_dma_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_exti.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_exti.o index 1928d74..a348e8c 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_exti.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_exti.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash.o index 5b62be0..944cb90 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ex.o index 80d84ef..a9f7c20 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ramfunc.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ramfunc.o index 3920c83..b492e79 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ramfunc.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_gpio.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_gpio.o index aa2180f..83dc325 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_gpio.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_gpio.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c.o index 15c8a5e..493dfc1 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c_ex.o index 758d3b1..a627f8d 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_i2c_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_msp.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_msp.o index c74b7a6..dd84612 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_msp.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_msp.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr.o index 71eb9dc..f57d9f7 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr_ex.o index 4fe3953..bb26b2a 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_pwr_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc.o index c64c23a..c6e28c5 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc_ex.o index e71248f..8fda666 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_rcc_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_sram.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_sram.o index 46a0580..e325a53 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_sram.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_sram.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.o index c6f0c41..22a2642 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.pbi.dep b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.pbi.dep index a57293d..a8229e1 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.pbi.dep +++ b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim.pbi.dep @@ -1,37 +1,36 @@ stm32f4xx_hal_tim.pbi: \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\stm32f4xx_hal_conf.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_rcc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include\stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\core_cm4.h \ - E:\Software\IAR\arm\inc\c\stdint.h E:\Software\IAR\arm\inc\c\ycheck.h \ - E:\Software\IAR\arm\inc\c\yvals.h \ - E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ - E:\\Software\\IAR\\arm\\inc\\c\\DLib_Config_Full.h \ - E:\Software\IAR\arm\inc\c\DLib_Product.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_version.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_compiler.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\cmsis_iccarm.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\ysizet.h \ + E:\Software\IAR\arm\inc\c\stddef.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\mpu_armv7.h \ E:\Software\IAR\arm\inc\c\iccarm_builtin.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/mpu_armv7.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - E:\Software\IAR\arm\inc\c\stddef.h E:\Software\IAR\arm\inc\c\ysizet.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_gpio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_exti.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_dma.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_cortex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_flash.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_pwr.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_tim.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_uart.h + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_iccarm.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_compiler.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_version.h \ + E:\Software\IAR\arm\inc\c\DLib_Product.h \ + E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ + E:\Software\IAR\arm\inc\c\yvals.h E:\Software\IAR\arm\inc\c\stdint.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\core_cm4.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\stm32f4xx_hal_conf.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim_ex.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim_ex.o index 61d6977..fc408b9 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim_ex.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_tim_ex.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_timebase_tim.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_timebase_tim.o index 7f7da2b..4e3054e 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_timebase_tim.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_timebase_tim.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_uart.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_uart.o index 10d5119..71739f0 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_uart.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_uart.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_usart.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_usart.o index 3c0dc61..2e0fef5 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_usart.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_usart.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_wwdg.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_wwdg.o index 4cb1f50..c9c5c1d 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_wwdg.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_hal_wwdg.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.o b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.o index 97367d0..0afd63d 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.o and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi index 5a0f249..ae58400 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi.dep b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi.dep index d68d6ca..544ee80 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi.dep +++ b/PLSR/PLSR/EWARM/test.1/Obj/stm32f4xx_it.pbi.dep @@ -1,45 +1,44 @@ stm32f4xx_it.pbi: \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Core\Src\stm32f4xx_it.c \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\main.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\stm32f4xx_hal_conf.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_rcc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include\stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\core_cm4.h \ - E:\Software\IAR\arm\inc\c\stdint.h E:\Software\IAR\arm\inc\c\ycheck.h \ - E:\Software\IAR\arm\inc\c\yvals.h \ - E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ - E:\\Software\\IAR\\arm\\inc\\c\\DLib_Config_Full.h \ - E:\Software\IAR\arm\inc\c\DLib_Product.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_version.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_compiler.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\cmsis_iccarm.h \ - E:\Software\IAR\arm\inc\c\iccarm_builtin.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/mpu_armv7.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - E:\Software\IAR\arm\inc\c\stddef.h E:\Software\IAR\arm\inc\c\ysizet.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_gpio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_exti.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_dma.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_cortex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_flash.h \ - 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e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ - E:\Software\IAR\arm\inc\c\stdarg.h E:\Software\IAR\arm\inc\c\stdio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\os_trace.h \ e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Ports\os_cpu.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source/os_trace.h + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\os_cfg.h \ + E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\stdio.h \ + E:\Software\IAR\arm\inc\c\stdarg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Config\app_cfg.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\UCOS\Source\ucos_ii.h \ + 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"c:stm32f4xx_hal_rcc.h@779@macro@__STM32F4xx_HAL_RCC_H", + "ID": "c:stm32f4xx_hal_tim.h@781@macro@STM32F4xx_HAL_TIM_H", "What": "MacroDef", "defdec": "Def", - "display": "__STM32F4xx_HAL_RCC_H", + "display": "STM32F4xx_HAL_TIM_H", "location": { "column": "9", - "line": "20", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "21", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "__STM32F4xx_HAL_RCC_H", + "name": "STM32F4xx_HAL_TIM_H", "origin": "user_include", "scope": null }, { - "ID": "c:@SA@RCC_OscInitTypeDef", + "ID": "c:@SA@TIM_Base_InitTypeDef", "What": "Struct", "defdec": "Def", "display": "", "location": { "column": "9", - "line": "49", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "46", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, "members": [ { - "ID": "c:@SA@RCC_OscInitTypeDef@FI@OscillatorType", + "ID": "c:@SA@TIM_Base_InitTypeDef@FI@Prescaler", "What": "FieldDecl", "defdec": "Def", - "display": "OscillatorType", + "display": "Prescaler", + "location": { + "column": "12", + "line": "48", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" + }, + "name": "Prescaler", + "origin": "user_include", + "scope": "_anonymous_stm32f4xx_hal_tim_h_46_9" + }, + { + "ID": "c:@SA@TIM_Base_InitTypeDef@FI@CounterMode", + "What": "FieldDecl", + "defdec": "Def", + "display": "CounterMode", "location": { "column": "12", "line": "51", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "OscillatorType", + "name": "CounterMode", "origin": "user_include", - "scope": "_anonymous_stm32f4xx_hal_rcc_h_49_9" + "scope": "_anonymous_stm32f4xx_hal_tim_h_46_9" }, { - "ID": "c:@SA@RCC_OscInitTypeDef@FI@HSEState", + "ID": "c:@SA@TIM_Base_InitTypeDef@FI@Period", "What": "FieldDecl", "defdec": "Def", - "display": "HSEState", + "display": "Period", "location": { "column": "12", "line": "54", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "HSEState", + "name": "Period", "origin": "user_include", - "scope": "_anonymous_stm32f4xx_hal_rcc_h_49_9" + "scope": "_anonymous_stm32f4xx_hal_tim_h_46_9" }, { - "ID": "c:@SA@RCC_OscInitTypeDef@FI@LSEState", + "ID": "c:@SA@TIM_Base_InitTypeDef@FI@ClockDivision", "What": "FieldDecl", "defdec": "Def", - "display": "LSEState", + "display": "ClockDivision", "location": { "column": "12", - "line": "57", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "58", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "LSEState", + "name": "ClockDivision", "origin": "user_include", - "scope": "_anonymous_stm32f4xx_hal_rcc_h_49_9" + "scope": "_anonymous_stm32f4xx_hal_tim_h_46_9" }, { - "ID": "c:@SA@RCC_OscInitTypeDef@FI@HSIState", + "ID": "c:@SA@TIM_Base_InitTypeDef@FI@RepetitionCounter", "What": "FieldDecl", "defdec": "Def", - "display": "HSIState", + "display": "RepetitionCounter", "location": { "column": "12", - "line": "60", - "path": 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"What": "MacroDef", "defdec": "Def", - "display": "RCC_IT_LSIRDY", + "display": "TIM_ICPSC_DIV2", "location": { "column": "9", - "line": "326", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "643", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "RCC_IT_LSIRDY", + "name": "TIM_ICPSC_DIV2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_rcc.h@11513@macro@RCC_IT_LSERDY", + "ID": "c:stm32f4xx_hal_tim.h@34885@macro@TIM_ICPSC_DIV4", "What": "MacroDef", "defdec": "Def", - "display": "RCC_IT_LSERDY", + "display": "TIM_ICPSC_DIV4", "location": { "column": "9", - "line": "327", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "644", + "path": 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"defdec": "Def", - "display": "RCC_IT_HSERDY", + "display": "TIM_OPMODE_SINGLE", "location": { "column": "9", - "line": "329", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "653", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "RCC_IT_HSERDY", + "name": "TIM_OPMODE_SINGLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_rcc.h@11684@macro@RCC_IT_PLLRDY", + "ID": "c:stm32f4xx_hal_tim.h@35416@macro@TIM_OPMODE_REPETITIVE", "What": "MacroDef", "defdec": "Def", - "display": "RCC_IT_PLLRDY", + "display": "TIM_OPMODE_REPETITIVE", "location": { "column": "9", - "line": "330", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "654", + "path": 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}, - "name": "RCC_FLAG_BORRST", + "name": "TIM_IT_COM", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_rcc.h@12669@macro@RCC_FLAG_PINRST", + "ID": "c:stm32f4xx_hal_tim.h@37105@macro@TIM_IT_TRIGGER", "What": "MacroDef", "defdec": "Def", - "display": "RCC_FLAG_PINRST", + "display": "TIM_IT_TRIGGER", "location": { "column": "9", - "line": "358", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" + "line": "678", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "RCC_FLAG_PINRST", + "name": "TIM_IT_TRIGGER", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_rcc.h@12726@macro@RCC_FLAG_PORRST", + "ID": "c:stm32f4xx_hal_tim.h@37221@macro@TIM_IT_BREAK", "What": "MacroDef", "defdec": "Def", - "display": "RCC_FLAG_PORRST", + "display": "TIM_IT_BREAK", "location": { "column": "9", - "line": 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"c:core_cm4.h@27450@macro@SCB_CCR_STKALIGN_Msk", - "What": "MacroDef", - "defdec": "Def", - "display": "SCB_CCR_STKALIGN_Msk", + "ID": "c:@F@HAL_TIM_PeriodElapsedHalfCpltCallback", + "What": "Function", + "defdec": "Dec", + "display": "void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *)", "location": { - "column": "9", - "line": "555", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\core_cm4.h" + "column": "6", + "line": "2074", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" }, - "name": "SCB_CCR_STKALIGN_Msk", + "name": "HAL_TIM_PeriodElapsedHalfCpltCallback", "origin": "user_include", "scope": null }, { - "ID": "c:core_cm4.h@27572@macro@SCB_CCR_BFHFNMIGN_Pos", - "What": "MacroDef", - "defdec": "Def", - "display": "SCB_CCR_BFHFNMIGN_Pos", + "ID": "c:@F@HAL_TIM_PeriodElapsedHalfCpltCallback", + "What": "Function", + "defdec": "Dec", + "display": "void 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null }, { - "ID": "c:core_cm4.h@103878@macro@EXC_RETURN_THREAD_PSP_FPU", + "ID": "c:stm32_hal_legacy.h@67326@macro@TIM_DMABase_CCR1", "What": "MacroDef", "defdec": "Def", - "display": "EXC_RETURN_THREAD_PSP_FPU", + "display": "TIM_DMABase_CCR1", "location": { "column": "9", - "line": "1641", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\core_cm4.h" + "line": "1417", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "EXC_RETURN_THREAD_PSP_FPU", + "name": "TIM_DMABase_CCR1", "origin": "user_include", "scope": null }, { - "ID": "c:core_cm4.h@F@__NVIC_SetPriorityGrouping", - "What": "Function", + "ID": "c:stm32_hal_legacy.h@67384@macro@TIM_DMABase_CCR2", + "What": "MacroDef", "defdec": "Def", - "display": "void __NVIC_SetPriorityGrouping(uint32_t)", + "display": "TIM_DMABase_CCR2", "location": { - "column": "22", - "line": "1653", - "path": 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"e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "CAN_IT_RQCP1", + "name": "__FMC_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@73595@macro@CAN_IT_RQCP2", + "ID": "c:stm32_hal_legacy.h@152640@macro@__FMC_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "CAN_IT_RQCP2", + "display": "__FMC_CLK_ENABLE", "location": { "column": "9", - "line": "1565", + "line": "2863", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "CAN_IT_RQCP2", + "name": "__FMC_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@73642@macro@INAK_TIMEOUT", + "ID": "c:stm32_hal_legacy.h@152690@macro@__FMC_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "INAK_TIMEOUT", + "display": "__FMC_CLK_SLEEP_DISABLE", "location": { "column": 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"CAN_TXSTATUS_FAILED", + "display": "__FMC_FORCE_RESET", "location": { "column": "9", - "line": "1568", + "line": "2866", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "CAN_TXSTATUS_FAILED", + "name": "__FMC_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@73803@macro@CAN_TXSTATUS_OK", + "ID": "c:stm32_hal_legacy.h@152868@macro@__FMC_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "CAN_TXSTATUS_OK", + "display": "__FMC_RELEASE_RESET", "location": { "column": "9", - "line": "1569", + "line": "2867", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "CAN_TXSTATUS_OK", + "name": "__FMC_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@73856@macro@CAN_TXSTATUS_PENDING", + "ID": "c:stm32_hal_legacy.h@152924@macro@__FSMC_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "CAN_TXSTATUS_PENDING", + "display": "__FSMC_CLK_DISABLE", "location": { "column": "9", - "line": "1570", + "line": "2868", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "CAN_TXSTATUS_PENDING", + "name": "__FSMC_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74032@macro@VLAN_TAG", + "ID": "c:stm32_hal_legacy.h@152978@macro@__FSMC_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "VLAN_TAG", + "display": "__FSMC_CLK_ENABLE", "location": { "column": "9", - "line": "1580", + "line": "2869", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "VLAN_TAG", + "name": "__FSMC_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74077@macro@MIN_ETH_PAYLOAD", + "ID": "c:stm32_hal_legacy.h@153030@macro@__GPIOA_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "MIN_ETH_PAYLOAD", + "display": "__GPIOA_CLK_DISABLE", "location": { "column": "9", - "line": "1581", + "line": "2870", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "MIN_ETH_PAYLOAD", + "name": "__GPIOA_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74129@macro@MAX_ETH_PAYLOAD", + "ID": "c:stm32_hal_legacy.h@153086@macro@__GPIOA_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "MAX_ETH_PAYLOAD", + "display": "__GPIOA_CLK_ENABLE", "location": { "column": "9", - "line": "1582", + "line": "2871", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "MAX_ETH_PAYLOAD", + "name": "__GPIOA_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74181@macro@JUMBO_FRAME_PAYLOAD", + "ID": "c:stm32_hal_legacy.h@153140@macro@__GPIOA_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "JUMBO_FRAME_PAYLOAD", + "display": "__GPIOA_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1583", + "line": "2872", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "JUMBO_FRAME_PAYLOAD", + "name": "__GPIOA_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74237@macro@MACMIIAR_CR_MASK", + "ID": "c:stm32_hal_legacy.h@153208@macro@__GPIOA_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "MACMIIAR_CR_MASK", + "display": "__GPIOA_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1584", + "line": "2873", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "MACMIIAR_CR_MASK", + "name": "__GPIOA_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74290@macro@MACCR_CLEAR_MASK", + "ID": "c:stm32_hal_legacy.h@153274@macro@__GPIOA_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "MACCR_CLEAR_MASK", + "display": "__GPIOA_FORCE_RESET", "location": { "column": "9", - "line": "1585", + "line": "2874", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "MACCR_CLEAR_MASK", + "name": "__GPIOA_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74343@macro@MACFCR_CLEAR_MASK", + "ID": "c:stm32_hal_legacy.h@153330@macro@__GPIOA_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "MACFCR_CLEAR_MASK", + "display": "__GPIOA_RELEASE_RESET", "location": { "column": "9", - "line": "1586", + "line": "2875", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "MACFCR_CLEAR_MASK", + "name": "__GPIOA_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74397@macro@DMAOMR_CLEAR_MASK", + "ID": "c:stm32_hal_legacy.h@153390@macro@__GPIOB_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "DMAOMR_CLEAR_MASK", + "display": "__GPIOB_CLK_DISABLE", "location": { "column": "9", - "line": "1587", + "line": "2876", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "DMAOMR_CLEAR_MASK", + "name": "__GPIOB_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74452@macro@ETH_MMCCR", + "ID": "c:stm32_hal_legacy.h@153446@macro@__GPIOB_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCCR", + "display": "__GPIOB_CLK_ENABLE", "location": { "column": "9", - "line": "1589", + "line": "2877", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCCR", + "name": "__GPIOB_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74495@macro@ETH_MMCRIR", + "ID": "c:stm32_hal_legacy.h@153500@macro@__GPIOB_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCRIR", + "display": "__GPIOB_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1590", + "line": "2878", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCRIR", + "name": "__GPIOB_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74538@macro@ETH_MMCTIR", + "ID": "c:stm32_hal_legacy.h@153568@macro@__GPIOB_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCTIR", + "display": "__GPIOB_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1591", + "line": "2879", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCTIR", + "name": "__GPIOB_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74581@macro@ETH_MMCRIMR", + "ID": "c:stm32_hal_legacy.h@153634@macro@__GPIOB_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCRIMR", + "display": "__GPIOB_FORCE_RESET", "location": { "column": "9", - "line": "1592", + "line": "2880", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCRIMR", + "name": "__GPIOB_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74624@macro@ETH_MMCTIMR", + "ID": "c:stm32_hal_legacy.h@153690@macro@__GPIOB_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCTIMR", + "display": "__GPIOB_RELEASE_RESET", "location": { "column": "9", - "line": "1593", + "line": "2881", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCTIMR", + "name": "__GPIOB_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74667@macro@ETH_MMCTGFSCCR", + "ID": "c:stm32_hal_legacy.h@153750@macro@__GPIOC_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCTGFSCCR", + "display": "__GPIOC_CLK_DISABLE", "location": { "column": "9", - "line": "1594", + "line": "2882", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCTGFSCCR", + "name": "__GPIOC_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74710@macro@ETH_MMCTGFMSCCR", + "ID": "c:stm32_hal_legacy.h@153806@macro@__GPIOC_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCTGFMSCCR", + "display": "__GPIOC_CLK_ENABLE", "location": { "column": "9", - "line": "1595", + "line": "2883", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCTGFMSCCR", + "name": "__GPIOC_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74753@macro@ETH_MMCTGFCR", + "ID": "c:stm32_hal_legacy.h@153860@macro@__GPIOC_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCTGFCR", + "display": "__GPIOC_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1596", + "line": "2884", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCTGFCR", + "name": "__GPIOC_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74796@macro@ETH_MMCRFCECR", + "ID": "c:stm32_hal_legacy.h@153928@macro@__GPIOC_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCRFCECR", + "display": "__GPIOC_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1597", + "line": "2885", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCRFCECR", + "name": "__GPIOC_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74839@macro@ETH_MMCRFAECR", + "ID": "c:stm32_hal_legacy.h@153994@macro@__GPIOC_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCRFAECR", + "display": "__GPIOC_FORCE_RESET", "location": { "column": "9", - "line": "1598", + "line": "2886", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCRFAECR", + "name": "__GPIOC_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74882@macro@ETH_MMCRGUFCR", + "ID": "c:stm32_hal_legacy.h@154050@macro@__GPIOC_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MMCRGUFCR", + "display": "__GPIOC_RELEASE_RESET", "location": { "column": "9", - "line": "1599", + "line": "2887", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MMCRGUFCR", + "name": "__GPIOC_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@74926@macro@ETH_MAC_TXFIFO_FULL", + "ID": "c:stm32_hal_legacy.h@154110@macro@__GPIOD_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_FULL", + "display": "__GPIOD_CLK_DISABLE", "location": { "column": "9", - "line": "1601", + "line": "2888", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_FULL", + "name": "__GPIOD_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75012@macro@ETH_MAC_TXFIFONOT_EMPTY", + "ID": "c:stm32_hal_legacy.h@154166@macro@__GPIOD_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFONOT_EMPTY", + "display": "__GPIOD_CLK_ENABLE", "location": { "column": "9", - "line": "1602", + "line": "2889", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFONOT_EMPTY", + "name": "__GPIOD_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75103@macro@ETH_MAC_TXFIFO_WRITE_ACTIVE", + "ID": "c:stm32_hal_legacy.h@154220@macro@__GPIOD_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_WRITE_ACTIVE", + "display": "__GPIOD_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1603", + "line": "2890", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_WRITE_ACTIVE", + "name": "__GPIOD_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75197@macro@ETH_MAC_TXFIFO_IDLE", + "ID": "c:stm32_hal_legacy.h@154288@macro@__GPIOD_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_IDLE", + "display": "__GPIOD_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1604", + "line": "2891", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_IDLE", + "name": "__GPIOD_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75296@macro@ETH_MAC_TXFIFO_READ", + "ID": "c:stm32_hal_legacy.h@154354@macro@__GPIOD_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_READ", + "display": "__GPIOD_FORCE_RESET", "location": { "column": "9", - "line": "1605", + "line": "2892", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_READ", + "name": "__GPIOD_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75509@macro@ETH_MAC_TXFIFO_WAITING", + "ID": "c:stm32_hal_legacy.h@154410@macro@__GPIOD_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_WAITING", + "display": "__GPIOD_RELEASE_RESET", "location": { "column": "9", - "line": "1607", + "line": "2893", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_WAITING", + "name": "__GPIOD_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75716@macro@ETH_MAC_TXFIFO_WRITING", + "ID": "c:stm32_hal_legacy.h@154470@macro@__GPIOE_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TXFIFO_WRITING", + "display": "__GPIOE_CLK_DISABLE", "location": { "column": "9", - "line": "1609", + "line": "2894", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TXFIFO_WRITING", + "name": "__GPIOE_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@75933@macro@ETH_MAC_TRANSMISSION_PAUSE", + "ID": "c:stm32_hal_legacy.h@154526@macro@__GPIOE_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TRANSMISSION_PAUSE", + "display": "__GPIOE_CLK_ENABLE", "location": { "column": "9", - "line": "1611", + "line": "2895", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TRANSMISSION_PAUSE", + "name": "__GPIOE_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76031@macro@ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE", + "ID": "c:stm32_hal_legacy.h@154580@macro@__GPIOE_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE", + "display": "__GPIOE_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1612", + "line": "2896", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE", + "name": "__GPIOE_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76140@macro@ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING", + "ID": "c:stm32_hal_legacy.h@154648@macro@__GPIOE_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING", + "display": "__GPIOE_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1613", + "line": "2897", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING", + "name": "__GPIOE_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76382@macro@ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF", + "ID": "c:stm32_hal_legacy.h@154714@macro@__GPIOE_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF", + "display": "__GPIOE_FORCE_RESET", "location": { "column": "9", - "line": "1615", + "line": "2898", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF", + "name": "__GPIOE_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76620@macro@ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING", + "ID": "c:stm32_hal_legacy.h@154770@macro@__GPIOE_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING", + "display": "__GPIOE_RELEASE_RESET", "location": { "column": "9", - "line": "1617", + "line": "2899", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING", + "name": "__GPIOE_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76837@macro@ETH_MAC_MII_TRANSMIT_ACTIVE", + "ID": "c:stm32_hal_legacy.h@154830@macro@__GPIOF_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_MII_TRANSMIT_ACTIVE", + "display": "__GPIOF_CLK_DISABLE", "location": { "column": "9", - "line": "1619", + "line": "2900", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_MII_TRANSMIT_ACTIVE", + "name": "__GPIOF_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@76933@macro@ETH_MAC_RXFIFO_EMPTY", + "ID": "c:stm32_hal_legacy.h@154886@macro@__GPIOF_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_RXFIFO_EMPTY", + "display": "__GPIOF_CLK_ENABLE", "location": { "column": "9", - "line": "1620", + "line": "2901", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_RXFIFO_EMPTY", + "name": "__GPIOF_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77024@macro@ETH_MAC_RXFIFO_BELOW_THRESHOLD", + "ID": "c:stm32_hal_legacy.h@154940@macro@__GPIOF_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_RXFIFO_BELOW_THRESHOLD", + "display": "__GPIOF_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1621", + "line": "2902", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_RXFIFO_BELOW_THRESHOLD", + "name": "__GPIOF_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77224@macro@ETH_MAC_RXFIFO_ABOVE_THRESHOLD", + "ID": "c:stm32_hal_legacy.h@155008@macro@__GPIOF_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_RXFIFO_ABOVE_THRESHOLD", + "display": "__GPIOF_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1623", + "line": "2903", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_RXFIFO_ABOVE_THRESHOLD", + "name": "__GPIOF_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77421@macro@ETH_MAC_RXFIFO_FULL", + "ID": "c:stm32_hal_legacy.h@155074@macro@__GPIOF_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_RXFIFO_FULL", + "display": "__GPIOF_FORCE_RESET", "location": { "column": "9", - "line": "1625", + "line": "2904", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_RXFIFO_FULL", + "name": "__GPIOF_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77538@macro@ETH_MAC_READCONTROLLER_IDLE", + "ID": "c:stm32_hal_legacy.h@155130@macro@__GPIOF_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_READCONTROLLER_IDLE", + "display": "__GPIOF_RELEASE_RESET", "location": { "column": "9", - "line": "1628", + "line": "2905", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_READCONTROLLER_IDLE", + "name": "__GPIOF_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77638@macro@ETH_MAC_READCONTROLLER_READING_DATA", + "ID": "c:stm32_hal_legacy.h@155190@macro@__GPIOG_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_READCONTROLLER_READING_DATA", + "display": "__GPIOG_CLK_DISABLE", "location": { "column": "9", - "line": "1629", + "line": "2906", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_READCONTROLLER_READING_DATA", + "name": "__GPIOG_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77746@macro@ETH_MAC_READCONTROLLER_READING_STATUS", + "ID": "c:stm32_hal_legacy.h@155246@macro@__GPIOG_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_READCONTROLLER_READING_STATUS", + "display": "__GPIOG_CLK_ENABLE", "location": { "column": "9", - "line": "1630", + "line": "2907", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_READCONTROLLER_READING_STATUS", + "name": "__GPIOG_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@77941@macro@ETH_MAC_READCONTROLLER_FLUSHING", + "ID": "c:stm32_hal_legacy.h@155300@macro@__GPIOG_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_READCONTROLLER_FLUSHING", + "display": "__GPIOG_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1633", + "line": "2908", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_READCONTROLLER_FLUSHING", + "name": "__GPIOG_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78128@macro@ETH_MAC_RXFIFO_WRITE_ACTIVE", + "ID": "c:stm32_hal_legacy.h@155368@macro@__GPIOG_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_RXFIFO_WRITE_ACTIVE", + "display": "__GPIOG_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1635", + "line": "2909", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_RXFIFO_WRITE_ACTIVE", + "name": "__GPIOG_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78225@macro@ETH_MAC_SMALL_FIFO_NOTACTIVE", + "ID": "c:stm32_hal_legacy.h@155434@macro@__GPIOG_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_SMALL_FIFO_NOTACTIVE", + "display": "__GPIOG_FORCE_RESET", "location": { "column": "9", - "line": "1636", + "line": "2910", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_SMALL_FIFO_NOTACTIVE", + "name": "__GPIOG_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78341@macro@ETH_MAC_SMALL_FIFO_READ_ACTIVE", + "ID": "c:stm32_hal_legacy.h@155490@macro@__GPIOG_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_SMALL_FIFO_READ_ACTIVE", + "display": "__GPIOG_RELEASE_RESET", "location": { "column": "9", - "line": "1637", + "line": "2911", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_SMALL_FIFO_READ_ACTIVE", + "name": "__GPIOG_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78444@macro@ETH_MAC_SMALL_FIFO_WRITE_ACTIVE", + "ID": "c:stm32_hal_legacy.h@155550@macro@__GPIOH_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_SMALL_FIFO_WRITE_ACTIVE", + "display": "__GPIOH_CLK_DISABLE", "location": { "column": "9", - "line": "1638", + "line": "2912", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_SMALL_FIFO_WRITE_ACTIVE", + "name": "__GPIOH_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78548@macro@ETH_MAC_SMALL_FIFO_RW_ACTIVE", + "ID": "c:stm32_hal_legacy.h@155606@macro@__GPIOH_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_SMALL_FIFO_RW_ACTIVE", + "display": "__GPIOH_CLK_ENABLE", "location": { "column": "9", - "line": "1639", + "line": "2913", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_SMALL_FIFO_RW_ACTIVE", + "name": "__GPIOH_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78660@macro@ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE", + "ID": "c:stm32_hal_legacy.h@155660@macro@__GPIOH_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE", + "display": "__GPIOH_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "1640", + "line": "2914", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE", + "name": "__GPIOH_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@78765@macro@ETH_TxPacketConfig", + "ID": "c:stm32_hal_legacy.h@155728@macro@__GPIOH_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "ETH_TxPacketConfig", + "display": "__GPIOH_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "1642", + "line": "2915", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "ETH_TxPacketConfig", + "name": "__GPIOH_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@79008@macro@HAL_DCMI_ERROR_OVF", + "ID": "c:stm32_hal_legacy.h@155794@macro@__GPIOH_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "HAL_DCMI_ERROR_OVF", + "display": "__GPIOH_FORCE_RESET", "location": { "column": "9", - "line": "1651", + "line": "2916", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "HAL_DCMI_ERROR_OVF", + "name": "__GPIOH_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@79059@macro@DCMI_IT_OVF", + "ID": "c:stm32_hal_legacy.h@155850@macro@__GPIOH_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "DCMI_IT_OVF", + "display": "__GPIOH_RELEASE_RESET", "location": { "column": "9", - "line": "1652", + "line": "2917", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "DCMI_IT_OVF", + "name": "__GPIOH_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@79103@macro@DCMI_FLAG_OVFRI", + "ID": "c:stm32_hal_legacy.h@155910@macro@__I2C1_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "DCMI_FLAG_OVFRI", + "display": "__I2C1_CLK_DISABLE", "location": { "column": "9", - "line": "1653", + "line": "2918", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "DCMI_FLAG_OVFRI", + "name": "__I2C1_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@79151@macro@DCMI_FLAG_OVFMI", + "ID": "c:stm32_hal_legacy.h@155964@macro@__I2C1_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "DCMI_FLAG_OVFMI", + "display": "__I2C1_CLK_ENABLE", "location": { "column": "9", - "line": "1654", + "line": "2919", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "DCMI_FLAG_OVFMI", + "name": "__I2C1_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@79200@macro@HAL_DCMI_ConfigCROP", + "ID": "c:stm32_hal_legacy.h@156016@macro@__I2C1_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": 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"c:stm32_hal_legacy.h@180815@macro@__SPI4_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PWR_VDDUSB_ENABLE", + "display": "__SPI4_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "2689", + "line": "3332", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PWR_VDDUSB_ENABLE", + "name": "__SPI4_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@142904@macro@__HAL_PVD_EXTI_ENABLE_IT", + "ID": "c:stm32_hal_legacy.h@180881@macro@__SPI4_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PVD_EXTI_ENABLE_IT", + "display": "__SPI4_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "2692", + "line": "3333", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PVD_EXTI_ENABLE_IT", + "name": "__SPI4_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@142995@macro@__HAL_PVD_EXTI_DISABLE_IT", + "ID": "c:stm32_hal_legacy.h@180948@macro@__GPIOI_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PVD_EXTI_DISABLE_IT", + "display": "__GPIOI_CLK_ENABLE", "location": { "column": "9", - "line": "2693", + "line": "3334", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PVD_EXTI_DISABLE_IT", + "name": "__GPIOI_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@143087@macro@__HAL_PVD_EXTI_GET_FLAG", + "ID": "c:stm32_hal_legacy.h@181011@macro@__GPIOI_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PVD_EXTI_GET_FLAG", + "display": "__GPIOI_CLK_DISABLE", "location": { "column": "9", - "line": "2694", + "line": "3335", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PVD_EXTI_GET_FLAG", + "name": "__GPIOI_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@143177@macro@__HAL_PVD_EXTI_CLEAR_FLAG", + "ID": "c:stm32_hal_legacy.h@181076@macro@__GPIOI_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PVD_EXTI_CLEAR_FLAG", + "display": "__GPIOI_FORCE_RESET", "location": { "column": "9", - "line": "2695", + "line": "3336", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PVD_EXTI_CLEAR_FLAG", + "name": "__GPIOI_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@143269@macro@__HAL_PVD_EXTI_GENERATE_SWIT", + "ID": "c:stm32_hal_legacy.h@181141@macro@__GPIOI_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_PVD_EXTI_GENERATE_SWIT", + "display": "__GPIOI_RELEASE_RESET", "location": { "column": "9", - "line": "2696", + "line": "3337", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__HAL_PVD_EXTI_GENERATE_SWIT", + "name": "__GPIOI_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@143973@macro@RCC_StopWakeUpClock_MSI", + "ID": "c:stm32_hal_legacy.h@181210@macro@__GPIOI_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "RCC_StopWakeUpClock_MSI", + "display": "__GPIOI_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "2713", + "line": "3338", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "RCC_StopWakeUpClock_MSI", + "name": "__GPIOI_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144034@macro@RCC_StopWakeUpClock_HSI", + "ID": "c:stm32_hal_legacy.h@181277@macro@__GPIOI_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "RCC_StopWakeUpClock_HSI", + "display": "__GPIOI_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "2714", + "line": "3339", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "RCC_StopWakeUpClock_HSI", + "name": "__GPIOI_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144096@macro@HAL_RCC_CCSCallback", + "ID": "c:stm32_hal_legacy.h@181346@macro@__GPIOJ_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "HAL_RCC_CCSCallback", + "display": "__GPIOJ_CLK_ENABLE", "location": { "column": "9", - "line": "2716", + "line": "3340", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "HAL_RCC_CCSCallback", + "name": "__GPIOJ_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144144@macro@HAL_RC48_EnableBuffer_Cmd", + "ID": "c:stm32_hal_legacy.h@181409@macro@__GPIOJ_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "HAL_RC48_EnableBuffer_Cmd", + "display": "__GPIOJ_CLK_DISABLE", "location": { "column": "9", - "line": "2717", + "line": "3341", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "HAL_RC48_EnableBuffer_Cmd", + "name": "__GPIOJ_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144313@macro@__ADC_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@181474@macro@__GPIOJ_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_CLK_DISABLE", + "display": "__GPIOJ_FORCE_RESET", "location": { "column": "9", - "line": "2720", + "line": "3342", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_CLK_DISABLE", + "name": "__GPIOJ_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144374@macro@__ADC_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@181538@macro@__GPIOJ_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_CLK_ENABLE", + "display": "__GPIOJ_RELEASE_RESET", "location": { "column": "9", - "line": "2721", + "line": "3343", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_CLK_ENABLE", + "name": "__GPIOJ_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144434@macro@__ADC_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@181607@macro@__GPIOJ_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_CLK_SLEEP_DISABLE", + "display": "__GPIOJ_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "2722", + "line": "3344", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_CLK_SLEEP_DISABLE", + "name": "__GPIOJ_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144501@macro@__ADC_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@181674@macro@__GPIOJ_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_CLK_SLEEP_ENABLE", + "display": "__GPIOJ_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "2723", + "line": "3345", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_CLK_SLEEP_ENABLE", + "name": "__GPIOJ_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144567@macro@__ADC_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@181743@macro@__GPIOK_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_FORCE_RESET", + "display": "__GPIOK_CLK_ENABLE", "location": { "column": "9", - "line": "2724", + "line": "3346", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_FORCE_RESET", + "name": "__GPIOK_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144628@macro@__ADC_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@181806@macro@__GPIOK_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC_RELEASE_RESET", + "display": "__GPIOK_CLK_DISABLE", "location": { "column": "9", - "line": "2725", + "line": "3347", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC_RELEASE_RESET", + "name": "__GPIOK_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144691@macro@__ADC1_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@181871@macro@__GPIOK_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_CLK_DISABLE", + "display": "__GPIOK_RELEASE_RESET", "location": { "column": "9", - "line": "2726", + "line": "3348", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_CLK_DISABLE", + "name": "__GPIOK_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144753@macro@__ADC1_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@181940@macro@__GPIOK_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_CLK_ENABLE", + "display": "__GPIOK_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "2727", + "line": "3349", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_CLK_ENABLE", + "name": "__GPIOK_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144814@macro@__ADC1_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@182007@macro@__GPIOK_CLK_SLEEP_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_FORCE_RESET", + "display": "__GPIOK_CLK_SLEEP_DISABLE", "location": { "column": "9", - "line": "2728", + "line": "3350", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_FORCE_RESET", + "name": "__GPIOK_CLK_SLEEP_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144876@macro@__ADC1_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@182076@macro@__ETH_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_RELEASE_RESET", + "display": "__ETH_CLK_ENABLE", "location": { "column": "9", - "line": "2729", + "line": "3351", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_RELEASE_RESET", + "name": "__ETH_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@144940@macro@__ADC1_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@182135@macro@__ETH_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_CLK_SLEEP_ENABLE", + "display": "__ETH_CLK_DISABLE", "location": { "column": "9", - "line": "2730", + "line": "3352", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_CLK_SLEEP_ENABLE", + "name": "__ETH_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145007@macro@__ADC1_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@182196@macro@__DCMI_CLK_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC1_CLK_SLEEP_DISABLE", + "display": "__DCMI_CLK_ENABLE", "location": { "column": "9", - "line": "2731", + "line": "3353", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC1_CLK_SLEEP_DISABLE", + "name": "__DCMI_CLK_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145075@macro@__ADC2_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@182257@macro@__DCMI_CLK_DISABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC2_CLK_DISABLE", + "display": "__DCMI_CLK_DISABLE", "location": { "column": "9", - "line": "2732", + "line": "3354", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC2_CLK_DISABLE", + "name": "__DCMI_CLK_DISABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145137@macro@__ADC2_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@182320@macro@__DCMI_FORCE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__ADC2_CLK_ENABLE", + "display": "__DCMI_FORCE_RESET", "location": { "column": "9", - "line": "2733", + "line": "3355", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC2_CLK_ENABLE", + "name": "__DCMI_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145198@macro@__ADC2_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@182383@macro@__DCMI_RELEASE_RESET", "What": "MacroDef", "defdec": "Def", - "display": "__ADC2_FORCE_RESET", + "display": "__DCMI_RELEASE_RESET", "location": { "column": "9", - "line": "2734", + "line": "3356", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC2_FORCE_RESET", + "name": "__DCMI_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145252@macro@__ADC2_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@182450@macro@__DCMI_CLK_SLEEP_ENABLE", "What": "MacroDef", "defdec": "Def", - "display": "__ADC2_RELEASE_RESET", + "display": "__DCMI_CLK_SLEEP_ENABLE", "location": { "column": "9", - "line": "2735", + "line": "3357", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__ADC2_RELEASE_RESET", + "name": "__DCMI_CLK_SLEEP_ENABLE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@145310@macro@__ADC3_CLK_DISABLE", + "ID": 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+ "ID": "c:stm32_hal_legacy.h@190958@macro@__GPIOD_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FMC_CLK_SLEEP_DISABLE", + "display": "__GPIOD_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2864", + "line": "3485", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FMC_CLK_SLEEP_DISABLE", + "name": "__GPIOD_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@152754@macro@__FMC_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@191025@macro@__GPIOD_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FMC_CLK_SLEEP_ENABLE", + "display": "__GPIOD_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2865", + "line": "3486", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FMC_CLK_SLEEP_ENABLE", + "name": "__GPIOD_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@152816@macro@__FMC_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@191093@macro@__GPIOE_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FMC_FORCE_RESET", + "display": "__GPIOE_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2866", + "line": "3487", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FMC_FORCE_RESET", + "name": "__GPIOE_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@152868@macro@__FMC_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@191160@macro@__GPIOE_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FMC_RELEASE_RESET", + "display": "__GPIOE_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2867", + "line": "3488", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FMC_RELEASE_RESET", + "name": "__GPIOE_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@152924@macro@__FSMC_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@191228@macro@__GPIOF_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FSMC_CLK_DISABLE", + "display": "__GPIOF_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2868", + "line": "3489", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FSMC_CLK_DISABLE", + "name": "__GPIOF_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@152978@macro@__FSMC_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@191295@macro@__GPIOF_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__FSMC_CLK_ENABLE", + "display": "__GPIOF_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2869", + "line": "3490", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__FSMC_CLK_ENABLE", + "name": "__GPIOF_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153030@macro@__GPIOA_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@191363@macro@__GPIOG_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_CLK_DISABLE", + "display": "__GPIOG_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2870", + "line": "3491", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_CLK_DISABLE", + "name": "__GPIOG_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153086@macro@__GPIOA_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@191430@macro@__GPIOG_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_CLK_ENABLE", + "display": "__GPIOG_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2871", + "line": "3492", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_CLK_ENABLE", + "name": "__GPIOG_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153140@macro@__GPIOA_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@191498@macro@__GPIOH_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_CLK_SLEEP_DISABLE", + "display": "__GPIOH_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2872", + "line": "3493", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_CLK_SLEEP_DISABLE", + "name": "__GPIOH_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153208@macro@__GPIOA_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@191565@macro@__GPIOH_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_CLK_SLEEP_ENABLE", + "display": "__GPIOH_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2873", + "line": "3494", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_CLK_SLEEP_ENABLE", + "name": "__GPIOH_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153274@macro@__GPIOA_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@191633@macro@__HRTIM1_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_FORCE_RESET", + "display": "__HRTIM1_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2874", + "line": "3495", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_FORCE_RESET", + "name": "__HRTIM1_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153330@macro@__GPIOA_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@191701@macro@__HRTIM1_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOA_RELEASE_RESET", + "display": "__HRTIM1_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2875", + "line": "3496", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOA_RELEASE_RESET", + "name": "__HRTIM1_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153390@macro@__GPIOB_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@191770@macro@__I2C1_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_CLK_DISABLE", + "display": "__I2C1_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2876", + "line": "3497", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_CLK_DISABLE", + "name": "__I2C1_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153446@macro@__GPIOB_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@191836@macro@__I2C1_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_CLK_ENABLE", + "display": "__I2C1_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2877", + "line": "3498", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_CLK_ENABLE", + "name": "__I2C1_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153500@macro@__GPIOB_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@191903@macro@__I2C2_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_CLK_SLEEP_DISABLE", + "display": "__I2C2_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2878", + "line": "3499", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_CLK_SLEEP_DISABLE", + "name": "__I2C2_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153568@macro@__GPIOB_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@191969@macro@__I2C2_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_CLK_SLEEP_ENABLE", + "display": "__I2C2_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2879", + "line": "3500", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_CLK_SLEEP_ENABLE", + "name": "__I2C2_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153634@macro@__GPIOB_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@192036@macro@__I2C3_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_FORCE_RESET", + "display": "__I2C3_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2880", + "line": "3501", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_FORCE_RESET", + "name": "__I2C3_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153690@macro@__GPIOB_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@192102@macro@__I2C3_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOB_RELEASE_RESET", + "display": "__I2C3_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2881", + "line": "3502", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOB_RELEASE_RESET", + "name": "__I2C3_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153750@macro@__GPIOC_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@192169@macro@__PWR_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_CLK_DISABLE", + "display": "__PWR_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2882", + "line": "3503", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_CLK_DISABLE", + "name": "__PWR_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153806@macro@__GPIOC_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@192234@macro@__PWR_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_CLK_ENABLE", + "display": "__PWR_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2883", + "line": "3504", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_CLK_ENABLE", + "name": "__PWR_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153860@macro@__GPIOC_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@192300@macro@__SYSCFG_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_CLK_SLEEP_DISABLE", + "display": "__SYSCFG_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2884", + "line": "3505", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_CLK_SLEEP_DISABLE", + "name": "__SYSCFG_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153928@macro@__GPIOC_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@192368@macro@__SYSCFG_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_CLK_SLEEP_ENABLE", + "display": "__SYSCFG_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2885", + "line": "3506", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_CLK_SLEEP_ENABLE", + "name": "__SYSCFG_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@153994@macro@__GPIOC_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@192437@macro@__SPI1_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_FORCE_RESET", + "display": "__SPI1_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2886", + "line": "3507", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_FORCE_RESET", + "name": "__SPI1_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154050@macro@__GPIOC_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@192503@macro@__SPI1_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOC_RELEASE_RESET", + "display": "__SPI1_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2887", + "line": "3508", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOC_RELEASE_RESET", + "name": "__SPI1_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154110@macro@__GPIOD_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@192570@macro@__SPI2_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_CLK_DISABLE", + "display": "__SPI2_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2888", + "line": "3509", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_CLK_DISABLE", + "name": "__SPI2_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154166@macro@__GPIOD_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@192636@macro@__SPI2_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_CLK_ENABLE", + "display": "__SPI2_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2889", + "line": "3510", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_CLK_ENABLE", + "name": "__SPI2_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154220@macro@__GPIOD_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@192703@macro@__SPI3_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_CLK_SLEEP_DISABLE", + "display": "__SPI3_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2890", + "line": "3511", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_CLK_SLEEP_DISABLE", + "name": "__SPI3_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154288@macro@__GPIOD_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@192769@macro@__SPI3_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_CLK_SLEEP_ENABLE", + "display": "__SPI3_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2891", + "line": "3512", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_CLK_SLEEP_ENABLE", + "name": "__SPI3_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154354@macro@__GPIOD_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@192836@macro@__SPI4_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_FORCE_RESET", + "display": "__SPI4_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2892", + "line": "3513", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_FORCE_RESET", + "name": "__SPI4_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154410@macro@__GPIOD_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@192902@macro@__SPI4_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOD_RELEASE_RESET", + "display": "__SPI4_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2893", + "line": "3514", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOD_RELEASE_RESET", + "name": "__SPI4_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154470@macro@__GPIOE_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@192969@macro@__SDADC1_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_CLK_DISABLE", + "display": "__SDADC1_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2894", + "line": "3515", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_CLK_DISABLE", + "name": "__SDADC1_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154526@macro@__GPIOE_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@193037@macro@__SDADC1_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_CLK_ENABLE", + "display": "__SDADC1_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2895", + "line": "3516", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_CLK_ENABLE", + "name": "__SDADC1_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154580@macro@__GPIOE_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@193106@macro@__SDADC2_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_CLK_SLEEP_DISABLE", + "display": "__SDADC2_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2896", + "line": "3517", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_CLK_SLEEP_DISABLE", + "name": "__SDADC2_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154648@macro@__GPIOE_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@193174@macro@__SDADC2_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_CLK_SLEEP_ENABLE", + "display": "__SDADC2_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2897", + "line": "3518", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_CLK_SLEEP_ENABLE", + "name": "__SDADC2_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154714@macro@__GPIOE_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@193243@macro@__SDADC3_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_FORCE_RESET", + "display": "__SDADC3_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2898", + "line": "3519", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_FORCE_RESET", + "name": "__SDADC3_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154770@macro@__GPIOE_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@193311@macro@__SDADC3_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOE_RELEASE_RESET", + "display": "__SDADC3_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2899", + "line": "3520", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOE_RELEASE_RESET", + "name": "__SDADC3_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154830@macro@__GPIOF_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@193380@macro@__SRAM_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_CLK_DISABLE", + "display": "__SRAM_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2900", + "line": "3521", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_CLK_DISABLE", + "name": "__SRAM_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154886@macro@__GPIOF_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@193446@macro@__SRAM_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_CLK_ENABLE", + "display": "__SRAM_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2901", + "line": "3522", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_CLK_ENABLE", + "name": "__SRAM_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@154940@macro@__GPIOF_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@193513@macro@__TIM1_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_CLK_SLEEP_DISABLE", + "display": "__TIM1_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2902", + "line": "3523", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_CLK_SLEEP_DISABLE", + "name": "__TIM1_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155008@macro@__GPIOF_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@193579@macro@__TIM1_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_CLK_SLEEP_ENABLE", + "display": "__TIM1_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2903", + "line": "3524", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_CLK_SLEEP_ENABLE", + "name": "__TIM1_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155074@macro@__GPIOF_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@193646@macro@__TIM2_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_FORCE_RESET", + "display": "__TIM2_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2904", + "line": "3525", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_FORCE_RESET", + "name": "__TIM2_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155130@macro@__GPIOF_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@193712@macro@__TIM2_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOF_RELEASE_RESET", + "display": "__TIM2_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2905", + "line": "3526", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOF_RELEASE_RESET", + "name": "__TIM2_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155190@macro@__GPIOG_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@193779@macro@__TIM3_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_CLK_DISABLE", + "display": "__TIM3_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2906", + "line": "3527", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_CLK_DISABLE", + "name": "__TIM3_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155246@macro@__GPIOG_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@193845@macro@__TIM3_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_CLK_ENABLE", + "display": "__TIM3_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2907", + "line": "3528", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_CLK_ENABLE", + "name": "__TIM3_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155300@macro@__GPIOG_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@193912@macro@__TIM4_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_CLK_SLEEP_DISABLE", + "display": "__TIM4_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2908", + "line": "3529", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_CLK_SLEEP_DISABLE", + "name": "__TIM4_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155368@macro@__GPIOG_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@193978@macro@__TIM4_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_CLK_SLEEP_ENABLE", + "display": "__TIM4_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2909", + "line": "3530", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_CLK_SLEEP_ENABLE", + "name": "__TIM4_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155434@macro@__GPIOG_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@194045@macro@__TIM5_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_FORCE_RESET", + "display": "__TIM5_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2910", + "line": "3531", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_FORCE_RESET", + "name": "__TIM5_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155490@macro@__GPIOG_RELEASE_RESET", + "ID": "c:stm32_hal_legacy.h@194111@macro@__TIM5_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOG_RELEASE_RESET", + "display": "__TIM5_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2911", + "line": "3532", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOG_RELEASE_RESET", + "name": "__TIM5_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155550@macro@__GPIOH_CLK_DISABLE", + "ID": "c:stm32_hal_legacy.h@194178@macro@__TIM6_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOH_CLK_DISABLE", + "display": "__TIM6_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2912", + "line": "3533", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOH_CLK_DISABLE", + "name": "__TIM6_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155606@macro@__GPIOH_CLK_ENABLE", + "ID": "c:stm32_hal_legacy.h@194244@macro@__TIM6_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOH_CLK_ENABLE", + "display": "__TIM6_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2913", + "line": "3534", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOH_CLK_ENABLE", + "name": "__TIM6_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155660@macro@__GPIOH_CLK_SLEEP_DISABLE", + "ID": "c:stm32_hal_legacy.h@194311@macro@__TIM7_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOH_CLK_SLEEP_DISABLE", + "display": "__TIM7_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2914", + "line": "3535", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOH_CLK_SLEEP_DISABLE", + "name": "__TIM7_IS_CLK_ENABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155728@macro@__GPIOH_CLK_SLEEP_ENABLE", + "ID": "c:stm32_hal_legacy.h@194377@macro@__TIM7_IS_CLK_DISABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOH_CLK_SLEEP_ENABLE", + "display": "__TIM7_IS_CLK_DISABLED", "location": { "column": "9", - "line": "2915", + "line": "3536", "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy\\stm32_hal_legacy.h" }, - "name": "__GPIOH_CLK_SLEEP_ENABLE", + "name": "__TIM7_IS_CLK_DISABLED", "origin": "user_include", "scope": null }, { - "ID": "c:stm32_hal_legacy.h@155794@macro@__GPIOH_FORCE_RESET", + "ID": "c:stm32_hal_legacy.h@194444@macro@__TIM8_IS_CLK_ENABLED", "What": "MacroDef", "defdec": "Def", - "display": "__GPIOH_FORCE_RESET", + "display": "__TIM8_IS_CLK_ENABLED", "location": { "column": "9", - "line": "2916", + "line": "3537", "path": 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"name": "HAL_HalfDuplex_Init", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTimeSet", + "ID": "c:@F@HAL_LIN_Init", "What": "Function", "defdec": "Dec", - "display": "void OSTimeSet(INT32U)", + "display": "HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *, uint32_t)", "location": { - "column": "15", - "line": "1222", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "719", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTimeSet", + "name": "HAL_LIN_Init", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTimeTick", + "ID": "c:@F@HAL_LIN_Init", "What": "Function", "defdec": "Dec", - "display": "void OSTimeTick(void)", + "display": "HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *, uint32_t)", "location": { - "column": "15", - "line": "1225", - "path": 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"ID": "c:@F@OSTmrCreate", + "ID": "c:@F@HAL_MultiProcessor_Init", "What": "Function", "defdec": "Dec", - "display": "OS_TMR * OSTmrCreate(INT32U, INT32U, INT8U, OS_TMR_CALLBACK, void *, INT8U *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *, uint8_t, uint32_t)", "location": { - "column": "14", - "line": "1234", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "720", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrCreate", + "name": "HAL_MultiProcessor_Init", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrCreate", + "ID": "c:@F@HAL_UART_DeInit", "What": "Function", "defdec": "Dec", - "display": "OS_TMR * OSTmrCreate(INT32U, INT32U, INT8U, OS_TMR_CALLBACK, void *, INT8U *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1234", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "721", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrCreate", + "name": "HAL_UART_DeInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrDel", + "ID": "c:@F@HAL_UART_DeInit", "What": "Function", "defdec": "Dec", - "display": "BOOLEAN OSTmrDel(OS_TMR *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1242", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "721", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrDel", + "name": "HAL_UART_DeInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrDel", + "ID": "c:@F@HAL_UART_MspInit", "What": "Function", "defdec": "Dec", - "display": "BOOLEAN OSTmrDel(OS_TMR *, INT8U *)", + "display": "void HAL_UART_MspInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1242", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "722", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrDel", + "name": "HAL_UART_MspInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrNameGet", + "ID": "c:@F@HAL_UART_MspInit", "What": "Function", "defdec": "Dec", - "display": "INT8U OSTmrNameGet(OS_TMR *, INT8U **, INT8U *)", + "display": "void HAL_UART_MspInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1246", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "722", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrNameGet", + "name": "HAL_UART_MspInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrNameGet", + "ID": "c:@F@HAL_UART_MspInit", "What": "Function", "defdec": "Dec", - "display": "INT8U OSTmrNameGet(OS_TMR *, INT8U **, INT8U *)", + "display": "void HAL_UART_MspInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1246", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "722", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrNameGet", + "name": "HAL_UART_MspInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrRemainGet", + "ID": "c:@F@HAL_UART_MspDeInit", "What": "Function", "defdec": "Dec", - "display": "INT32U OSTmrRemainGet(OS_TMR *, INT8U *)", + "display": "void HAL_UART_MspDeInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1250", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "723", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrRemainGet", + "name": "HAL_UART_MspDeInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrRemainGet", + "ID": "c:@F@HAL_UART_MspDeInit", "What": "Function", "defdec": "Dec", - "display": "INT32U OSTmrRemainGet(OS_TMR *, INT8U *)", + "display": "void HAL_UART_MspDeInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1250", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "723", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrRemainGet", + "name": "HAL_UART_MspDeInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrStateGet", + "ID": "c:@F@HAL_UART_MspDeInit", "What": "Function", "defdec": "Dec", - "display": "INT8U OSTmrStateGet(OS_TMR *, INT8U *)", + "display": "void HAL_UART_MspDeInit(UART_HandleTypeDef *)", "location": { - "column": "14", - "line": "1253", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "6", + "line": "723", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrStateGet", + "name": "HAL_UART_MspDeInit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrStateGet", + "ID": "c:@F@HAL_UART_Transmit", "What": "Function", "defdec": "Dec", - "display": "INT8U OSTmrStateGet(OS_TMR *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *, const uint8_t *, uint16_t, uint32_t)", "location": { - "column": "14", - "line": "1253", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "744", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrStateGet", + "name": "HAL_UART_Transmit", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrStart", + "ID": "c:@F@HAL_UART_Transmit", "What": "Function", "defdec": "Dec", - "display": "BOOLEAN OSTmrStart(OS_TMR *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *, const uint8_t *, uint16_t, uint32_t)", "location": { - "column": "14", - "line": "1256", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + 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- "display": "BOOLEAN OSTmrStop(OS_TMR *, INT8U, void *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *, uint8_t *, uint16_t, uint32_t)", "location": { - "column": "14", - "line": "1259", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "745", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrStop", + "name": "HAL_UART_Receive", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSTmrStop", + "ID": "c:@F@HAL_UART_Transmit_IT", "What": "Function", "defdec": "Dec", - "display": "BOOLEAN OSTmrStop(OS_TMR *, INT8U, void *, INT8U *)", + "display": "HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *, const uint8_t *, uint16_t)", "location": { - "column": "14", - "line": "1259", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + 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"Function", "defdec": "Dec", - "display": "INT8U OSTmrSignal(void)", + "display": "HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *, uint8_t *, uint16_t)", "location": { - "column": "14", - "line": "1264", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "747", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSTmrSignal", + "name": "HAL_UART_Receive_IT", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSInit", + "ID": "c:@F@HAL_UART_Receive_IT", "What": "Function", "defdec": "Dec", - "display": "void OSInit(void)", + "display": "HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *, uint8_t *, uint16_t)", "location": { - "column": "15", - "line": "1273", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "747", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSInit", + "name": "HAL_UART_Receive_IT", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSInit", + "ID": "c:@F@HAL_UART_Transmit_DMA", "What": "Function", "defdec": "Dec", - "display": "void OSInit(void)", + "display": "HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *, const uint8_t *, uint16_t)", "location": { - "column": "15", - "line": "1273", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "748", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSInit", + "name": "HAL_UART_Transmit_DMA", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSIntEnter", + "ID": "c:@F@HAL_UART_Transmit_DMA", "What": "Function", "defdec": "Dec", - "display": "void OSIntEnter(void)", + "display": "HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *, const uint8_t *, uint16_t)", "location": { - "column": "15", - "line": "1275", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "748", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSIntEnter", + "name": "HAL_UART_Transmit_DMA", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSIntEnter", + "ID": "c:@F@HAL_UART_Receive_DMA", "What": "Function", "defdec": "Dec", - "display": "void OSIntEnter(void)", + "display": "HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *, uint8_t *, uint16_t)", "location": { - "column": "15", - "line": "1275", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "749", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSIntEnter", + "name": "HAL_UART_Receive_DMA", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSIntExit", + "ID": "c:@F@HAL_UART_Receive_DMA", "What": "Function", "defdec": "Dec", - "display": "void OSIntExit(void)", + "display": "HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *, uint8_t *, uint16_t)", "location": { - "column": "15", - "line": "1276", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "749", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSIntExit", + "name": "HAL_UART_Receive_DMA", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSIntExit", + "ID": "c:@F@HAL_UART_DMAPause", "What": "Function", "defdec": "Dec", - "display": "void OSIntExit(void)", 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"name": "OSSchedLock", + "name": "HAL_UART_DMAPause", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSSchedLock", + "ID": "c:@F@HAL_UART_DMAResume", "What": "Function", "defdec": "Dec", - "display": "void OSSchedLock(void)", + "display": "HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *)", "location": { - "column": "15", - "line": "1283", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "751", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSSchedLock", + "name": "HAL_UART_DMAResume", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSSchedUnlock", + "ID": "c:@F@HAL_UART_DMAResume", "What": "Function", "defdec": "Dec", - "display": "void OSSchedUnlock(void)", + "display": "HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *)", "location": { - "column": "15", - "line": "1284", - "path": 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"ID": "c:@F@HAL_UART_DMAStop", "What": "Function", "defdec": "Dec", - "display": "void OSStart(void)", + "display": "HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *)", "location": { - "column": "15", - "line": "1287", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", + "line": "752", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" }, - "name": "OSStart", + "name": "HAL_UART_DMAStop", "origin": "user_include", "scope": null }, { - "ID": "c:@F@OSStart", + "ID": "c:@F@HAL_UARTEx_ReceiveToIdle", "What": "Function", "defdec": "Dec", - "display": "void OSStart(void)", + "display": "HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *, uint8_t *, uint16_t, uint16_t *, uint32_t)", "location": { - "column": "15", - "line": "1287", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\UCOS\\Source\\ucos_ii.h" + "column": "19", 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HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *, const TIM_ClockConfigTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc_ex.h@158519@macro@__HAL_RCC_RNG_FORCE_RESET", + "What": "MacroDef", + "defdec": "Def", + "display": "__HAL_RCC_RNG_FORCE_RESET", "location": { - "column": "19", - "line": "2045", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" + "column": "9", + "line": "2669", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc_ex.h" }, - "name": "HAL_TIM_ConfigClockSource", + "name": "__HAL_RCC_RNG_FORCE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_TIM_ConfigClockSource", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *, const TIM_ClockConfigTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc_ex.h@158599@macro@__HAL_RCC_RNG_RELEASE_RESET", + "What": "MacroDef", + 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"__HAL_RCC_TIM7_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_TIM_OC_DelayElapsedCallback", - "What": "Function", - "defdec": "Dec", - "display": "void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc_ex.h@161272@macro@__HAL_RCC_TIM12_RELEASE_RESET", + "What": "MacroDef", + "defdec": "Def", + "display": "__HAL_RCC_TIM12_RELEASE_RESET", "location": { - "column": "6", - "line": "2075", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" + "column": "9", + "line": "2717", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc_ex.h" }, - "name": "HAL_TIM_OC_DelayElapsedCallback", + "name": "__HAL_RCC_TIM12_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_TIM_IC_CaptureCallback", - "What": "Function", - "defdec": "Dec", - "display": "void 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"__HAL_RCC_UART5_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_TIM_PWM_PulseFinishedCallback", - "What": "Function", - "defdec": "Dec", - "display": "void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc_ex.h@161783@macro@__HAL_RCC_CAN1_RELEASE_RESET", + "What": "MacroDef", + "defdec": "Def", + "display": "__HAL_RCC_CAN1_RELEASE_RESET", "location": { - "column": "6", - "line": "2078", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_tim.h" + "column": "9", + "line": "2723", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc_ex.h" }, - "name": "HAL_TIM_PWM_PulseFinishedCallback", + "name": "__HAL_RCC_CAN1_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_TIM_PWM_PulseFinishedHalfCpltCallback", - "What": "Function", - "defdec": "Dec", - "display": "void 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"e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" }, - "name": "HAL_UART_AbortReceive", + "name": "RCC_RTCCLKSOURCE_HSE_DIV10", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_UART_AbortReceive", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc.h@9356@macro@RCC_RTCCLKSOURCE_HSE_DIV11", + "What": "MacroDef", + "defdec": "Def", + "display": "RCC_RTCCLKSOURCE_HSE_DIV11", "location": { - "column": "19", - "line": "764", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" + "column": "9", + "line": "266", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" }, - "name": "HAL_UART_AbortReceive", + "name": "RCC_RTCCLKSOURCE_HSE_DIV11", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_UART_Abort_IT", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc.h@9409@macro@RCC_RTCCLKSOURCE_HSE_DIV12", + "What": "MacroDef", + "defdec": "Def", + "display": "RCC_RTCCLKSOURCE_HSE_DIV12", "location": { - "column": "19", - "line": "765", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_uart.h" + "column": "9", + "line": "267", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" }, - "name": "HAL_UART_Abort_IT", + "name": "RCC_RTCCLKSOURCE_HSE_DIV12", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_UART_Abort_IT", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *)", + "ID": "c:stm32f4xx_hal_rcc.h@9462@macro@RCC_RTCCLKSOURCE_HSE_DIV13", + "What": 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"__HAL_RCC_USART2_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@fputc", - "What": "Function", - "defdec": "Dec", - "display": "int fputc(int, FILE *)", + "ID": "c:stm32f4xx_hal_rcc.h@34531@macro@__HAL_RCC_I2C1_RELEASE_RESET", + "What": "MacroDef", + "defdec": "Def", + "display": "__HAL_RCC_I2C1_RELEASE_RESET", "location": { - "column": "5", - "line": "107", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\usart.h" + "column": "9", + "line": "698", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_rcc.h" }, - "name": "fputc", + "name": "__HAL_RCC_I2C1_RELEASE_RESET", "origin": "user_include", "scope": null }, { - "ID": "c:@F@fputc", - "What": "Function", - "defdec": "Dec", - "display": "int fputc(int, FILE *)", + "ID": "c:stm32f4xx_hal_rcc.h@34615@macro@__HAL_RCC_I2C2_RELEASE_RESET", + "What": "MacroDef", + "defdec": "Def", + "display": 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"scope": null }, { - "ID": "c:stm32f4xx_hal_conf.h@13707@macro@USE_SPI_CRC", - "What": "MacroDef", - "defdec": "Def", - "display": "USE_SPI_CRC", + "ID": "c:@F@HAL_GPIO_Init", + "What": "Function", + "defdec": "Dec", + "display": "void HAL_GPIO_Init(GPIO_TypeDef *, GPIO_InitTypeDef *)", "location": { - "column": "9", - "line": "269", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_hal_conf.h" + "column": "7", + "line": "224", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio.h" }, - "name": "USE_SPI_CRC", + "name": "HAL_GPIO_Init", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_conf.h@19945@macro@assert_param", - "What": "MacroDef", - "defdec": "Def", - "display": "assert_param", + "ID": "c:@F@HAL_GPIO_Init", + "What": "Function", + "defdec": "Dec", + "display": "void HAL_GPIO_Init(GPIO_TypeDef *, GPIO_InitTypeDef *)", "location": { - "column": "11", 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"c:mpu_armv7.h@1895@macro@ARM_MPU_REGION_SIZE_8KB", - "What": "MacroDef", - "defdec": "Def", - "display": "ARM_MPU_REGION_SIZE_8KB", + "ID": "c:@F@HAL_GPIO_LockPin", + "What": "Function", + "defdec": "Dec", + "display": "HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *, uint16_t)", "location": { - "column": "9", - "line": "42", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + "column": "19", + "line": "237", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio.h" }, - "name": "ARM_MPU_REGION_SIZE_8KB", + "name": "HAL_GPIO_LockPin", "origin": "user_include", "scope": null }, { - "ID": "c:mpu_armv7.h@1980@macro@ARM_MPU_REGION_SIZE_16KB", - "What": "MacroDef", - "defdec": "Def", - "display": "ARM_MPU_REGION_SIZE_16KB", - "location": { - "column": "9", - "line": "43", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + "ID": "c:@F@HAL_GPIO_EXTI_IRQHandler", + "What": "Function", + "defdec": "Dec", + "display": "void HAL_GPIO_EXTI_IRQHandler(uint16_t)", + "location": { + "column": "6", + "line": "238", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio.h" }, - "name": "ARM_MPU_REGION_SIZE_16KB", + "name": "HAL_GPIO_EXTI_IRQHandler", "origin": "user_include", "scope": null }, { - "ID": "c:mpu_armv7.h@2066@macro@ARM_MPU_REGION_SIZE_32KB", - "What": "MacroDef", - "defdec": "Def", - "display": "ARM_MPU_REGION_SIZE_32KB", + "ID": "c:@F@HAL_GPIO_EXTI_IRQHandler", + "What": "Function", + "defdec": "Dec", + "display": "void HAL_GPIO_EXTI_IRQHandler(uint16_t)", "location": { - "column": "9", - "line": "44", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + "column": "6", + "line": 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"c:mpu_armv7.h@2499@macro@ARM_MPU_REGION_SIZE_1MB", + "ID": "c:stm32f4xx_hal_gpio.h@10678@macro@MODE_INPUT", "What": "MacroDef", "defdec": "Def", - "display": "ARM_MPU_REGION_SIZE_1MB", + "display": "MODE_INPUT", "location": { "column": "9", - "line": "49", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + "line": "256", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio.h" }, - "name": "ARM_MPU_REGION_SIZE_1MB", + "name": "MODE_INPUT", "origin": "user_include", "scope": null }, { - "ID": "c:mpu_armv7.h@2583@macro@ARM_MPU_REGION_SIZE_2MB", + "ID": "c:stm32f4xx_hal_gpio.h@10751@macro@MODE_OUTPUT", "What": "MacroDef", "defdec": "Def", - "display": "ARM_MPU_REGION_SIZE_2MB", + "display": "MODE_OUTPUT", "location": { "column": "9", - "line": "50", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + "line": 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"c:@F@HAL_NVIC_GetPendingIRQ", + "ID": "c:@F@PLSR_Route_Init", "What": "Function", "defdec": "Dec", - "display": "uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Init(PLSR_RouteConfig_t *)", "location": { - "column": "10", - "line": "276", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "6", + "line": "205", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_GetPendingIRQ", + "name": "PLSR_Route_Init", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_GetPendingIRQ", + "ID": "c:@F@PLSR_Route_Init", "What": "Function", "defdec": "Dec", - "display": "uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Init(PLSR_RouteConfig_t *)", "location": { - "column": "10", - "line": "276", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "6", + "line": "205", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_GetPendingIRQ", + "name": "PLSR_Route_Init", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_SetPendingIRQ", + "ID": "c:@F@PLSR_Route_Set", "What": "Function", "defdec": "Dec", - "display": "void HAL_NVIC_SetPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Set(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "277", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "206", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_SetPendingIRQ", + "name": "PLSR_Route_Set", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_SetPendingIRQ", + "ID": "c:@F@PLSR_Route_Set", "What": "Function", "defdec": "Dec", - "display": "void HAL_NVIC_SetPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Set(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "277", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "206", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_SetPendingIRQ", + "name": "PLSR_Route_Set", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_ClearPendingIRQ", + "ID": "c:@F@PLSR_Route_Start", "What": "Function", "defdec": "Dec", - "display": "void HAL_NVIC_ClearPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Start(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "278", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "207", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_ClearPendingIRQ", + "name": "PLSR_Route_Start", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_ClearPendingIRQ", + "ID": "c:@F@PLSR_Route_Start", "What": "Function", "defdec": "Dec", - "display": "void HAL_NVIC_ClearPendingIRQ(IRQn_Type)", + "display": "void PLSR_Route_Start(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "278", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "207", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_ClearPendingIRQ", + "name": "PLSR_Route_Start", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_GetActive", + "ID": "c:@F@PLSR_Route_Stop", "What": "Function", "defdec": "Dec", - "display": "uint32_t HAL_NVIC_GetActive(IRQn_Type)", + "display": "void PLSR_Route_Stop(PLSR_RouteConfig_t *)", "location": { - "column": "10", - "line": "279", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "6", + "line": "208", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_GetActive", + "name": "PLSR_Route_Stop", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_NVIC_GetActive", + "ID": "c:@F@PLSR_Route_Stop", "What": "Function", "defdec": "Dec", - "display": "uint32_t HAL_NVIC_GetActive(IRQn_Type)", + "display": "void PLSR_Route_Stop(PLSR_RouteConfig_t *)", "location": { - "column": "10", - "line": "279", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "6", + "line": "208", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_NVIC_GetActive", + "name": "PLSR_Route_Stop", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_CLKSourceConfig", + "ID": "c:@F@PLSR_Section_Process", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_CLKSourceConfig(uint32_t)", + "display": "void PLSR_Section_Process(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "280", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "209", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_CLKSourceConfig", + "name": "PLSR_Section_Process", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_CLKSourceConfig", + "ID": "c:@F@PLSR_Section_Process", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_CLKSourceConfig(uint32_t)", + "display": "void PLSR_Section_Process(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "280", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "209", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_CLKSourceConfig", + "name": "PLSR_Section_Process", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_IRQHandler", + "ID": "c:@F@PLSR_Section_SwitchNext", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_IRQHandler(void)", + "display": "void PLSR_Section_SwitchNext(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "281", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "212", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_IRQHandler", + "name": "PLSR_Section_SwitchNext", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_IRQHandler", + "ID": "c:@F@PLSR_Section_SwitchNext", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_IRQHandler(void)", + "display": "void PLSR_Section_SwitchNext(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "281", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "212", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_IRQHandler", + "name": "PLSR_Section_SwitchNext", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_Callback", + "ID": "c:@F@PLSR_Section_CheckWaitCondition", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_Callback(void)", + "display": "uint8_t PLSR_Section_CheckWaitCondition(PLSR_RouteConfig_t *)", "location": { - "column": "6", - "line": "282", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "9", + "line": "213", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_Callback", + "name": "PLSR_Section_CheckWaitCondition", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_SYSTICK_Callback", + "ID": "c:@F@PLSR_Section_CheckWaitCondition", "What": "Function", "defdec": "Dec", - "display": "void HAL_SYSTICK_Callback(void)", + "display": "uint8_t PLSR_Section_CheckWaitCondition(PLSR_RouteConfig_t *)", "location": { - "column": "6", - "line": "282", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "9", + "line": "213", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_SYSTICK_Callback", + "name": "PLSR_Section_CheckWaitCondition", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_Enable", + "ID": "c:@F@PLSR_Section_CalculateConstPulse", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_Enable(uint32_t)", + "display": "void PLSR_Section_CalculateConstPulse(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "285", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "214", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_Enable", + "name": "PLSR_Section_CalculateConstPulse", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_Enable", + "ID": "c:@F@PLSR_Section_CalculateConstPulse", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_Enable(uint32_t)", + "display": "void PLSR_Section_CalculateConstPulse(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "285", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "214", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_Enable", + "name": "PLSR_Section_CalculateConstPulse", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_Disable", + "ID": "c:@F@PLSR_Section_StartNewSection", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_Disable(void)", + "display": "void PLSR_Section_StartNewSection(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "286", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "215", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_Disable", + "name": "PLSR_Section_StartNewSection", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_Disable", + "ID": "c:@F@PLSR_Section_StartNewSection", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_Disable(void)", + "display": "void PLSR_Section_StartNewSection(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "286", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "215", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_Disable", + "name": "PLSR_Section_StartNewSection", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_EnableRegion", + "ID": "c:@F@PLSR_Accel_CalculateCurve", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_EnableRegion(uint32_t)", + "display": "float PLSR_Accel_CalculateCurve(float)", "location": { - "column": "6", - "line": "287", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "7", + "line": "218", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_EnableRegion", + "name": "PLSR_Accel_CalculateCurve", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_EnableRegion", + "ID": "c:@F@PLSR_Accel_CalculateCurve", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_EnableRegion(uint32_t)", + "display": "float PLSR_Accel_CalculateCurve(float)", "location": { - "column": "6", - "line": "287", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "7", + "line": "218", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_EnableRegion", + "name": "PLSR_Accel_CalculateCurve", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_DisableRegion", + "ID": "c:@F@PLSR_Accel_CalculateSine", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_DisableRegion(uint32_t)", + "display": "float PLSR_Accel_CalculateSine(float)", "location": { - "column": "6", - "line": "288", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "7", + "line": "219", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_DisableRegion", + "name": "PLSR_Accel_CalculateSine", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_DisableRegion", + "ID": "c:@F@PLSR_Accel_CalculateSine", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_DisableRegion(uint32_t)", + "display": "float PLSR_Accel_CalculateSine(float)", "location": { - "column": "6", - "line": "288", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "column": "7", + "line": "219", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_DisableRegion", + "name": "PLSR_Accel_CalculateSine", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_ConfigRegion", + "ID": "c:@F@PLSR_Accel_Process", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *)", + "display": "void PLSR_Accel_Process(PLSR_RouteConfig_t *)", "location": { "column": "6", - "line": "289", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_cortex.h" + "line": "220", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\tim.h" }, - "name": "HAL_MPU_ConfigRegion", + "name": "PLSR_Accel_Process", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_MPU_ConfigRegion", + "ID": "c:@F@PLSR_Accel_Process", "What": "Function", "defdec": "Dec", - "display": "void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef 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"origin": "user_include", + "scope": null + }, + { + "ID": "c:mpu_armv7.h@F@ARM_MPU_SetRegionEx", + "What": "Function", + "defdec": "Def", + "display": "void ARM_MPU_SetRegionEx(uint32_t, uint32_t, uint32_t)", + "location": { + "column": "22", + "line": "239", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + }, + "name": "ARM_MPU_SetRegionEx", + "origin": "user_include", + "scope": null + }, + { + "ID": "c:mpu_armv7.h@F@ARM_MPU_OrderedMemcpy", + "What": "Function", + "defdec": "Def", + "display": "void ARM_MPU_OrderedMemcpy(volatile uint32_t *, const uint32_t *restrict, uint32_t)", + "location": { + "column": "22", + "line": "251", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\CMSIS\\Include\\mpu_armv7.h" + }, + "name": "ARM_MPU_OrderedMemcpy", + "origin": "user_include", + "scope": null + }, + { + "ID": "c:mpu_armv7.h@11081@F@ARM_MPU_OrderedMemcpy@i", + "What": "Variable", + "defdec": "Def", + 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"user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3225@macro@HAL_FLASH_ERROR_OPERATION", + "ID": "c:stm32f4xx_hal_gpio_ex.h@12913@macro@GPIO_AF0_TAMPER", "What": "MacroDef", "defdec": "Def", - "display": "HAL_FLASH_ERROR_OPERATION", + "display": "GPIO_AF0_TAMPER", "location": { "column": "9", - "line": "94", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "289", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "HAL_FLASH_ERROR_OPERATION", + "name": "GPIO_AF0_TAMPER", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3396@macro@FLASH_TYPEPROGRAM_BYTE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13025@macro@GPIO_AF0_SWJ", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_TYPEPROGRAM_BYTE", + "display": "GPIO_AF0_SWJ", "location": { "column": "9", - "line": "102", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "290", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_TYPEPROGRAM_BYTE", + "name": "GPIO_AF0_SWJ", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3509@macro@FLASH_TYPEPROGRAM_HALFWORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13137@macro@GPIO_AF0_TRACE", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_TYPEPROGRAM_HALFWORD", + "display": "GPIO_AF0_TRACE", "location": { "column": "9", - "line": "103", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "291", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_TYPEPROGRAM_HALFWORD", + "name": "GPIO_AF0_TRACE", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3622@macro@FLASH_TYPEPROGRAM_WORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13291@macro@GPIO_AF1_TIM1", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_TYPEPROGRAM_WORD", + "display": "GPIO_AF1_TIM1", "location": { "column": "9", - "line": "104", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "296", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_TYPEPROGRAM_WORD", + "name": "GPIO_AF1_TIM1", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3735@macro@FLASH_TYPEPROGRAM_DOUBLEWORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13377@macro@GPIO_AF1_TIM2", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_TYPEPROGRAM_DOUBLEWORD", + "display": "GPIO_AF1_TIM2", "location": { "column": "9", - "line": "105", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "297", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_TYPEPROGRAM_DOUBLEWORD", + "name": "GPIO_AF1_TIM2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@3962@macro@FLASH_FLAG_EOP", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13505@macro@GPIO_AF2_TIM3", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_EOP", + "display": "GPIO_AF2_TIM3", "location": { "column": "9", - "line": "114", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "302", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_EOP", + "name": "GPIO_AF2_TIM3", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4075@macro@FLASH_FLAG_OPERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13591@macro@GPIO_AF2_TIM4", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_OPERR", + "display": "GPIO_AF2_TIM4", "location": { "column": "9", - "line": "115", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "303", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_OPERR", + "name": "GPIO_AF2_TIM4", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4188@macro@FLASH_FLAG_WRPERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13677@macro@GPIO_AF2_TIM5", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_WRPERR", + "display": "GPIO_AF2_TIM5", "location": { "column": "9", - "line": "116", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "304", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_WRPERR", + "name": "GPIO_AF2_TIM5", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4301@macro@FLASH_FLAG_PGAERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13805@macro@GPIO_AF3_TIM8", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_PGAERR", + "display": "GPIO_AF3_TIM8", "location": { "column": "9", - "line": "117", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "309", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_PGAERR", + "name": "GPIO_AF3_TIM8", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4414@macro@FLASH_FLAG_PGPERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13892@macro@GPIO_AF3_TIM9", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_PGPERR", + "display": "GPIO_AF3_TIM9", "location": { "column": "9", - "line": "118", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "310", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_PGPERR", + "name": "GPIO_AF3_TIM9", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4527@macro@FLASH_FLAG_PGSERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@13979@macro@GPIO_AF3_TIM10", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_PGSERR", + "display": "GPIO_AF3_TIM10", "location": { "column": "9", - "line": "119", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "311", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_PGSERR", + "name": "GPIO_AF3_TIM10", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@4809@macro@FLASH_FLAG_BSY", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14066@macro@GPIO_AF3_TIM11", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_FLAG_BSY", + "display": "GPIO_AF3_TIM11", "location": { "column": "9", - "line": "123", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "312", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_FLAG_BSY", + "name": "GPIO_AF3_TIM11", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5057@macro@FLASH_IT_EOP", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14195@macro@GPIO_AF4_I2C1", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_IT_EOP", + "display": "GPIO_AF4_I2C1", "location": { "column": "9", - "line": "132", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "317", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_IT_EOP", + "name": "GPIO_AF4_I2C1", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5168@macro@FLASH_IT_ERR", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14281@macro@GPIO_AF4_I2C2", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_IT_ERR", + "display": "GPIO_AF4_I2C2", "location": { "column": "9", - "line": "133", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "318", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_IT_ERR", + "name": "GPIO_AF4_I2C2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5374@macro@FLASH_PSIZE_BYTE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14367@macro@GPIO_AF4_I2C3", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_PSIZE_BYTE", + "display": "GPIO_AF4_I2C3", "location": { "column": "9", - "line": "141", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "319", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_PSIZE_BYTE", + "name": "GPIO_AF4_I2C3", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5421@macro@FLASH_PSIZE_HALF_WORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14495@macro@GPIO_AF5_SPI1", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_PSIZE_HALF_WORD", + "display": "GPIO_AF5_SPI1", "location": { "column": "9", - "line": "142", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "324", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_PSIZE_HALF_WORD", + "name": "GPIO_AF5_SPI1", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5468@macro@FLASH_PSIZE_WORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14588@macro@GPIO_AF5_SPI2", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_PSIZE_WORD", + "display": "GPIO_AF5_SPI2", "location": { "column": "9", - "line": "143", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "325", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_PSIZE_WORD", + "name": "GPIO_AF5_SPI2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5515@macro@FLASH_PSIZE_DOUBLE_WORD", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14681@macro@GPIO_AF5_I2S3ext", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_PSIZE_DOUBLE_WORD", + "display": "GPIO_AF5_I2S3ext", "location": { "column": "9", - "line": "144", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "326", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_PSIZE_DOUBLE_WORD", + "name": "GPIO_AF5_I2S3ext", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5562@macro@CR_PSIZE_MASK", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14816@macro@GPIO_AF6_SPI3", "What": "MacroDef", "defdec": "Def", - "display": "CR_PSIZE_MASK", + "display": "GPIO_AF6_SPI3", "location": { "column": "9", - "line": "145", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "331", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "CR_PSIZE_MASK", + "name": "GPIO_AF6_SPI3", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5674@macro@RDP_KEY", + "ID": "c:stm32f4xx_hal_gpio_ex.h@14908@macro@GPIO_AF6_I2S2ext", "What": "MacroDef", "defdec": "Def", - "display": "RDP_KEY", + "display": "GPIO_AF6_I2S2ext", "location": { "column": "9", - "line": "153", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "332", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "RDP_KEY", + "name": "GPIO_AF6_I2S2ext", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5726@macro@FLASH_KEY1", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15042@macro@GPIO_AF7_USART1", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_KEY1", + "display": "GPIO_AF7_USART1", "location": { "column": "9", - "line": "154", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "337", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_KEY1", + "name": "GPIO_AF7_USART1", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5771@macro@FLASH_KEY2", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15134@macro@GPIO_AF7_USART2", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_KEY2", + "display": "GPIO_AF7_USART2", "location": { "column": "9", - "line": "155", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "338", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_KEY2", + "name": "GPIO_AF7_USART2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5816@macro@FLASH_OPT_KEY1", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15226@macro@GPIO_AF7_USART3", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_OPT_KEY1", + "display": "GPIO_AF7_USART3", "location": { "column": "9", - "line": "156", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "339", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_OPT_KEY1", + "name": "GPIO_AF7_USART3", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@5861@macro@FLASH_OPT_KEY2", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15318@macro@GPIO_AF7_I2S3ext", "What": "MacroDef", "defdec": "Def", - "display": "FLASH_OPT_KEY2", + "display": "GPIO_AF7_I2S3ext", "location": { "column": "9", - "line": "157", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "340", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "FLASH_OPT_KEY2", + "name": "GPIO_AF7_I2S3ext", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@6275@macro@__HAL_FLASH_SET_LATENCY", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15452@macro@GPIO_AF8_UART4", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_SET_LATENCY", + "display": "GPIO_AF8_UART4", "location": { "column": "9", - "line": "176", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "345", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_SET_LATENCY", + "name": "GPIO_AF8_UART4", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@6539@macro@__HAL_FLASH_GET_LATENCY", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15540@macro@GPIO_AF8_UART5", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_GET_LATENCY", + "display": "GPIO_AF8_UART5", "location": { "column": "9", - "line": "183", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "346", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_GET_LATENCY", + "name": "GPIO_AF8_UART5", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@6694@macro@__HAL_FLASH_PREFETCH_BUFFER_ENABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15628@macro@GPIO_AF8_USART6", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_PREFETCH_BUFFER_ENABLE", + "display": "GPIO_AF8_USART6", "location": { "column": "9", - "line": "189", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "347", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_PREFETCH_BUFFER_ENABLE", + "name": "GPIO_AF8_USART6", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@6847@macro@__HAL_FLASH_PREFETCH_BUFFER_DISABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15757@macro@GPIO_AF9_CAN1", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_PREFETCH_BUFFER_DISABLE", + "display": "GPIO_AF9_CAN1", "location": { "column": "9", - "line": "195", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "352", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_PREFETCH_BUFFER_DISABLE", + "name": "GPIO_AF9_CAN1", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@7006@macro@__HAL_FLASH_INSTRUCTION_CACHE_ENABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15844@macro@GPIO_AF9_CAN2", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_INSTRUCTION_CACHE_ENABLE", + "display": "GPIO_AF9_CAN2", "location": { "column": "9", - "line": "201", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "353", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_INSTRUCTION_CACHE_ENABLE", + "name": "GPIO_AF9_CAN2", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@7161@macro@__HAL_FLASH_INSTRUCTION_CACHE_DISABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@15931@macro@GPIO_AF9_TIM12", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_INSTRUCTION_CACHE_DISABLE", + "display": "GPIO_AF9_TIM12", "location": { "column": "9", - "line": "207", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "354", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_INSTRUCTION_CACHE_DISABLE", + "name": "GPIO_AF9_TIM12", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@7313@macro@__HAL_FLASH_DATA_CACHE_ENABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16018@macro@GPIO_AF9_TIM13", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_DATA_CACHE_ENABLE", + "display": "GPIO_AF9_TIM13", "location": { "column": "9", - "line": "213", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "355", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_DATA_CACHE_ENABLE", + "name": "GPIO_AF9_TIM13", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@7454@macro@__HAL_FLASH_DATA_CACHE_DISABLE", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16105@macro@GPIO_AF9_TIM14", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_DATA_CACHE_DISABLE", + "display": "GPIO_AF9_TIM14", "location": { "column": "9", - "line": "219", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "356", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_DATA_CACHE_DISABLE", + "name": "GPIO_AF9_TIM14", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@7690@macro@__HAL_FLASH_INSTRUCTION_CACHE_RESET", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16235@macro@GPIO_AF10_OTG_FS", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_INSTRUCTION_CACHE_RESET", + "display": "GPIO_AF10_OTG_FS", "location": { "column": "9", - "line": "226", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "361", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_INSTRUCTION_CACHE_RESET", + "name": "GPIO_AF10_OTG_FS", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@8064@macro@__HAL_FLASH_DATA_CACHE_RESET", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16324@macro@GPIO_AF10_OTG_HS", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_DATA_CACHE_RESET", + "display": "GPIO_AF10_OTG_HS", "location": { "column": "9", - "line": "235", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "362", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_DATA_CACHE_RESET", + "name": "GPIO_AF10_OTG_HS", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@8569@macro@__HAL_FLASH_ENABLE_IT", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16456@macro@GPIO_AF11_ETH", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_ENABLE_IT", + "display": "GPIO_AF11_ETH", "location": { "column": "9", - "line": "246", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "367", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_ENABLE_IT", + "name": "GPIO_AF11_ETH", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@8945@macro@__HAL_FLASH_DISABLE_IT", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16590@macro@GPIO_AF12_FSMC", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_DISABLE_IT", + "display": "GPIO_AF12_FSMC", "location": { "column": "9", - "line": "256", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "372", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_DISABLE_IT", + "name": "GPIO_AF12_FSMC", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@9953@macro@__HAL_FLASH_GET_FLAG", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16697@macro@GPIO_AF12_OTG_HS_FS", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_GET_FLAG", + "display": "GPIO_AF12_OTG_HS_FS", "location": { "column": "9", - "line": "273", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "373", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_GET_FLAG", + "name": "GPIO_AF12_OTG_HS_FS", "origin": "user_include", "scope": null }, { - "ID": "c:stm32f4xx_hal_flash.h@10844@macro@__HAL_FLASH_CLEAR_FLAG", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16804@macro@GPIO_AF12_SDIO", "What": "MacroDef", "defdec": "Def", - "display": "__HAL_FLASH_CLEAR_FLAG", + "display": "GPIO_AF12_SDIO", "location": { "column": "9", - "line": "289", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "line": "374", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "__HAL_FLASH_CLEAR_FLAG", + "name": "GPIO_AF12_SDIO", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_FLASH_Program", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_FLASH_Program(uint32_t, uint32_t, uint64_t)", + "ID": "c:stm32f4xx_hal_gpio_ex.h@16954@macro@GPIO_AF13_DCMI", + "What": "MacroDef", + "defdec": "Def", + "display": "GPIO_AF13_DCMI", "location": { - "column": "19", - "line": "306", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_flash.h" + "column": "9", + "line": "379", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\stm32f4xx_hal_gpio_ex.h" }, - "name": "HAL_FLASH_Program", + "name": "GPIO_AF13_DCMI", "origin": "user_include", "scope": null }, { - "ID": "c:@F@HAL_FLASH_Program", - "What": "Function", - "defdec": "Dec", - "display": "HAL_StatusTypeDef HAL_FLASH_Program(uint32_t, uint32_t, uint64_t)", + "ID": "c:stm32f4xx_hal_gpio_ex.h@17084@macro@GPIO_AF15_EVENTOUT", + "What": "MacroDef", + "defdec": "Def", + "display": "GPIO_AF15_EVENTOUT", "location": { - "column": "19", - "line": "306", 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"Function", - "defdec": "Dec", - "display": "void SVC_Handler(void)", + "defdec": "Def", + "display": "void HAL_DBGMCU_DisableDBGSleepMode(void)", "location": { "column": "6", - "line": "54", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "478", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "SVC_Handler", - "origin": "user_include", + "name": "HAL_DBGMCU_DisableDBGSleepMode", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@DebugMon_Handler", + "ID": "c:@F@HAL_DBGMCU_EnableDBGStopMode", "What": "Function", - "defdec": "Dec", - "display": "void DebugMon_Handler(void)", + "defdec": "Def", + "display": "void HAL_DBGMCU_EnableDBGStopMode(void)", "location": { "column": "6", - "line": "55", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "487", + "path": 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"c:@F@HAL_DBGMCU_EnableDBGStandbyMode", "What": "Function", - "defdec": "Dec", - "display": "void SysTick_Handler(void)", + "defdec": "Def", + "display": "void HAL_DBGMCU_EnableDBGStandbyMode(void)", "location": { "column": "6", - "line": "57", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "505", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "SysTick_Handler", - "origin": "user_include", + "name": "HAL_DBGMCU_EnableDBGStandbyMode", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@TIM1_UP_TIM10_IRQHandler", + "ID": "c:@F@HAL_DBGMCU_DisableDBGStandbyMode", "What": "Function", - "defdec": "Dec", - "display": "void TIM1_UP_TIM10_IRQHandler(void)", + "defdec": "Def", + "display": "void HAL_DBGMCU_DisableDBGStandbyMode(void)", "location": { "column": "6", - "line": "58", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "514", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "TIM1_UP_TIM10_IRQHandler", - "origin": "user_include", + "name": "HAL_DBGMCU_DisableDBGStandbyMode", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@USART1_IRQHandler", + "ID": "c:@F@HAL_EnableCompensationCell", "What": "Function", - "defdec": "Dec", - "display": "void USART1_IRQHandler(void)", + "defdec": "Def", + "display": "void HAL_EnableCompensationCell(void)", "location": { "column": "6", - "line": "59", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "525", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "USART1_IRQHandler", - "origin": "user_include", + "name": "HAL_EnableCompensationCell", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@TIM6_DAC_IRQHandler", + "ID": "c:@F@HAL_DisableCompensationCell", "What": "Function", - "defdec": "Dec", - "display": "void TIM6_DAC_IRQHandler(void)", + "defdec": "Def", + "display": "void HAL_DisableCompensationCell(void)", "location": { "column": "6", - "line": "60", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "line": "536", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "TIM6_DAC_IRQHandler", - "origin": "user_include", + "name": "HAL_DisableCompensationCell", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@DMA2_Stream0_IRQHandler", + "ID": "c:@F@HAL_GetUIDw0", "What": "Function", - "defdec": "Dec", - "display": "void DMA2_Stream0_IRQHandler(void)", + "defdec": "Def", + "display": "uint32_t HAL_GetUIDw0(void)", "location": { - "column": "6", - "line": "61", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "column": "10", + "line": "545", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "DMA2_Stream0_IRQHandler", - "origin": "user_include", + "name": "HAL_GetUIDw0", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@DMA2_Stream2_IRQHandler", + "ID": "c:@F@HAL_GetUIDw1", "What": "Function", - "defdec": "Dec", - "display": "void DMA2_Stream2_IRQHandler(void)", + "defdec": "Def", + "display": "uint32_t HAL_GetUIDw1(void)", "location": { - "column": "6", - "line": "62", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "column": "10", + "line": "554", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "DMA2_Stream2_IRQHandler", - "origin": "user_include", + "name": "HAL_GetUIDw1", + "origin": "project_file", "scope": null }, { - "ID": "c:@F@DMA2_Stream7_IRQHandler", + "ID": "c:@F@HAL_GetUIDw2", "What": "Function", - "defdec": "Dec", - "display": "void DMA2_Stream7_IRQHandler(void)", + "defdec": "Def", + "display": "uint32_t HAL_GetUIDw2(void)", "location": { - "column": "6", - "line": "63", - "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Inc\\stm32f4xx_it.h" + "column": "10", + "line": "563", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Drivers\\STM32F4xx_HAL_Driver\\Src\\stm32f4xx_hal.c" }, - "name": "DMA2_Stream7_IRQHandler", - "origin": "user_include", + "name": "HAL_GetUIDw2", + "origin": "project_file", "scope": null }, { @@ -309897,6 +309615,146 @@ "origin": "project_file", "scope": null }, + { + "ID": "c:@SystemCoreClock", + "What": "Variable", + "defdec": "Def", + "display": "SystemCoreClock", + "location": { + "column": "10", + "line": "137", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "SystemCoreClock", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:@AHBPrescTable", + "What": "Variable", + "defdec": "Def", + "display": "AHBPrescTable", + "location": { + "column": "15", + "line": "138", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "AHBPrescTable", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:@APBPrescTable", + "What": "Variable", + "defdec": "Def", + "display": "APBPrescTable", + "location": { + "column": "15", + "line": "139", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "APBPrescTable", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:@F@SystemInit", + "What": "Function", + "defdec": "Def", + "display": "void SystemInit(void)", + "location": { + "column": "6", + "line": "167", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "SystemInit", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:@F@SystemCoreClockUpdate", + "What": "Function", + "defdec": "Def", + "display": "void SystemCoreClockUpdate(void)", + "location": { + "column": "6", + "line": "220", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "SystemCoreClockUpdate", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:system_stm32f4xx.c@8397@F@SystemCoreClockUpdate@tmp", + "What": "Variable", + "defdec": "Def", + "display": "tmp", + "location": { + "column": "12", + "line": "222", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "tmp", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:system_stm32f4xx.c@8397@F@SystemCoreClockUpdate@pllvco", + "What": "Variable", + "defdec": "Dec", + "display": "pllvco", + "location": { + "column": "17", + "line": "222", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "pllvco", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:system_stm32f4xx.c@8397@F@SystemCoreClockUpdate@pllp", + "What": "Variable", + "defdec": "Dec", + "display": "pllp", + "location": { + "column": "25", + "line": "222", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "pllp", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:system_stm32f4xx.c@8397@F@SystemCoreClockUpdate@pllsource", + "What": "Variable", + "defdec": "Dec", + "display": "pllsource", + "location": { + "column": "31", + "line": "222", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "pllsource", + "origin": "project_file", + "scope": null + }, + { + "ID": "c:system_stm32f4xx.c@8397@F@SystemCoreClockUpdate@pllm", + "What": "Variable", + "defdec": "Dec", + "display": "pllm", + "location": { + "column": "42", + "line": "222", + "path": "e:\\Users\\Mortal\\Desktop\\Train_Camp_PLSR\\PLSR\\PLSR\\Core\\Src\\system_stm32f4xx.c" + }, + "name": "pllm", + "origin": "project_file", + "scope": null + }, { "ID": "c:@SA@DMA_Base_Registers", "What": "Struct", diff --git a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part0.pbi b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part0.pbi index 18283fd..13587dd 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part0.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part0.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part1.pbi b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part1.pbi index 62bfca0..568f3c8 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part1.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part1.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part6.pbi b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part6.pbi index 76f60de..5da8f4d 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part6.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part6.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part7.pbi b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part7.pbi index d5c7a14..39195e9 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/test.1_part7.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/test.1_part7.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/tim.o b/PLSR/PLSR/EWARM/test.1/Obj/tim.o index c4a7b1a..6e29621 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/tim.o and b/PLSR/PLSR/EWARM/test.1/Obj/tim.o differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi b/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi index 2b937e6..ddf6094 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi and b/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi differ diff --git a/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi.dep b/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi.dep index c31bb53..9144767 100644 --- a/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi.dep +++ b/PLSR/PLSR/EWARM/test.1/Obj/tim.pbi.dep @@ -1,40 +1,47 @@ -tim.pbi: e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Core\Src\tim.c \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\tim.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc/main.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Core/Inc\stm32f4xx_hal_conf.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_rcc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include\stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\core_cm4.h \ - E:\Software\IAR\arm\inc\c\stdint.h E:\Software\IAR\arm\inc\c\ycheck.h \ - E:\Software\IAR\arm\inc\c\yvals.h \ - E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ - E:\\Software\\IAR\\arm\\inc\\c\\DLib_Config_Full.h \ - E:\Software\IAR\arm\inc\c\DLib_Product.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_version.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/cmsis_compiler.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include\cmsis_iccarm.h \ +tim.pbi: E:\Software\IAR\arm\inc\c\DLib_float_setup.h \ + E:\Software\IAR\arm\inc\c\ycheck.h E:\Software\IAR\arm\inc\c\math.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\usart.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\modbus_log.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\flash_save.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\modbus_crc.h \ + E:\Software\IAR\arm\inc\c\stdarg.h \ + E:\Software\IAR\arm\inc\c\DLib_Product_stdlib.h \ + E:\Software\IAR\arm\inc\c\stdlib.h E:\Software\IAR\arm\inc\c\ctype.h \ + E:\Software\IAR\arm\inc\c\DLib_Product_string.h \ + E:\Software\IAR\arm\inc\c\string.h E:\Software\IAR\arm\inc\c\stdio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + E:\Software\IAR\arm\inc\c\ysizet.h E:\Software\IAR\arm\inc\c\stddef.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\mpu_armv7.h \ E:\Software\IAR\arm\inc\c\iccarm_builtin.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Include/mpu_armv7.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - E:\Software\IAR\arm\inc\c\stddef.h E:\Software\IAR\arm\inc\c\ysizet.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_gpio.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_exti.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_dma.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_cortex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_flash.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_pwr.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_tim.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ - e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM/../Drivers/STM32F4xx_HAL_Driver/Inc\stm32f4xx_hal_uart.h \ - E:\Software\IAR\arm\inc\c\math.h \ - E:\Software\IAR\arm\inc\c\DLib_float_setup.h + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_iccarm.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_compiler.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\cmsis_version.h \ + E:\Software\IAR\arm\inc\c\DLib_Product.h \ + E:\Software\IAR\arm\inc\c\DLib_Defaults.h \ + E:\Software\IAR\arm\inc\c\yvals.h E:\Software\IAR\arm\inc\c\stdint.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Include\core_cm4.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\stm32f4xx_hal_conf.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\main.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\EWARM\..\Core\Inc\tim.h \ + e:\Users\Mortal\Desktop\Train_Camp_PLSR\PLSR\PLSR\Core\Src\tim.c diff --git a/PLSR/PLSR/EWARM/test.1/Obj/ucos_ii.o b/PLSR/PLSR/EWARM/test.1/Obj/ucos_ii.o index 12ab7df..933dfb1 100644 Binary files a/PLSR/PLSR/EWARM/test.1/Obj/ucos_ii.o and b/PLSR/PLSR/EWARM/test.1/Obj/ucos_ii.o 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