训练营PLSR题目
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_ll_usb.c
  4. * @author MCD Application Team
  5. * @brief USB Low Layer HAL module driver.
  6. *
  7. * This file provides firmware functions to manage the following
  8. * functionalities of the USB Peripheral Controller:
  9. * + Initialization/de-initialization functions
  10. * + I/O operation functions
  11. * + Peripheral Control functions
  12. * + Peripheral State functions
  13. *
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * Copyright (c) 2016 STMicroelectronics.
  18. * All rights reserved.
  19. *
  20. * This software is licensed under terms that can be found in the LICENSE file
  21. * in the root directory of this software component.
  22. * If no LICENSE file comes with this software, it is provided AS-IS.
  23. *
  24. ******************************************************************************
  25. @verbatim
  26. ==============================================================================
  27. ##### How to use this driver #####
  28. ==============================================================================
  29. [..]
  30. (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
  31. (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
  32. (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
  33. @endverbatim
  34. ******************************************************************************
  35. */
  36. /* Includes ------------------------------------------------------------------*/
  37. #include "stm32f4xx_hal.h"
  38. /** @addtogroup STM32F4xx_LL_USB_DRIVER
  39. * @{
  40. */
  41. #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
  42. #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
  43. /* Private typedef -----------------------------------------------------------*/
  44. /* Private define ------------------------------------------------------------*/
  45. /* Private macro -------------------------------------------------------------*/
  46. /* Private variables ---------------------------------------------------------*/
  47. /* Private function prototypes -----------------------------------------------*/
  48. /* Private functions ---------------------------------------------------------*/
  49. #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
  50. static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
  51. /* Exported functions --------------------------------------------------------*/
  52. /** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions
  53. * @{
  54. */
  55. /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions
  56. * @brief Initialization and Configuration functions
  57. *
  58. @verbatim
  59. ===============================================================================
  60. ##### Initialization/de-initialization functions #####
  61. ===============================================================================
  62. @endverbatim
  63. * @{
  64. */
  65. /**
  66. * @brief Initializes the USB Core
  67. * @param USBx USB Instance
  68. * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  69. * the configuration information for the specified USBx peripheral.
  70. * @retval HAL status
  71. */
  72. HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
  73. {
  74. HAL_StatusTypeDef ret;
  75. if (cfg.phy_itface == USB_OTG_ULPI_PHY)
  76. {
  77. USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
  78. /* Init The ULPI Interface */
  79. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
  80. /* Select vbus source */
  81. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
  82. if (cfg.use_external_vbus == 1U)
  83. {
  84. USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
  85. }
  86. /* Reset after a PHY select */
  87. ret = USB_CoreReset(USBx);
  88. }
  89. else /* FS interface (embedded Phy) */
  90. {
  91. /* Select FS Embedded PHY */
  92. USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
  93. /* Reset after a PHY select */
  94. ret = USB_CoreReset(USBx);
  95. if (cfg.battery_charging_enable == 0U)
  96. {
  97. /* Activate the USB Transceiver */
  98. USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
  99. }
  100. else
  101. {
  102. /* Deactivate the USB Transceiver */
  103. USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
  104. }
  105. }
  106. if (cfg.dma_enable == 1U)
  107. {
  108. USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
  109. USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
  110. }
  111. return ret;
  112. }
  113. /**
  114. * @brief Set the USB turnaround time
  115. * @param USBx USB Instance
  116. * @param hclk: AHB clock frequency
  117. * @retval USB turnaround time In PHY Clocks number
  118. */
  119. HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,
  120. uint32_t hclk, uint8_t speed)
  121. {
  122. uint32_t UsbTrd;
  123. /* The USBTRD is configured according to the tables below, depending on AHB frequency
  124. used by application. In the low AHB frequency range it is used to stretch enough the USB response
  125. time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
  126. latency to the Data FIFO */
  127. if (speed == USBD_FS_SPEED)
  128. {
  129. if ((hclk >= 14200000U) && (hclk < 15000000U))
  130. {
  131. /* hclk Clock Range between 14.2-15 MHz */
  132. UsbTrd = 0xFU;
  133. }
  134. else if ((hclk >= 15000000U) && (hclk < 16000000U))
  135. {
  136. /* hclk Clock Range between 15-16 MHz */
  137. UsbTrd = 0xEU;
  138. }
  139. else if ((hclk >= 16000000U) && (hclk < 17200000U))
  140. {
  141. /* hclk Clock Range between 16-17.2 MHz */
  142. UsbTrd = 0xDU;
  143. }
  144. else if ((hclk >= 17200000U) && (hclk < 18500000U))
  145. {
  146. /* hclk Clock Range between 17.2-18.5 MHz */
  147. UsbTrd = 0xCU;
  148. }
  149. else if ((hclk >= 18500000U) && (hclk < 20000000U))
  150. {
  151. /* hclk Clock Range between 18.5-20 MHz */
  152. UsbTrd = 0xBU;
  153. }
  154. else if ((hclk >= 20000000U) && (hclk < 21800000U))
  155. {
  156. /* hclk Clock Range between 20-21.8 MHz */
  157. UsbTrd = 0xAU;
  158. }
  159. else if ((hclk >= 21800000U) && (hclk < 24000000U))
  160. {
  161. /* hclk Clock Range between 21.8-24 MHz */
  162. UsbTrd = 0x9U;
  163. }
  164. else if ((hclk >= 24000000U) && (hclk < 27700000U))
  165. {
  166. /* hclk Clock Range between 24-27.7 MHz */
  167. UsbTrd = 0x8U;
  168. }
  169. else if ((hclk >= 27700000U) && (hclk < 32000000U))
  170. {
  171. /* hclk Clock Range between 27.7-32 MHz */
  172. UsbTrd = 0x7U;
  173. }
  174. else /* if(hclk >= 32000000) */
  175. {
  176. /* hclk Clock Range between 32-200 MHz */
  177. UsbTrd = 0x6U;
  178. }
  179. }
  180. else if (speed == USBD_HS_SPEED)
  181. {
  182. UsbTrd = USBD_HS_TRDT_VALUE;
  183. }
  184. else
  185. {
  186. UsbTrd = USBD_DEFAULT_TRDT_VALUE;
  187. }
  188. USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
  189. USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);
  190. return HAL_OK;
  191. }
  192. /**
  193. * @brief USB_EnableGlobalInt
  194. * Enables the controller's Global Int in the AHB Config reg
  195. * @param USBx Selected device
  196. * @retval HAL status
  197. */
  198. HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
  199. {
  200. USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
  201. return HAL_OK;
  202. }
  203. /**
  204. * @brief USB_DisableGlobalInt
  205. * Disable the controller's Global Int in the AHB Config reg
  206. * @param USBx Selected device
  207. * @retval HAL status
  208. */
  209. HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
  210. {
  211. USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
  212. return HAL_OK;
  213. }
  214. /**
  215. * @brief USB_SetCurrentMode Set functional mode
  216. * @param USBx Selected device
  217. * @param mode current core mode
  218. * This parameter can be one of these values:
  219. * @arg USB_DEVICE_MODE Peripheral mode
  220. * @arg USB_HOST_MODE Host mode
  221. * @retval HAL status
  222. */
  223. HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
  224. {
  225. uint32_t ms = 0U;
  226. USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
  227. if (mode == USB_HOST_MODE)
  228. {
  229. USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
  230. do
  231. {
  232. HAL_Delay(1U);
  233. ms++;
  234. } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
  235. }
  236. else if (mode == USB_DEVICE_MODE)
  237. {
  238. USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
  239. do
  240. {
  241. HAL_Delay(1U);
  242. ms++;
  243. } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
  244. }
  245. else
  246. {
  247. return HAL_ERROR;
  248. }
  249. if (ms == 50U)
  250. {
  251. return HAL_ERROR;
  252. }
  253. return HAL_OK;
  254. }
  255. /**
  256. * @brief USB_DevInit Initializes the USB_OTG controller registers
  257. * for device mode
  258. * @param USBx Selected device
  259. * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  260. * the configuration information for the specified USBx peripheral.
  261. * @retval HAL status
  262. */
  263. HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
  264. {
  265. HAL_StatusTypeDef ret = HAL_OK;
  266. uint32_t USBx_BASE = (uint32_t)USBx;
  267. uint32_t i;
  268. for (i = 0U; i < 15U; i++)
  269. {
  270. USBx->DIEPTXF[i] = 0U;
  271. }
  272. #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
  273. /* VBUS Sensing setup */
  274. if (cfg.vbus_sensing_enable == 0U)
  275. {
  276. USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
  277. /* Deactivate VBUS Sensing B */
  278. USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
  279. /* B-peripheral session valid override enable */
  280. USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
  281. USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
  282. }
  283. else
  284. {
  285. /* Enable HW VBUS sensing */
  286. USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
  287. }
  288. #else
  289. /* VBUS Sensing setup */
  290. if (cfg.vbus_sensing_enable == 0U)
  291. {
  292. /*
  293. * Disable HW VBUS sensing. VBUS is internally considered to be always
  294. * at VBUS-Valid level (5V).
  295. */
  296. USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
  297. USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
  298. USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
  299. USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
  300. }
  301. else
  302. {
  303. /* Enable HW VBUS sensing */
  304. USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
  305. USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
  306. }
  307. #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
  308. /* Restart the Phy Clock */
  309. USBx_PCGCCTL = 0U;
  310. /* Device mode configuration */
  311. USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
  312. if (cfg.phy_itface == USB_OTG_ULPI_PHY)
  313. {
  314. if (cfg.speed == USBD_HS_SPEED)
  315. {
  316. /* Set Core speed to High speed mode */
  317. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
  318. }
  319. else
  320. {
  321. /* Set Core speed to Full speed mode */
  322. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
  323. }
  324. }
  325. else
  326. {
  327. /* Set Core speed to Full speed mode */
  328. (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
  329. }
  330. /* Flush the FIFOs */
  331. if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
  332. {
  333. ret = HAL_ERROR;
  334. }
  335. if (USB_FlushRxFifo(USBx) != HAL_OK)
  336. {
  337. ret = HAL_ERROR;
  338. }
  339. /* Clear all pending Device Interrupts */
  340. USBx_DEVICE->DIEPMSK = 0U;
  341. USBx_DEVICE->DOEPMSK = 0U;
  342. USBx_DEVICE->DAINTMSK = 0U;
  343. for (i = 0U; i < cfg.dev_endpoints; i++)
  344. {
  345. if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  346. {
  347. if (i == 0U)
  348. {
  349. USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
  350. }
  351. else
  352. {
  353. USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
  354. }
  355. }
  356. else
  357. {
  358. USBx_INEP(i)->DIEPCTL = 0U;
  359. }
  360. USBx_INEP(i)->DIEPTSIZ = 0U;
  361. USBx_INEP(i)->DIEPINT = 0xFB7FU;
  362. }
  363. for (i = 0U; i < cfg.dev_endpoints; i++)
  364. {
  365. if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  366. {
  367. if (i == 0U)
  368. {
  369. USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
  370. }
  371. else
  372. {
  373. USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
  374. }
  375. }
  376. else
  377. {
  378. USBx_OUTEP(i)->DOEPCTL = 0U;
  379. }
  380. USBx_OUTEP(i)->DOEPTSIZ = 0U;
  381. USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
  382. }
  383. USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
  384. /* Disable all interrupts. */
  385. USBx->GINTMSK = 0U;
  386. /* Clear any pending interrupts */
  387. USBx->GINTSTS = 0xBFFFFFFFU;
  388. /* Enable the common interrupts */
  389. if (cfg.dma_enable == 0U)
  390. {
  391. USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
  392. }
  393. /* Enable interrupts matching to the Device mode ONLY */
  394. USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
  395. USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
  396. USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
  397. USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
  398. if (cfg.Sof_enable != 0U)
  399. {
  400. USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
  401. }
  402. if (cfg.vbus_sensing_enable == 1U)
  403. {
  404. USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
  405. }
  406. return ret;
  407. }
  408. /**
  409. * @brief USB_FlushTxFifo Flush a Tx FIFO
  410. * @param USBx Selected device
  411. * @param num FIFO number
  412. * This parameter can be a value from 1 to 15
  413. 15 means Flush all Tx FIFOs
  414. * @retval HAL status
  415. */
  416. HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
  417. {
  418. __IO uint32_t count = 0U;
  419. /* Wait for AHB master IDLE state. */
  420. do
  421. {
  422. count++;
  423. if (count > 200000U)
  424. {
  425. return HAL_TIMEOUT;
  426. }
  427. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  428. /* Flush TX Fifo */
  429. count = 0U;
  430. USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
  431. do
  432. {
  433. count++;
  434. if (count > 200000U)
  435. {
  436. return HAL_TIMEOUT;
  437. }
  438. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
  439. return HAL_OK;
  440. }
  441. /**
  442. * @brief USB_FlushRxFifo Flush Rx FIFO
  443. * @param USBx Selected device
  444. * @retval HAL status
  445. */
  446. HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
  447. {
  448. __IO uint32_t count = 0U;
  449. /* Wait for AHB master IDLE state. */
  450. do
  451. {
  452. count++;
  453. if (count > 200000U)
  454. {
  455. return HAL_TIMEOUT;
  456. }
  457. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  458. /* Flush RX Fifo */
  459. count = 0U;
  460. USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
  461. do
  462. {
  463. count++;
  464. if (count > 200000U)
  465. {
  466. return HAL_TIMEOUT;
  467. }
  468. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
  469. return HAL_OK;
  470. }
  471. /**
  472. * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register
  473. * depending the PHY type and the enumeration speed of the device.
  474. * @param USBx Selected device
  475. * @param speed device speed
  476. * This parameter can be one of these values:
  477. * @arg USB_OTG_SPEED_HIGH: High speed mode
  478. * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
  479. * @arg USB_OTG_SPEED_FULL: Full speed mode
  480. * @retval Hal status
  481. */
  482. HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
  483. {
  484. uint32_t USBx_BASE = (uint32_t)USBx;
  485. USBx_DEVICE->DCFG |= speed;
  486. return HAL_OK;
  487. }
  488. /**
  489. * @brief USB_GetDevSpeed Return the Dev Speed
  490. * @param USBx Selected device
  491. * @retval speed device speed
  492. * This parameter can be one of these values:
  493. * @arg USBD_HS_SPEED: High speed mode
  494. * @arg USBD_FS_SPEED: Full speed mode
  495. */
  496. uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
  497. {
  498. uint32_t USBx_BASE = (uint32_t)USBx;
  499. uint8_t speed;
  500. uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
  501. if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
  502. {
  503. speed = USBD_HS_SPEED;
  504. }
  505. else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||
  506. (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))
  507. {
  508. speed = USBD_FS_SPEED;
  509. }
  510. else
  511. {
  512. speed = 0xFU;
  513. }
  514. return speed;
  515. }
  516. /**
  517. * @brief Activate and configure an endpoint
  518. * @param USBx Selected device
  519. * @param ep pointer to endpoint structure
  520. * @retval HAL status
  521. */
  522. HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  523. {
  524. uint32_t USBx_BASE = (uint32_t)USBx;
  525. uint32_t epnum = (uint32_t)ep->num;
  526. if (ep->is_in == 1U)
  527. {
  528. USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
  529. if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)
  530. {
  531. USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
  532. ((uint32_t)ep->type << 18) | (epnum << 22) |
  533. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  534. USB_OTG_DIEPCTL_USBAEP;
  535. }
  536. }
  537. else
  538. {
  539. USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
  540. if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
  541. {
  542. USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
  543. ((uint32_t)ep->type << 18) |
  544. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  545. USB_OTG_DOEPCTL_USBAEP;
  546. }
  547. }
  548. return HAL_OK;
  549. }
  550. /**
  551. * @brief Activate and configure a dedicated endpoint
  552. * @param USBx Selected device
  553. * @param ep pointer to endpoint structure
  554. * @retval HAL status
  555. */
  556. HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  557. {
  558. uint32_t USBx_BASE = (uint32_t)USBx;
  559. uint32_t epnum = (uint32_t)ep->num;
  560. /* Read DEPCTLn register */
  561. if (ep->is_in == 1U)
  562. {
  563. if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
  564. {
  565. USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |
  566. ((uint32_t)ep->type << 18) | (epnum << 22) |
  567. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  568. USB_OTG_DIEPCTL_USBAEP;
  569. }
  570. USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));
  571. }
  572. else
  573. {
  574. if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
  575. {
  576. USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |
  577. ((uint32_t)ep->type << 18) | (epnum << 22) |
  578. USB_OTG_DOEPCTL_USBAEP;
  579. }
  580. USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);
  581. }
  582. return HAL_OK;
  583. }
  584. /**
  585. * @brief De-activate and de-initialize an endpoint
  586. * @param USBx Selected device
  587. * @param ep pointer to endpoint structure
  588. * @retval HAL status
  589. */
  590. HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  591. {
  592. uint32_t USBx_BASE = (uint32_t)USBx;
  593. uint32_t epnum = (uint32_t)ep->num;
  594. /* Read DEPCTLn register */
  595. if (ep->is_in == 1U)
  596. {
  597. if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  598. {
  599. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
  600. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
  601. }
  602. USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
  603. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
  604. USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
  605. USB_OTG_DIEPCTL_MPSIZ |
  606. USB_OTG_DIEPCTL_TXFNUM |
  607. USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
  608. USB_OTG_DIEPCTL_EPTYP);
  609. }
  610. else
  611. {
  612. if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  613. {
  614. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
  615. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
  616. }
  617. USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
  618. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
  619. USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
  620. USB_OTG_DOEPCTL_MPSIZ |
  621. USB_OTG_DOEPCTL_SD0PID_SEVNFRM |
  622. USB_OTG_DOEPCTL_EPTYP);
  623. }
  624. return HAL_OK;
  625. }
  626. /**
  627. * @brief De-activate and de-initialize a dedicated endpoint
  628. * @param USBx Selected device
  629. * @param ep pointer to endpoint structure
  630. * @retval HAL status
  631. */
  632. HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  633. {
  634. uint32_t USBx_BASE = (uint32_t)USBx;
  635. uint32_t epnum = (uint32_t)ep->num;
  636. /* Read DEPCTLn register */
  637. if (ep->is_in == 1U)
  638. {
  639. if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  640. {
  641. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
  642. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
  643. }
  644. USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
  645. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
  646. }
  647. else
  648. {
  649. if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  650. {
  651. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
  652. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
  653. }
  654. USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
  655. USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
  656. }
  657. return HAL_OK;
  658. }
  659. /**
  660. * @brief USB_EPStartXfer : setup and starts a transfer over an EP
  661. * @param USBx Selected device
  662. * @param ep pointer to endpoint structure
  663. * @param dma USB dma enabled or disabled
  664. * This parameter can be one of these values:
  665. * 0 : DMA feature not used
  666. * 1 : DMA feature used
  667. * @retval HAL status
  668. */
  669. HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
  670. {
  671. uint32_t USBx_BASE = (uint32_t)USBx;
  672. uint32_t epnum = (uint32_t)ep->num;
  673. uint16_t pktcnt;
  674. /* IN endpoint */
  675. if (ep->is_in == 1U)
  676. {
  677. /* Zero Length Packet? */
  678. if (ep->xfer_len == 0U)
  679. {
  680. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  681. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  682. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  683. }
  684. else
  685. {
  686. /* Program the transfer size and packet count
  687. * as follows: xfersize = N * maxpacket +
  688. * short_packet pktcnt = N + (short_packet
  689. * exist ? 1 : 0)
  690. */
  691. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  692. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  693. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
  694. (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
  695. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
  696. if (ep->type == EP_TYPE_ISOC)
  697. {
  698. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
  699. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
  700. }
  701. }
  702. if (dma == 1U)
  703. {
  704. if ((uint32_t)ep->dma_addr != 0U)
  705. {
  706. USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
  707. }
  708. if (ep->type == EP_TYPE_ISOC)
  709. {
  710. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  711. {
  712. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
  713. }
  714. else
  715. {
  716. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
  717. }
  718. }
  719. /* EP enable, IN data in FIFO */
  720. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  721. }
  722. else
  723. {
  724. /* EP enable, IN data in FIFO */
  725. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  726. if (ep->type != EP_TYPE_ISOC)
  727. {
  728. /* Enable the Tx FIFO Empty Interrupt for this EP */
  729. if (ep->xfer_len > 0U)
  730. {
  731. USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
  732. }
  733. }
  734. else
  735. {
  736. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  737. {
  738. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
  739. }
  740. else
  741. {
  742. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
  743. }
  744. (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);
  745. }
  746. }
  747. }
  748. else /* OUT endpoint */
  749. {
  750. /* Program the transfer size and packet count as follows:
  751. * pktcnt = N
  752. * xfersize = N * maxpacket
  753. */
  754. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
  755. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
  756. if (ep->xfer_len == 0U)
  757. {
  758. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
  759. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  760. }
  761. else
  762. {
  763. pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
  764. ep->xfer_size = ep->maxpacket * pktcnt;
  765. USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
  766. USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
  767. }
  768. if (dma == 1U)
  769. {
  770. if ((uint32_t)ep->xfer_buff != 0U)
  771. {
  772. USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
  773. }
  774. }
  775. if (ep->type == EP_TYPE_ISOC)
  776. {
  777. if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
  778. {
  779. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
  780. }
  781. else
  782. {
  783. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
  784. }
  785. }
  786. /* EP enable */
  787. USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
  788. }
  789. return HAL_OK;
  790. }
  791. /**
  792. * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
  793. * @param USBx Selected device
  794. * @param ep pointer to endpoint structure
  795. * @param dma USB dma enabled or disabled
  796. * This parameter can be one of these values:
  797. * 0 : DMA feature not used
  798. * 1 : DMA feature used
  799. * @retval HAL status
  800. */
  801. HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
  802. {
  803. uint32_t USBx_BASE = (uint32_t)USBx;
  804. uint32_t epnum = (uint32_t)ep->num;
  805. /* IN endpoint */
  806. if (ep->is_in == 1U)
  807. {
  808. /* Zero Length Packet? */
  809. if (ep->xfer_len == 0U)
  810. {
  811. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  812. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  813. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  814. }
  815. else
  816. {
  817. /* Program the transfer size and packet count
  818. * as follows: xfersize = N * maxpacket +
  819. * short_packet pktcnt = N + (short_packet
  820. * exist ? 1 : 0)
  821. */
  822. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
  823. USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
  824. if (ep->xfer_len > ep->maxpacket)
  825. {
  826. ep->xfer_len = ep->maxpacket;
  827. }
  828. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
  829. USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
  830. }
  831. if (dma == 1U)
  832. {
  833. if ((uint32_t)ep->dma_addr != 0U)
  834. {
  835. USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
  836. }
  837. /* EP enable, IN data in FIFO */
  838. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  839. }
  840. else
  841. {
  842. /* EP enable, IN data in FIFO */
  843. USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
  844. /* Enable the Tx FIFO Empty Interrupt for this EP */
  845. if (ep->xfer_len > 0U)
  846. {
  847. USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
  848. }
  849. }
  850. }
  851. else /* OUT endpoint */
  852. {
  853. /* Program the transfer size and packet count as follows:
  854. * pktcnt = N
  855. * xfersize = N * maxpacket
  856. */
  857. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
  858. USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
  859. if (ep->xfer_len > 0U)
  860. {
  861. ep->xfer_len = ep->maxpacket;
  862. }
  863. /* Store transfer size, for EP0 this is equal to endpoint max packet size */
  864. ep->xfer_size = ep->maxpacket;
  865. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  866. USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
  867. if (dma == 1U)
  868. {
  869. if ((uint32_t)ep->xfer_buff != 0U)
  870. {
  871. USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
  872. }
  873. }
  874. /* EP enable */
  875. USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
  876. }
  877. return HAL_OK;
  878. }
  879. /**
  880. * @brief USB_EPStoptXfer Stop transfer on an EP
  881. * @param USBx usb device instance
  882. * @param ep pointer to endpoint structure
  883. * @retval HAL status
  884. */
  885. HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  886. {
  887. __IO uint32_t count = 0U;
  888. HAL_StatusTypeDef ret = HAL_OK;
  889. uint32_t USBx_BASE = (uint32_t)USBx;
  890. /* IN endpoint */
  891. if (ep->is_in == 1U)
  892. {
  893. /* EP enable, IN data in FIFO */
  894. if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
  895. {
  896. USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
  897. USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
  898. do
  899. {
  900. count++;
  901. if (count > 10000U)
  902. {
  903. ret = HAL_ERROR;
  904. break;
  905. }
  906. } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA);
  907. }
  908. }
  909. else /* OUT endpoint */
  910. {
  911. if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  912. {
  913. USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
  914. USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
  915. do
  916. {
  917. count++;
  918. if (count > 10000U)
  919. {
  920. ret = HAL_ERROR;
  921. break;
  922. }
  923. } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA);
  924. }
  925. }
  926. return ret;
  927. }
  928. /**
  929. * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
  930. * with the EP/channel
  931. * @param USBx Selected device
  932. * @param src pointer to source buffer
  933. * @param ch_ep_num endpoint or host channel number
  934. * @param len Number of bytes to write
  935. * @param dma USB dma enabled or disabled
  936. * This parameter can be one of these values:
  937. * 0 : DMA feature not used
  938. * 1 : DMA feature used
  939. * @retval HAL status
  940. */
  941. HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
  942. uint8_t ch_ep_num, uint16_t len, uint8_t dma)
  943. {
  944. uint32_t USBx_BASE = (uint32_t)USBx;
  945. uint8_t *pSrc = src;
  946. uint32_t count32b;
  947. uint32_t i;
  948. if (dma == 0U)
  949. {
  950. count32b = ((uint32_t)len + 3U) / 4U;
  951. for (i = 0U; i < count32b; i++)
  952. {
  953. USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
  954. pSrc++;
  955. pSrc++;
  956. pSrc++;
  957. pSrc++;
  958. }
  959. }
  960. return HAL_OK;
  961. }
  962. /**
  963. * @brief USB_ReadPacket : read a packet from the RX FIFO
  964. * @param USBx Selected device
  965. * @param dest source pointer
  966. * @param len Number of bytes to read
  967. * @retval pointer to destination buffer
  968. */
  969. void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
  970. {
  971. uint32_t USBx_BASE = (uint32_t)USBx;
  972. uint8_t *pDest = dest;
  973. uint32_t pData;
  974. uint32_t i;
  975. uint32_t count32b = (uint32_t)len >> 2U;
  976. uint16_t remaining_bytes = len % 4U;
  977. for (i = 0U; i < count32b; i++)
  978. {
  979. __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
  980. pDest++;
  981. pDest++;
  982. pDest++;
  983. pDest++;
  984. }
  985. /* When Number of data is not word aligned, read the remaining byte */
  986. if (remaining_bytes != 0U)
  987. {
  988. i = 0U;
  989. __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
  990. do
  991. {
  992. *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
  993. i++;
  994. pDest++;
  995. remaining_bytes--;
  996. } while (remaining_bytes != 0U);
  997. }
  998. return ((void *)pDest);
  999. }
  1000. /**
  1001. * @brief USB_EPSetStall : set a stall condition over an EP
  1002. * @param USBx Selected device
  1003. * @param ep pointer to endpoint structure
  1004. * @retval HAL status
  1005. */
  1006. HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  1007. {
  1008. uint32_t USBx_BASE = (uint32_t)USBx;
  1009. uint32_t epnum = (uint32_t)ep->num;
  1010. if (ep->is_in == 1U)
  1011. {
  1012. if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))
  1013. {
  1014. USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
  1015. }
  1016. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
  1017. }
  1018. else
  1019. {
  1020. if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))
  1021. {
  1022. USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
  1023. }
  1024. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
  1025. }
  1026. return HAL_OK;
  1027. }
  1028. /**
  1029. * @brief USB_EPClearStall : Clear a stall condition over an EP
  1030. * @param USBx Selected device
  1031. * @param ep pointer to endpoint structure
  1032. * @retval HAL status
  1033. */
  1034. HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
  1035. {
  1036. uint32_t USBx_BASE = (uint32_t)USBx;
  1037. uint32_t epnum = (uint32_t)ep->num;
  1038. if (ep->is_in == 1U)
  1039. {
  1040. USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
  1041. if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
  1042. {
  1043. USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
  1044. }
  1045. }
  1046. else
  1047. {
  1048. USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
  1049. if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))
  1050. {
  1051. USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
  1052. }
  1053. }
  1054. return HAL_OK;
  1055. }
  1056. /**
  1057. * @brief USB_StopDevice : Stop the usb device mode
  1058. * @param USBx Selected device
  1059. * @retval HAL status
  1060. */
  1061. HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
  1062. {
  1063. HAL_StatusTypeDef ret;
  1064. uint32_t USBx_BASE = (uint32_t)USBx;
  1065. uint32_t i;
  1066. /* Clear Pending interrupt */
  1067. for (i = 0U; i < 15U; i++)
  1068. {
  1069. USBx_INEP(i)->DIEPINT = 0xFB7FU;
  1070. USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
  1071. }
  1072. /* Clear interrupt masks */
  1073. USBx_DEVICE->DIEPMSK = 0U;
  1074. USBx_DEVICE->DOEPMSK = 0U;
  1075. USBx_DEVICE->DAINTMSK = 0U;
  1076. /* Flush the FIFO */
  1077. ret = USB_FlushRxFifo(USBx);
  1078. if (ret != HAL_OK)
  1079. {
  1080. return ret;
  1081. }
  1082. ret = USB_FlushTxFifo(USBx, 0x10U);
  1083. if (ret != HAL_OK)
  1084. {
  1085. return ret;
  1086. }
  1087. return ret;
  1088. }
  1089. /**
  1090. * @brief USB_SetDevAddress : Stop the usb device mode
  1091. * @param USBx Selected device
  1092. * @param address new device address to be assigned
  1093. * This parameter can be a value from 0 to 255
  1094. * @retval HAL status
  1095. */
  1096. HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
  1097. {
  1098. uint32_t USBx_BASE = (uint32_t)USBx;
  1099. USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
  1100. USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;
  1101. return HAL_OK;
  1102. }
  1103. /**
  1104. * @brief USB_DevConnect : Connect the USB device by enabling Rpu
  1105. * @param USBx Selected device
  1106. * @retval HAL status
  1107. */
  1108. HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
  1109. {
  1110. uint32_t USBx_BASE = (uint32_t)USBx;
  1111. /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  1112. USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
  1113. USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
  1114. return HAL_OK;
  1115. }
  1116. /**
  1117. * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
  1118. * @param USBx Selected device
  1119. * @retval HAL status
  1120. */
  1121. HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
  1122. {
  1123. uint32_t USBx_BASE = (uint32_t)USBx;
  1124. /* In case phy is stopped, ensure to ungate and restore the phy CLK */
  1125. USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
  1126. USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
  1127. return HAL_OK;
  1128. }
  1129. /**
  1130. * @brief USB_ReadInterrupts: return the global USB interrupt status
  1131. * @param USBx Selected device
  1132. * @retval HAL status
  1133. */
  1134. uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
  1135. {
  1136. uint32_t tmpreg;
  1137. tmpreg = USBx->GINTSTS;
  1138. tmpreg &= USBx->GINTMSK;
  1139. return tmpreg;
  1140. }
  1141. /**
  1142. * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
  1143. * @param USBx Selected device
  1144. * @retval HAL status
  1145. */
  1146. uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
  1147. {
  1148. uint32_t USBx_BASE = (uint32_t)USBx;
  1149. uint32_t tmpreg;
  1150. tmpreg = USBx_DEVICE->DAINT;
  1151. tmpreg &= USBx_DEVICE->DAINTMSK;
  1152. return ((tmpreg & 0xffff0000U) >> 16);
  1153. }
  1154. /**
  1155. * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
  1156. * @param USBx Selected device
  1157. * @retval HAL status
  1158. */
  1159. uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
  1160. {
  1161. uint32_t USBx_BASE = (uint32_t)USBx;
  1162. uint32_t tmpreg;
  1163. tmpreg = USBx_DEVICE->DAINT;
  1164. tmpreg &= USBx_DEVICE->DAINTMSK;
  1165. return ((tmpreg & 0xFFFFU));
  1166. }
  1167. /**
  1168. * @brief Returns Device OUT EP Interrupt register
  1169. * @param USBx Selected device
  1170. * @param epnum endpoint number
  1171. * This parameter can be a value from 0 to 15
  1172. * @retval Device OUT EP Interrupt register
  1173. */
  1174. uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
  1175. {
  1176. uint32_t USBx_BASE = (uint32_t)USBx;
  1177. uint32_t tmpreg;
  1178. tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
  1179. tmpreg &= USBx_DEVICE->DOEPMSK;
  1180. return tmpreg;
  1181. }
  1182. /**
  1183. * @brief Returns Device IN EP Interrupt register
  1184. * @param USBx Selected device
  1185. * @param epnum endpoint number
  1186. * This parameter can be a value from 0 to 15
  1187. * @retval Device IN EP Interrupt register
  1188. */
  1189. uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
  1190. {
  1191. uint32_t USBx_BASE = (uint32_t)USBx;
  1192. uint32_t tmpreg;
  1193. uint32_t msk;
  1194. uint32_t emp;
  1195. msk = USBx_DEVICE->DIEPMSK;
  1196. emp = USBx_DEVICE->DIEPEMPMSK;
  1197. msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;
  1198. tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;
  1199. return tmpreg;
  1200. }
  1201. /**
  1202. * @brief USB_ClearInterrupts: clear a USB interrupt
  1203. * @param USBx Selected device
  1204. * @param interrupt flag
  1205. * @retval None
  1206. */
  1207. void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
  1208. {
  1209. USBx->GINTSTS |= interrupt;
  1210. }
  1211. /**
  1212. * @brief Returns USB core mode
  1213. * @param USBx Selected device
  1214. * @retval return core mode : Host or Device
  1215. * This parameter can be one of these values:
  1216. * 0 : Host
  1217. * 1 : Device
  1218. */
  1219. uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
  1220. {
  1221. return ((USBx->GINTSTS) & 0x1U);
  1222. }
  1223. /**
  1224. * @brief Activate EP0 for Setup transactions
  1225. * @param USBx Selected device
  1226. * @retval HAL status
  1227. */
  1228. HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
  1229. {
  1230. uint32_t USBx_BASE = (uint32_t)USBx;
  1231. /* Set the MPS of the IN EP0 to 64 bytes */
  1232. USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
  1233. USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
  1234. return HAL_OK;
  1235. }
  1236. /**
  1237. * @brief Prepare the EP0 to start the first control setup
  1238. * @param USBx Selected device
  1239. * @param dma USB dma enabled or disabled
  1240. * This parameter can be one of these values:
  1241. * 0 : DMA feature not used
  1242. * 1 : DMA feature used
  1243. * @param psetup pointer to setup packet
  1244. * @retval HAL status
  1245. */
  1246. HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
  1247. {
  1248. uint32_t USBx_BASE = (uint32_t)USBx;
  1249. uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
  1250. if (gSNPSiD > USB_OTG_CORE_ID_300A)
  1251. {
  1252. if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
  1253. {
  1254. return HAL_OK;
  1255. }
  1256. }
  1257. USBx_OUTEP(0U)->DOEPTSIZ = 0U;
  1258. USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
  1259. USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
  1260. USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
  1261. if (dma == 1U)
  1262. {
  1263. USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
  1264. /* EP enable */
  1265. USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;
  1266. }
  1267. return HAL_OK;
  1268. }
  1269. /**
  1270. * @brief Reset the USB Core (needed after USB clock settings change)
  1271. * @param USBx Selected device
  1272. * @retval HAL status
  1273. */
  1274. static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
  1275. {
  1276. __IO uint32_t count = 0U;
  1277. /* Wait for AHB master IDLE state. */
  1278. do
  1279. {
  1280. count++;
  1281. if (count > 200000U)
  1282. {
  1283. return HAL_TIMEOUT;
  1284. }
  1285. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
  1286. /* Core Soft Reset */
  1287. count = 0U;
  1288. USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
  1289. do
  1290. {
  1291. count++;
  1292. if (count > 200000U)
  1293. {
  1294. return HAL_TIMEOUT;
  1295. }
  1296. } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
  1297. return HAL_OK;
  1298. }
  1299. /**
  1300. * @brief USB_HostInit : Initializes the USB OTG controller registers
  1301. * for Host mode
  1302. * @param USBx Selected device
  1303. * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
  1304. * the configuration information for the specified USBx peripheral.
  1305. * @retval HAL status
  1306. */
  1307. HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
  1308. {
  1309. HAL_StatusTypeDef ret = HAL_OK;
  1310. uint32_t USBx_BASE = (uint32_t)USBx;
  1311. uint32_t i;
  1312. /* Restart the Phy Clock */
  1313. USBx_PCGCCTL = 0U;
  1314. #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
  1315. /* Disable HW VBUS sensing */
  1316. USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);
  1317. #else
  1318. /*
  1319. * Disable HW VBUS sensing. VBUS is internally considered to be always
  1320. * at VBUS-Valid level (5V).
  1321. */
  1322. USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
  1323. USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
  1324. USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
  1325. #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
  1326. #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
  1327. /* Disable Battery chargin detector */
  1328. USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
  1329. #endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
  1330. if ((USBx->CID & (0x1U << 8)) != 0U)
  1331. {
  1332. if (cfg.speed == USBH_FSLS_SPEED)
  1333. {
  1334. /* Force Device Enumeration to FS/LS mode only */
  1335. USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
  1336. }
  1337. else
  1338. {
  1339. /* Set default Max speed support */
  1340. USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
  1341. }
  1342. }
  1343. else
  1344. {
  1345. /* Set default Max speed support */
  1346. USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
  1347. }
  1348. /* Make sure the FIFOs are flushed. */
  1349. if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
  1350. {
  1351. ret = HAL_ERROR;
  1352. }
  1353. if (USB_FlushRxFifo(USBx) != HAL_OK)
  1354. {
  1355. ret = HAL_ERROR;
  1356. }
  1357. /* Clear all pending HC Interrupts */
  1358. for (i = 0U; i < cfg.Host_channels; i++)
  1359. {
  1360. USBx_HC(i)->HCINT = 0xFFFFFFFFU;
  1361. USBx_HC(i)->HCINTMSK = 0U;
  1362. }
  1363. /* Disable all interrupts. */
  1364. USBx->GINTMSK = 0U;
  1365. /* Clear any pending interrupts */
  1366. USBx->GINTSTS = 0xFFFFFFFFU;
  1367. if ((USBx->CID & (0x1U << 8)) != 0U)
  1368. {
  1369. /* set Rx FIFO size */
  1370. USBx->GRXFSIZ = 0x200U;
  1371. USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
  1372. USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
  1373. }
  1374. else
  1375. {
  1376. /* set Rx FIFO size */
  1377. USBx->GRXFSIZ = 0x80U;
  1378. USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
  1379. USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
  1380. }
  1381. /* Enable the common interrupts */
  1382. if (cfg.dma_enable == 0U)
  1383. {
  1384. USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
  1385. }
  1386. /* Enable interrupts matching to the Host mode ONLY */
  1387. USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
  1388. USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
  1389. USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
  1390. return ret;
  1391. }
  1392. /**
  1393. * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
  1394. * HCFG register on the PHY type and set the right frame interval
  1395. * @param USBx Selected device
  1396. * @param freq clock frequency
  1397. * This parameter can be one of these values:
  1398. * HCFG_48_MHZ : Full Speed 48 MHz Clock
  1399. * HCFG_6_MHZ : Low Speed 6 MHz Clock
  1400. * @retval HAL status
  1401. */
  1402. HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
  1403. {
  1404. uint32_t USBx_BASE = (uint32_t)USBx;
  1405. USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
  1406. USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
  1407. if (freq == HCFG_48_MHZ)
  1408. {
  1409. USBx_HOST->HFIR = 48000U;
  1410. }
  1411. else if (freq == HCFG_6_MHZ)
  1412. {
  1413. USBx_HOST->HFIR = 6000U;
  1414. }
  1415. else
  1416. {
  1417. /* ... */
  1418. }
  1419. return HAL_OK;
  1420. }
  1421. /**
  1422. * @brief USB_OTG_ResetPort : Reset Host Port
  1423. * @param USBx Selected device
  1424. * @retval HAL status
  1425. * @note (1)The application must wait at least 10 ms
  1426. * before clearing the reset bit.
  1427. */
  1428. HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
  1429. {
  1430. uint32_t USBx_BASE = (uint32_t)USBx;
  1431. __IO uint32_t hprt0 = 0U;
  1432. hprt0 = USBx_HPRT0;
  1433. hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
  1434. USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
  1435. USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
  1436. HAL_Delay(100U); /* See Note #1 */
  1437. USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
  1438. HAL_Delay(10U);
  1439. return HAL_OK;
  1440. }
  1441. /**
  1442. * @brief USB_DriveVbus : activate or de-activate vbus
  1443. * @param state VBUS state
  1444. * This parameter can be one of these values:
  1445. * 0 : Deactivate VBUS
  1446. * 1 : Activate VBUS
  1447. * @retval HAL status
  1448. */
  1449. HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
  1450. {
  1451. uint32_t USBx_BASE = (uint32_t)USBx;
  1452. __IO uint32_t hprt0 = 0U;
  1453. hprt0 = USBx_HPRT0;
  1454. hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
  1455. USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
  1456. if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
  1457. {
  1458. USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
  1459. }
  1460. if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
  1461. {
  1462. USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
  1463. }
  1464. return HAL_OK;
  1465. }
  1466. /**
  1467. * @brief Return Host Core speed
  1468. * @param USBx Selected device
  1469. * @retval speed : Host speed
  1470. * This parameter can be one of these values:
  1471. * @arg HCD_SPEED_HIGH: High speed mode
  1472. * @arg HCD_SPEED_FULL: Full speed mode
  1473. * @arg HCD_SPEED_LOW: Low speed mode
  1474. */
  1475. uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
  1476. {
  1477. uint32_t USBx_BASE = (uint32_t)USBx;
  1478. __IO uint32_t hprt0 = 0U;
  1479. hprt0 = USBx_HPRT0;
  1480. return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
  1481. }
  1482. /**
  1483. * @brief Return Host Current Frame number
  1484. * @param USBx Selected device
  1485. * @retval current frame number
  1486. */
  1487. uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
  1488. {
  1489. uint32_t USBx_BASE = (uint32_t)USBx;
  1490. return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
  1491. }
  1492. /**
  1493. * @brief Initialize a host channel
  1494. * @param USBx Selected device
  1495. * @param ch_num Channel number
  1496. * This parameter can be a value from 1 to 15
  1497. * @param epnum Endpoint number
  1498. * This parameter can be a value from 1 to 15
  1499. * @param dev_address Current device address
  1500. * This parameter can be a value from 0 to 255
  1501. * @param speed Current device speed
  1502. * This parameter can be one of these values:
  1503. * @arg USB_OTG_SPEED_HIGH: High speed mode
  1504. * @arg USB_OTG_SPEED_FULL: Full speed mode
  1505. * @arg USB_OTG_SPEED_LOW: Low speed mode
  1506. * @param ep_type Endpoint Type
  1507. * This parameter can be one of these values:
  1508. * @arg EP_TYPE_CTRL: Control type
  1509. * @arg EP_TYPE_ISOC: Isochronous type
  1510. * @arg EP_TYPE_BULK: Bulk type
  1511. * @arg EP_TYPE_INTR: Interrupt type
  1512. * @param mps Max Packet Size
  1513. * This parameter can be a value from 0 to 32K
  1514. * @retval HAL state
  1515. */
  1516. HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
  1517. uint8_t epnum, uint8_t dev_address, uint8_t speed,
  1518. uint8_t ep_type, uint16_t mps)
  1519. {
  1520. HAL_StatusTypeDef ret = HAL_OK;
  1521. uint32_t USBx_BASE = (uint32_t)USBx;
  1522. uint32_t HCcharEpDir;
  1523. uint32_t HCcharLowSpeed;
  1524. uint32_t HostCoreSpeed;
  1525. /* Clear old interrupt conditions for this host channel. */
  1526. USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
  1527. /* Enable channel interrupts required for this transfer. */
  1528. switch (ep_type)
  1529. {
  1530. case EP_TYPE_CTRL:
  1531. case EP_TYPE_BULK:
  1532. USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
  1533. USB_OTG_HCINTMSK_STALLM |
  1534. USB_OTG_HCINTMSK_TXERRM |
  1535. USB_OTG_HCINTMSK_DTERRM |
  1536. USB_OTG_HCINTMSK_AHBERR |
  1537. USB_OTG_HCINTMSK_NAKM;
  1538. if ((epnum & 0x80U) == 0x80U)
  1539. {
  1540. USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
  1541. }
  1542. else
  1543. {
  1544. if ((USBx->CID & (0x1U << 8)) != 0U)
  1545. {
  1546. USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
  1547. USB_OTG_HCINTMSK_ACKM;
  1548. }
  1549. }
  1550. break;
  1551. case EP_TYPE_INTR:
  1552. USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
  1553. USB_OTG_HCINTMSK_STALLM |
  1554. USB_OTG_HCINTMSK_TXERRM |
  1555. USB_OTG_HCINTMSK_DTERRM |
  1556. USB_OTG_HCINTMSK_NAKM |
  1557. USB_OTG_HCINTMSK_AHBERR |
  1558. USB_OTG_HCINTMSK_FRMORM;
  1559. if ((epnum & 0x80U) == 0x80U)
  1560. {
  1561. USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
  1562. }
  1563. break;
  1564. case EP_TYPE_ISOC:
  1565. USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
  1566. USB_OTG_HCINTMSK_ACKM |
  1567. USB_OTG_HCINTMSK_AHBERR |
  1568. USB_OTG_HCINTMSK_FRMORM;
  1569. if ((epnum & 0x80U) == 0x80U)
  1570. {
  1571. USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
  1572. }
  1573. break;
  1574. default:
  1575. ret = HAL_ERROR;
  1576. break;
  1577. }
  1578. /* Enable host channel Halt interrupt */
  1579. USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
  1580. /* Enable the top level host channel interrupt. */
  1581. USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
  1582. /* Make sure host channel interrupts are enabled. */
  1583. USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
  1584. /* Program the HCCHAR register */
  1585. if ((epnum & 0x80U) == 0x80U)
  1586. {
  1587. HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
  1588. }
  1589. else
  1590. {
  1591. HCcharEpDir = 0U;
  1592. }
  1593. HostCoreSpeed = USB_GetHostSpeed(USBx);
  1594. /* LS device plugged to HUB */
  1595. if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
  1596. {
  1597. HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
  1598. }
  1599. else
  1600. {
  1601. HCcharLowSpeed = 0U;
  1602. }
  1603. USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
  1604. ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
  1605. (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
  1606. ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
  1607. if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
  1608. {
  1609. USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
  1610. }
  1611. return ret;
  1612. }
  1613. /**
  1614. * @brief Start a transfer over a host channel
  1615. * @param USBx Selected device
  1616. * @param hc pointer to host channel structure
  1617. * @param dma USB dma enabled or disabled
  1618. * This parameter can be one of these values:
  1619. * 0 : DMA feature not used
  1620. * 1 : DMA feature used
  1621. * @retval HAL state
  1622. */
  1623. HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
  1624. {
  1625. uint32_t USBx_BASE = (uint32_t)USBx;
  1626. uint32_t ch_num = (uint32_t)hc->ch_num;
  1627. __IO uint32_t tmpreg;
  1628. uint8_t is_oddframe;
  1629. uint16_t len_words;
  1630. uint16_t num_packets;
  1631. uint16_t max_hc_pkt_count = 256U;
  1632. if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
  1633. {
  1634. /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
  1635. if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
  1636. {
  1637. USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
  1638. USB_OTG_HCINTMSK_ACKM |
  1639. USB_OTG_HCINTMSK_NAKM);
  1640. }
  1641. if ((dma == 0U) && (hc->do_ping == 1U))
  1642. {
  1643. (void)USB_DoPing(USBx, hc->ch_num);
  1644. return HAL_OK;
  1645. }
  1646. }
  1647. /* Compute the expected number of packets associated to the transfer */
  1648. if (hc->xfer_len > 0U)
  1649. {
  1650. num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
  1651. if (num_packets > max_hc_pkt_count)
  1652. {
  1653. num_packets = max_hc_pkt_count;
  1654. hc->XferSize = (uint32_t)num_packets * hc->max_packet;
  1655. }
  1656. }
  1657. else
  1658. {
  1659. num_packets = 1U;
  1660. }
  1661. /*
  1662. * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
  1663. * max_packet size.
  1664. */
  1665. if (hc->ep_is_in != 0U)
  1666. {
  1667. hc->XferSize = (uint32_t)num_packets * hc->max_packet;
  1668. }
  1669. else
  1670. {
  1671. hc->XferSize = hc->xfer_len;
  1672. }
  1673. /* Initialize the HCTSIZn register */
  1674. USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
  1675. (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
  1676. (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
  1677. if (dma != 0U)
  1678. {
  1679. /* xfer_buff MUST be 32-bits aligned */
  1680. USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
  1681. }
  1682. is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
  1683. USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
  1684. USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
  1685. /* Set host channel enable */
  1686. tmpreg = USBx_HC(ch_num)->HCCHAR;
  1687. tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
  1688. /* make sure to set the correct ep direction */
  1689. if (hc->ep_is_in != 0U)
  1690. {
  1691. tmpreg |= USB_OTG_HCCHAR_EPDIR;
  1692. }
  1693. else
  1694. {
  1695. tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
  1696. }
  1697. tmpreg |= USB_OTG_HCCHAR_CHENA;
  1698. USBx_HC(ch_num)->HCCHAR = tmpreg;
  1699. if (dma != 0U) /* dma mode */
  1700. {
  1701. return HAL_OK;
  1702. }
  1703. if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
  1704. {
  1705. switch (hc->ep_type)
  1706. {
  1707. /* Non periodic transfer */
  1708. case EP_TYPE_CTRL:
  1709. case EP_TYPE_BULK:
  1710. len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
  1711. /* check if there is enough space in FIFO space */
  1712. if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
  1713. {
  1714. /* need to process data in nptxfempty interrupt */
  1715. USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
  1716. }
  1717. break;
  1718. /* Periodic transfer */
  1719. case EP_TYPE_INTR:
  1720. case EP_TYPE_ISOC:
  1721. len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
  1722. /* check if there is enough space in FIFO space */
  1723. if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
  1724. {
  1725. /* need to process data in ptxfempty interrupt */
  1726. USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
  1727. }
  1728. break;
  1729. default:
  1730. break;
  1731. }
  1732. /* Write packet into the Tx FIFO. */
  1733. (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
  1734. }
  1735. return HAL_OK;
  1736. }
  1737. /**
  1738. * @brief Read all host channel interrupts status
  1739. * @param USBx Selected device
  1740. * @retval HAL state
  1741. */
  1742. uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
  1743. {
  1744. uint32_t USBx_BASE = (uint32_t)USBx;
  1745. return ((USBx_HOST->HAINT) & 0xFFFFU);
  1746. }
  1747. /**
  1748. * @brief Halt a host channel
  1749. * @param USBx Selected device
  1750. * @param hc_num Host Channel number
  1751. * This parameter can be a value from 1 to 15
  1752. * @retval HAL state
  1753. */
  1754. HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
  1755. {
  1756. uint32_t USBx_BASE = (uint32_t)USBx;
  1757. uint32_t hcnum = (uint32_t)hc_num;
  1758. __IO uint32_t count = 0U;
  1759. uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
  1760. uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
  1761. if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
  1762. (ChannelEna == 0U))
  1763. {
  1764. return HAL_OK;
  1765. }
  1766. /* Check for space in the request queue to issue the halt. */
  1767. if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
  1768. {
  1769. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
  1770. if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
  1771. {
  1772. if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
  1773. {
  1774. USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
  1775. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
  1776. do
  1777. {
  1778. count++;
  1779. if (count > 1000U)
  1780. {
  1781. break;
  1782. }
  1783. } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
  1784. }
  1785. else
  1786. {
  1787. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
  1788. }
  1789. }
  1790. }
  1791. else
  1792. {
  1793. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
  1794. if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
  1795. {
  1796. USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
  1797. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
  1798. do
  1799. {
  1800. count++;
  1801. if (count > 1000U)
  1802. {
  1803. break;
  1804. }
  1805. } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
  1806. }
  1807. else
  1808. {
  1809. USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
  1810. }
  1811. }
  1812. return HAL_OK;
  1813. }
  1814. /**
  1815. * @brief Initiate Do Ping protocol
  1816. * @param USBx Selected device
  1817. * @param hc_num Host Channel number
  1818. * This parameter can be a value from 1 to 15
  1819. * @retval HAL state
  1820. */
  1821. HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
  1822. {
  1823. uint32_t USBx_BASE = (uint32_t)USBx;
  1824. uint32_t chnum = (uint32_t)ch_num;
  1825. uint32_t num_packets = 1U;
  1826. uint32_t tmpreg;
  1827. USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
  1828. USB_OTG_HCTSIZ_DOPING;
  1829. /* Set host channel enable */
  1830. tmpreg = USBx_HC(chnum)->HCCHAR;
  1831. tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
  1832. tmpreg |= USB_OTG_HCCHAR_CHENA;
  1833. USBx_HC(chnum)->HCCHAR = tmpreg;
  1834. return HAL_OK;
  1835. }
  1836. /**
  1837. * @brief Stop Host Core
  1838. * @param USBx Selected device
  1839. * @retval HAL state
  1840. */
  1841. HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
  1842. {
  1843. HAL_StatusTypeDef ret = HAL_OK;
  1844. uint32_t USBx_BASE = (uint32_t)USBx;
  1845. __IO uint32_t count = 0U;
  1846. uint32_t value;
  1847. uint32_t i;
  1848. (void)USB_DisableGlobalInt(USBx);
  1849. /* Flush USB FIFO */
  1850. if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
  1851. {
  1852. ret = HAL_ERROR;
  1853. }
  1854. if (USB_FlushRxFifo(USBx) != HAL_OK)
  1855. {
  1856. ret = HAL_ERROR;
  1857. }
  1858. /* Flush out any leftover queued requests. */
  1859. for (i = 0U; i <= 15U; i++)
  1860. {
  1861. value = USBx_HC(i)->HCCHAR;
  1862. value |= USB_OTG_HCCHAR_CHDIS;
  1863. value &= ~USB_OTG_HCCHAR_CHENA;
  1864. value &= ~USB_OTG_HCCHAR_EPDIR;
  1865. USBx_HC(i)->HCCHAR = value;
  1866. }
  1867. /* Halt all channels to put them into a known state. */
  1868. for (i = 0U; i <= 15U; i++)
  1869. {
  1870. value = USBx_HC(i)->HCCHAR;
  1871. value |= USB_OTG_HCCHAR_CHDIS;
  1872. value |= USB_OTG_HCCHAR_CHENA;
  1873. value &= ~USB_OTG_HCCHAR_EPDIR;
  1874. USBx_HC(i)->HCCHAR = value;
  1875. do
  1876. {
  1877. count++;
  1878. if (count > 1000U)
  1879. {
  1880. break;
  1881. }
  1882. } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
  1883. }
  1884. /* Clear any pending Host interrupts */
  1885. USBx_HOST->HAINT = 0xFFFFFFFFU;
  1886. USBx->GINTSTS = 0xFFFFFFFFU;
  1887. (void)USB_EnableGlobalInt(USBx);
  1888. return ret;
  1889. }
  1890. /**
  1891. * @brief USB_ActivateRemoteWakeup active remote wakeup signalling
  1892. * @param USBx Selected device
  1893. * @retval HAL status
  1894. */
  1895. HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
  1896. {
  1897. uint32_t USBx_BASE = (uint32_t)USBx;
  1898. if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
  1899. {
  1900. /* active Remote wakeup signalling */
  1901. USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
  1902. }
  1903. return HAL_OK;
  1904. }
  1905. /**
  1906. * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
  1907. * @param USBx Selected device
  1908. * @retval HAL status
  1909. */
  1910. HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
  1911. {
  1912. uint32_t USBx_BASE = (uint32_t)USBx;
  1913. /* active Remote wakeup signalling */
  1914. USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
  1915. return HAL_OK;
  1916. }
  1917. #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
  1918. /**
  1919. * @}
  1920. */
  1921. /**
  1922. * @}
  1923. */
  1924. #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
  1925. #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
  1926. /**
  1927. * @}
  1928. */