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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_ll_fmc.c
  4. * @author MCD Application Team
  5. * @brief FMC Low Layer HAL module driver.
  6. *
  7. * This file provides firmware functions to manage the following
  8. * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
  9. * + Initialization/de-initialization functions
  10. * + Peripheral Control functions
  11. * + Peripheral State functions
  12. *
  13. ******************************************************************************
  14. * @attention
  15. *
  16. * Copyright (c) 2016 STMicroelectronics.
  17. * All rights reserved.
  18. *
  19. * This software is licensed under terms that can be found in the LICENSE file
  20. * in the root directory of this software component.
  21. * If no LICENSE file comes with this software, it is provided AS-IS.
  22. *
  23. ******************************************************************************
  24. @verbatim
  25. ==============================================================================
  26. ##### FMC peripheral features #####
  27. ==============================================================================
  28. [..] The Flexible memory controller (FMC) includes following memory controllers:
  29. (+) The NOR/PSRAM memory controller
  30. (+) The NAND/PC Card memory controller
  31. (+) The Synchronous DRAM (SDRAM) controller
  32. [..] The FMC functional block makes the interface with synchronous and asynchronous static
  33. memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
  34. (+) to translate AHB transactions into the appropriate external device protocol
  35. (+) to meet the access time requirements of the external memory devices
  36. [..] All external memories share the addresses, data and control signals with the controller.
  37. Each external device is accessed by means of a unique Chip Select. The FMC performs
  38. only one access at a time to an external device.
  39. The main features of the FMC controller are the following:
  40. (+) Interface with static-memory mapped devices including:
  41. (++) Static random access memory (SRAM)
  42. (++) Read-only memory (ROM)
  43. (++) NOR Flash memory/OneNAND Flash memory
  44. (++) PSRAM (4 memory banks)
  45. (++) 16-bit PC Card compatible devices
  46. (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  47. data
  48. (+) Interface with synchronous DRAM (SDRAM) memories
  49. (+) Independent Chip Select control for each memory bank
  50. (+) Independent configuration for each memory bank
  51. @endverbatim
  52. ******************************************************************************
  53. */
  54. /* Includes ------------------------------------------------------------------*/
  55. #include "stm32f4xx_hal.h"
  56. /** @addtogroup STM32F4xx_HAL_Driver
  57. * @{
  58. */
  59. #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
  60. /** @defgroup FMC_LL FMC Low Layer
  61. * @brief FMC driver modules
  62. * @{
  63. */
  64. /* Private typedef -----------------------------------------------------------*/
  65. /* Private define ------------------------------------------------------------*/
  66. /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
  67. * @{
  68. */
  69. /* ----------------------- FMC registers bit mask --------------------------- */
  70. #if defined(FMC_Bank1)
  71. /* --- BCR Register ---*/
  72. /* BCR register clear mask */
  73. /* --- BTR Register ---*/
  74. /* BTR register clear mask */
  75. #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
  76. FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
  77. FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
  78. FMC_BTR1_ACCMOD))
  79. /* --- BWTR Register ---*/
  80. /* BWTR register clear mask */
  81. #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
  82. FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
  83. FMC_BWTR1_ACCMOD))
  84. #endif /* FMC_Bank1 */
  85. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  86. #if defined (FMC_PCR_PWAITEN)
  87. /* --- PCR Register ---*/
  88. /* PCR register clear mask */
  89. #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
  90. FMC_PCR_PTYP | FMC_PCR_PWID | \
  91. FMC_PCR_ECCEN | FMC_PCR_TCLR | \
  92. FMC_PCR_TAR | FMC_PCR_ECCPS))
  93. /* --- PMEM Register ---*/
  94. /* PMEM register clear mask */
  95. #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\
  96. FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2))
  97. /* --- PATT Register ---*/
  98. /* PATT register clear mask */
  99. #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\
  100. FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2))
  101. #else
  102. /* --- PCR Register ---*/
  103. /* PCR register clear mask */
  104. #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \
  105. FMC_PCR2_PTYP | FMC_PCR2_PWID | \
  106. FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
  107. FMC_PCR2_TAR | FMC_PCR2_ECCPS))
  108. /* --- PMEM Register ---*/
  109. /* PMEM register clear mask */
  110. #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\
  111. FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2))
  112. /* --- PATT Register ---*/
  113. /* PATT register clear mask */
  114. #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\
  115. FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2))
  116. #endif /* FMC_PCR_PWAITEN */
  117. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  118. #if defined(FMC_Bank4)
  119. /* --- PCR Register ---*/
  120. /* PCR register clear mask */
  121. #define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \
  122. FMC_PCR4_PTYP | FMC_PCR4_PWID | \
  123. FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \
  124. FMC_PCR4_TAR | FMC_PCR4_ECCPS))
  125. /* --- PMEM Register ---*/
  126. /* PMEM register clear mask */
  127. #define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\
  128. FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4))
  129. /* --- PATT Register ---*/
  130. /* PATT register clear mask */
  131. #define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\
  132. FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4))
  133. /* --- PIO4 Register ---*/
  134. /* PIO4 register clear mask */
  135. #define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
  136. FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
  137. #endif /* FMC_Bank4 */
  138. #if defined(FMC_Bank5_6)
  139. /* --- SDCR Register ---*/
  140. /* SDCR register clear mask */
  141. #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
  142. FMC_SDCR1_MWID | FMC_SDCR1_NB | \
  143. FMC_SDCR1_CAS | FMC_SDCR1_WP | \
  144. FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
  145. FMC_SDCR1_RPIPE))
  146. /* --- SDTR Register ---*/
  147. /* SDTR register clear mask */
  148. #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
  149. FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
  150. FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
  151. FMC_SDTR1_TRCD))
  152. #endif /* FMC_Bank5_6 */
  153. /**
  154. * @}
  155. */
  156. /* Private macro -------------------------------------------------------------*/
  157. /* Private variables ---------------------------------------------------------*/
  158. /* Private function prototypes -----------------------------------------------*/
  159. /* Exported functions --------------------------------------------------------*/
  160. /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
  161. * @{
  162. */
  163. #if defined(FMC_Bank1)
  164. /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
  165. * @brief NORSRAM Controller functions
  166. *
  167. @verbatim
  168. ==============================================================================
  169. ##### How to use NORSRAM device driver #####
  170. ==============================================================================
  171. [..]
  172. This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
  173. to run the NORSRAM external devices.
  174. (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
  175. (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
  176. (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
  177. (+) FMC NORSRAM bank extended timing configuration using the function
  178. FMC_NORSRAM_Extended_Timing_Init()
  179. (+) FMC NORSRAM bank enable/disable write operation using the functions
  180. FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
  181. @endverbatim
  182. * @{
  183. */
  184. /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
  185. * @brief Initialization and Configuration functions
  186. *
  187. @verbatim
  188. ==============================================================================
  189. ##### Initialization and de_initialization functions #####
  190. ==============================================================================
  191. [..]
  192. This section provides functions allowing to:
  193. (+) Initialize and configure the FMC NORSRAM interface
  194. (+) De-initialize the FMC NORSRAM interface
  195. (+) Configure the FMC clock and associated GPIOs
  196. @endverbatim
  197. * @{
  198. */
  199. /**
  200. * @brief Initialize the FMC_NORSRAM device according to the specified
  201. * control parameters in the FMC_NORSRAM_InitTypeDef
  202. * @param Device Pointer to NORSRAM device instance
  203. * @param Init Pointer to NORSRAM Initialization structure
  204. * @retval HAL status
  205. */
  206. HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
  207. FMC_NORSRAM_InitTypeDef *Init)
  208. {
  209. uint32_t flashaccess;
  210. uint32_t btcr_reg;
  211. uint32_t mask;
  212. /* Check the parameters */
  213. assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  214. assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
  215. assert_param(IS_FMC_MUX(Init->DataAddressMux));
  216. assert_param(IS_FMC_MEMORY(Init->MemoryType));
  217. assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
  218. assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
  219. assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
  220. #if defined(FMC_BCR1_WRAPMOD)
  221. assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
  222. #endif /* FMC_BCR1_WRAPMOD */
  223. assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
  224. assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
  225. assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
  226. assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
  227. assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
  228. assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
  229. #if defined(FMC_BCR1_CCLKEN)
  230. assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
  231. #endif
  232. #if defined(FMC_BCR1_WFDIS)
  233. assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
  234. #endif /* FMC_BCR1_WFDIS */
  235. assert_param(IS_FMC_PAGESIZE(Init->PageSize));
  236. /* Disable NORSRAM Device */
  237. __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
  238. /* Set NORSRAM device control parameters */
  239. if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
  240. {
  241. flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
  242. }
  243. else
  244. {
  245. flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
  246. }
  247. btcr_reg = (flashaccess | \
  248. Init->DataAddressMux | \
  249. Init->MemoryType | \
  250. Init->MemoryDataWidth | \
  251. Init->BurstAccessMode | \
  252. Init->WaitSignalPolarity | \
  253. Init->WaitSignalActive | \
  254. Init->WriteOperation | \
  255. Init->WaitSignal | \
  256. Init->ExtendedMode | \
  257. Init->AsynchronousWait | \
  258. Init->WriteBurst);
  259. #if defined(FMC_BCR1_WRAPMOD)
  260. btcr_reg |= Init->WrapMode;
  261. #endif /* FMC_BCR1_WRAPMOD */
  262. #if defined(FMC_BCR1_CCLKEN)
  263. btcr_reg |= Init->ContinuousClock;
  264. #endif /* FMC_BCR1_CCLKEN */
  265. #if defined(FMC_BCR1_WFDIS)
  266. btcr_reg |= Init->WriteFifo;
  267. #endif /* FMC_BCR1_WFDIS */
  268. btcr_reg |= Init->PageSize;
  269. mask = (FMC_BCR1_MBKEN |
  270. FMC_BCR1_MUXEN |
  271. FMC_BCR1_MTYP |
  272. FMC_BCR1_MWID |
  273. FMC_BCR1_FACCEN |
  274. FMC_BCR1_BURSTEN |
  275. FMC_BCR1_WAITPOL |
  276. FMC_BCR1_WAITCFG |
  277. FMC_BCR1_WREN |
  278. FMC_BCR1_WAITEN |
  279. FMC_BCR1_EXTMOD |
  280. FMC_BCR1_ASYNCWAIT |
  281. FMC_BCR1_CBURSTRW);
  282. #if defined(FMC_BCR1_WRAPMOD)
  283. mask |= FMC_BCR1_WRAPMOD;
  284. #endif /* FMC_BCR1_WRAPMOD */
  285. #if defined(FMC_BCR1_CCLKEN)
  286. mask |= FMC_BCR1_CCLKEN;
  287. #endif
  288. #if defined(FMC_BCR1_WFDIS)
  289. mask |= FMC_BCR1_WFDIS;
  290. #endif /* FMC_BCR1_WFDIS */
  291. mask |= FMC_BCR1_CPSIZE;
  292. MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
  293. #if defined(FMC_BCR1_CCLKEN)
  294. /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
  295. if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
  296. {
  297. MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
  298. }
  299. #endif
  300. #if defined(FMC_BCR1_WFDIS)
  301. if (Init->NSBank != FMC_NORSRAM_BANK1)
  302. {
  303. /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
  304. SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
  305. }
  306. #endif /* FMC_BCR1_WFDIS */
  307. return HAL_OK;
  308. }
  309. /**
  310. * @brief DeInitialize the FMC_NORSRAM peripheral
  311. * @param Device Pointer to NORSRAM device instance
  312. * @param ExDevice Pointer to NORSRAM extended mode device instance
  313. * @param Bank NORSRAM bank number
  314. * @retval HAL status
  315. */
  316. HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
  317. FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
  318. {
  319. /* Check the parameters */
  320. assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  321. assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
  322. assert_param(IS_FMC_NORSRAM_BANK(Bank));
  323. /* Disable the FMC_NORSRAM device */
  324. __FMC_NORSRAM_DISABLE(Device, Bank);
  325. /* De-initialize the FMC_NORSRAM device */
  326. /* FMC_NORSRAM_BANK1 */
  327. if (Bank == FMC_NORSRAM_BANK1)
  328. {
  329. Device->BTCR[Bank] = 0x000030DBU;
  330. }
  331. /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
  332. else
  333. {
  334. Device->BTCR[Bank] = 0x000030D2U;
  335. }
  336. Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
  337. ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
  338. return HAL_OK;
  339. }
  340. /**
  341. * @brief Initialize the FMC_NORSRAM Timing according to the specified
  342. * parameters in the FMC_NORSRAM_TimingTypeDef
  343. * @param Device Pointer to NORSRAM device instance
  344. * @param Timing Pointer to NORSRAM Timing structure
  345. * @param Bank NORSRAM bank number
  346. * @retval HAL status
  347. */
  348. HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
  349. FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
  350. {
  351. #if defined(FMC_BCR1_CCLKEN)
  352. uint32_t tmpr;
  353. #endif
  354. /* Check the parameters */
  355. assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  356. assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  357. assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  358. assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
  359. assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  360. assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
  361. assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
  362. assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
  363. assert_param(IS_FMC_NORSRAM_BANK(Bank));
  364. /* Set FMC_NORSRAM device timing parameters */
  365. MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
  366. ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) |
  367. ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) |
  368. ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) |
  369. (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) |
  370. (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) |
  371. (Timing->AccessMode)));
  372. #if defined(FMC_BCR1_CCLKEN)
  373. /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
  374. if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
  375. {
  376. tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
  377. tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
  378. MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
  379. }
  380. #endif
  381. return HAL_OK;
  382. }
  383. /**
  384. * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
  385. * parameters in the FMC_NORSRAM_TimingTypeDef
  386. * @param Device Pointer to NORSRAM device instance
  387. * @param Timing Pointer to NORSRAM Timing structure
  388. * @param Bank NORSRAM bank number
  389. * @param ExtendedMode FMC Extended Mode
  390. * This parameter can be one of the following values:
  391. * @arg FMC_EXTENDED_MODE_DISABLE
  392. * @arg FMC_EXTENDED_MODE_ENABLE
  393. * @retval HAL status
  394. */
  395. HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
  396. FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
  397. uint32_t ExtendedMode)
  398. {
  399. /* Check the parameters */
  400. assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
  401. /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  402. if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
  403. {
  404. /* Check the parameters */
  405. assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
  406. assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
  407. assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
  408. assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
  409. assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
  410. assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
  411. assert_param(IS_FMC_NORSRAM_BANK(Bank));
  412. /* Set NORSRAM device timing register for write configuration, if extended mode is used */
  413. MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
  414. ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
  415. ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
  416. Timing->AccessMode |
  417. ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
  418. }
  419. else
  420. {
  421. Device->BWTR[Bank] = 0x0FFFFFFFU;
  422. }
  423. return HAL_OK;
  424. }
  425. /**
  426. * @}
  427. */
  428. /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
  429. * @brief management functions
  430. *
  431. @verbatim
  432. ==============================================================================
  433. ##### FMC_NORSRAM Control functions #####
  434. ==============================================================================
  435. [..]
  436. This subsection provides a set of functions allowing to control dynamically
  437. the FMC NORSRAM interface.
  438. @endverbatim
  439. * @{
  440. */
  441. /**
  442. * @brief Enables dynamically FMC_NORSRAM write operation.
  443. * @param Device Pointer to NORSRAM device instance
  444. * @param Bank NORSRAM bank number
  445. * @retval HAL status
  446. */
  447. HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  448. {
  449. /* Check the parameters */
  450. assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  451. assert_param(IS_FMC_NORSRAM_BANK(Bank));
  452. /* Enable write operation */
  453. SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
  454. return HAL_OK;
  455. }
  456. /**
  457. * @brief Disables dynamically FMC_NORSRAM write operation.
  458. * @param Device Pointer to NORSRAM device instance
  459. * @param Bank NORSRAM bank number
  460. * @retval HAL status
  461. */
  462. HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
  463. {
  464. /* Check the parameters */
  465. assert_param(IS_FMC_NORSRAM_DEVICE(Device));
  466. assert_param(IS_FMC_NORSRAM_BANK(Bank));
  467. /* Disable write operation */
  468. CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
  469. return HAL_OK;
  470. }
  471. /**
  472. * @}
  473. */
  474. /**
  475. * @}
  476. */
  477. #endif /* FMC_Bank1 */
  478. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  479. /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
  480. * @brief NAND Controller functions
  481. *
  482. @verbatim
  483. ==============================================================================
  484. ##### How to use NAND device driver #####
  485. ==============================================================================
  486. [..]
  487. This driver contains a set of APIs to interface with the FMC NAND banks in order
  488. to run the NAND external devices.
  489. (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
  490. (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
  491. (+) FMC NAND bank common space timing configuration using the function
  492. FMC_NAND_CommonSpace_Timing_Init()
  493. (+) FMC NAND bank attribute space timing configuration using the function
  494. FMC_NAND_AttributeSpace_Timing_Init()
  495. (+) FMC NAND bank enable/disable ECC correction feature using the functions
  496. FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
  497. (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
  498. @endverbatim
  499. * @{
  500. */
  501. /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  502. * @brief Initialization and Configuration functions
  503. *
  504. @verbatim
  505. ==============================================================================
  506. ##### Initialization and de_initialization functions #####
  507. ==============================================================================
  508. [..]
  509. This section provides functions allowing to:
  510. (+) Initialize and configure the FMC NAND interface
  511. (+) De-initialize the FMC NAND interface
  512. (+) Configure the FMC clock and associated GPIOs
  513. @endverbatim
  514. * @{
  515. */
  516. /**
  517. * @brief Initializes the FMC_NAND device according to the specified
  518. * control parameters in the FMC_NAND_HandleTypeDef
  519. * @param Device Pointer to NAND device instance
  520. * @param Init Pointer to NAND Initialization structure
  521. * @retval HAL status
  522. */
  523. HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
  524. {
  525. /* Check the parameters */
  526. assert_param(IS_FMC_NAND_DEVICE(Device));
  527. assert_param(IS_FMC_NAND_BANK(Init->NandBank));
  528. assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
  529. assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
  530. assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
  531. assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
  532. assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
  533. assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
  534. #if defined(FMC_Bank2_3)
  535. /* Set NAND device control parameters */
  536. if (Init->NandBank == FMC_NAND_BANK2)
  537. {
  538. /* NAND bank 2 registers configuration */
  539. MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
  540. FMC_PCR_MEMORY_TYPE_NAND |
  541. Init->MemoryDataWidth |
  542. Init->EccComputation |
  543. Init->ECCPageSize |
  544. ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
  545. ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
  546. }
  547. else
  548. {
  549. /* NAND bank 3 registers configuration */
  550. MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
  551. FMC_PCR_MEMORY_TYPE_NAND |
  552. Init->MemoryDataWidth |
  553. Init->EccComputation |
  554. Init->ECCPageSize |
  555. ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
  556. ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
  557. }
  558. #else
  559. /* NAND bank 3 registers configuration */
  560. MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
  561. FMC_PCR_MEMORY_TYPE_NAND |
  562. Init->MemoryDataWidth |
  563. Init->EccComputation |
  564. Init->ECCPageSize |
  565. ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
  566. ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
  567. #endif
  568. return HAL_OK;
  569. }
  570. /**
  571. * @brief Initializes the FMC_NAND Common space Timing according to the specified
  572. * parameters in the FMC_NAND_PCC_TimingTypeDef
  573. * @param Device Pointer to NAND device instance
  574. * @param Timing Pointer to NAND timing structure
  575. * @param Bank NAND bank number
  576. * @retval HAL status
  577. */
  578. HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
  579. FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  580. {
  581. /* Check the parameters */
  582. assert_param(IS_FMC_NAND_DEVICE(Device));
  583. assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
  584. assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
  585. assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
  586. assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
  587. assert_param(IS_FMC_NAND_BANK(Bank));
  588. #if defined(FMC_Bank2_3)
  589. /* Set FMC_NAND device timing parameters */
  590. if (Bank == FMC_NAND_BANK2)
  591. {
  592. /* NAND bank 2 registers configuration */
  593. MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
  594. ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
  595. ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
  596. ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
  597. }
  598. else
  599. {
  600. /* NAND bank 3 registers configuration */
  601. MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
  602. ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
  603. ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
  604. ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
  605. }
  606. #else
  607. /* Prevent unused argument(s) compilation warning if no assert_param check */
  608. UNUSED(Bank);
  609. /* NAND bank 3 registers configuration */
  610. MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
  611. ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) |
  612. ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) |
  613. ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos)));
  614. #endif
  615. return HAL_OK;
  616. }
  617. /**
  618. * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
  619. * parameters in the FMC_NAND_PCC_TimingTypeDef
  620. * @param Device Pointer to NAND device instance
  621. * @param Timing Pointer to NAND timing structure
  622. * @param Bank NAND bank number
  623. * @retval HAL status
  624. */
  625. HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
  626. FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
  627. {
  628. /* Check the parameters */
  629. assert_param(IS_FMC_NAND_DEVICE(Device));
  630. assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
  631. assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
  632. assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
  633. assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
  634. assert_param(IS_FMC_NAND_BANK(Bank));
  635. #if defined(FMC_Bank2_3)
  636. /* Set FMC_NAND device timing parameters */
  637. if (Bank == FMC_NAND_BANK2)
  638. {
  639. /* NAND bank 2 registers configuration */
  640. MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
  641. ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
  642. ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
  643. ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
  644. }
  645. else
  646. {
  647. /* NAND bank 3 registers configuration */
  648. MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
  649. ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
  650. ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
  651. ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
  652. }
  653. #else
  654. /* Prevent unused argument(s) compilation warning if no assert_param check */
  655. UNUSED(Bank);
  656. /* NAND bank 3 registers configuration */
  657. MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
  658. ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) |
  659. ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) |
  660. ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos)));
  661. #endif
  662. return HAL_OK;
  663. }
  664. /**
  665. * @brief DeInitializes the FMC_NAND device
  666. * @param Device Pointer to NAND device instance
  667. * @param Bank NAND bank number
  668. * @retval HAL status
  669. */
  670. HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
  671. {
  672. /* Check the parameters */
  673. assert_param(IS_FMC_NAND_DEVICE(Device));
  674. assert_param(IS_FMC_NAND_BANK(Bank));
  675. /* Disable the NAND Bank */
  676. __FMC_NAND_DISABLE(Device, Bank);
  677. /* De-initialize the NAND Bank */
  678. #if defined(FMC_Bank2_3)
  679. if (Bank == FMC_NAND_BANK2)
  680. {
  681. /* Set the FMC_NAND_BANK2 registers to their reset values */
  682. WRITE_REG(Device->PCR2, 0x00000018U);
  683. WRITE_REG(Device->SR2, 0x00000040U);
  684. WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
  685. WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
  686. }
  687. /* FMC_Bank3_NAND */
  688. else
  689. {
  690. /* Set the FMC_NAND_BANK3 registers to their reset values */
  691. WRITE_REG(Device->PCR3, 0x00000018U);
  692. WRITE_REG(Device->SR3, 0x00000040U);
  693. WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
  694. WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
  695. }
  696. #else
  697. /* Prevent unused argument(s) compilation warning if no assert_param check */
  698. UNUSED(Bank);
  699. /* Set the FMC_NAND_BANK3 registers to their reset values */
  700. WRITE_REG(Device->PCR, 0x00000018U);
  701. WRITE_REG(Device->SR, 0x00000040U);
  702. WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
  703. WRITE_REG(Device->PATT, 0xFCFCFCFCU);
  704. #endif
  705. return HAL_OK;
  706. }
  707. /**
  708. * @}
  709. */
  710. /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
  711. * @brief management functions
  712. *
  713. @verbatim
  714. ==============================================================================
  715. ##### FMC_NAND Control functions #####
  716. ==============================================================================
  717. [..]
  718. This subsection provides a set of functions allowing to control dynamically
  719. the FMC NAND interface.
  720. @endverbatim
  721. * @{
  722. */
  723. /**
  724. * @brief Enables dynamically FMC_NAND ECC feature.
  725. * @param Device Pointer to NAND device instance
  726. * @param Bank NAND bank number
  727. * @retval HAL status
  728. */
  729. HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
  730. {
  731. /* Check the parameters */
  732. assert_param(IS_FMC_NAND_DEVICE(Device));
  733. assert_param(IS_FMC_NAND_BANK(Bank));
  734. /* Enable ECC feature */
  735. #if defined(FMC_Bank2_3)
  736. if (Bank == FMC_NAND_BANK2)
  737. {
  738. SET_BIT(Device->PCR2, FMC_PCR2_ECCEN);
  739. }
  740. else
  741. {
  742. SET_BIT(Device->PCR3, FMC_PCR2_ECCEN);
  743. }
  744. #else
  745. /* Prevent unused argument(s) compilation warning if no assert_param check */
  746. UNUSED(Bank);
  747. SET_BIT(Device->PCR, FMC_PCR_ECCEN);
  748. #endif
  749. return HAL_OK;
  750. }
  751. /**
  752. * @brief Disables dynamically FMC_NAND ECC feature.
  753. * @param Device Pointer to NAND device instance
  754. * @param Bank NAND bank number
  755. * @retval HAL status
  756. */
  757. HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
  758. {
  759. /* Check the parameters */
  760. assert_param(IS_FMC_NAND_DEVICE(Device));
  761. assert_param(IS_FMC_NAND_BANK(Bank));
  762. /* Disable ECC feature */
  763. #if defined(FMC_Bank2_3)
  764. if (Bank == FMC_NAND_BANK2)
  765. {
  766. CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN);
  767. }
  768. else
  769. {
  770. CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN);
  771. }
  772. #else
  773. /* Prevent unused argument(s) compilation warning if no assert_param check */
  774. UNUSED(Bank);
  775. CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
  776. #endif
  777. return HAL_OK;
  778. }
  779. /**
  780. * @brief Disables dynamically FMC_NAND ECC feature.
  781. * @param Device Pointer to NAND device instance
  782. * @param ECCval Pointer to ECC value
  783. * @param Bank NAND bank number
  784. * @param Timeout Timeout wait value
  785. * @retval HAL status
  786. */
  787. HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
  788. uint32_t Timeout)
  789. {
  790. uint32_t tickstart;
  791. /* Check the parameters */
  792. assert_param(IS_FMC_NAND_DEVICE(Device));
  793. assert_param(IS_FMC_NAND_BANK(Bank));
  794. /* Get tick */
  795. tickstart = HAL_GetTick();
  796. /* Wait until FIFO is empty */
  797. while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
  798. {
  799. /* Check for the Timeout */
  800. if (Timeout != HAL_MAX_DELAY)
  801. {
  802. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  803. {
  804. return HAL_TIMEOUT;
  805. }
  806. }
  807. }
  808. #if defined(FMC_Bank2_3)
  809. if (Bank == FMC_NAND_BANK2)
  810. {
  811. /* Get the ECCR2 register value */
  812. *ECCval = (uint32_t)Device->ECCR2;
  813. }
  814. else
  815. {
  816. /* Get the ECCR3 register value */
  817. *ECCval = (uint32_t)Device->ECCR3;
  818. }
  819. #else
  820. /* Prevent unused argument(s) compilation warning if no assert_param check */
  821. UNUSED(Bank);
  822. /* Get the ECCR register value */
  823. *ECCval = (uint32_t)Device->ECCR;
  824. #endif
  825. return HAL_OK;
  826. }
  827. /**
  828. * @}
  829. */
  830. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  831. #if defined(FMC_Bank4)
  832. /** @addtogroup FMC_LL_PCCARD
  833. * @brief PCCARD Controller functions
  834. *
  835. @verbatim
  836. ==============================================================================
  837. ##### How to use PCCARD device driver #####
  838. ==============================================================================
  839. [..]
  840. This driver contains a set of APIs to interface with the FMC PCCARD bank in order
  841. to run the PCCARD/compact flash external devices.
  842. (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
  843. (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
  844. (+) FMC PCCARD bank common space timing configuration using the function
  845. FMC_PCCARD_CommonSpace_Timing_Init()
  846. (+) FMC PCCARD bank attribute space timing configuration using the function
  847. FMC_PCCARD_AttributeSpace_Timing_Init()
  848. (+) FMC PCCARD bank IO space timing configuration using the function
  849. FMC_PCCARD_IOSpace_Timing_Init()
  850. @endverbatim
  851. * @{
  852. */
  853. /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
  854. * @brief Initialization and Configuration functions
  855. *
  856. @verbatim
  857. ==============================================================================
  858. ##### Initialization and de_initialization functions #####
  859. ==============================================================================
  860. [..]
  861. This section provides functions allowing to:
  862. (+) Initialize and configure the FMC PCCARD interface
  863. (+) De-initialize the FMC PCCARD interface
  864. (+) Configure the FMC clock and associated GPIOs
  865. @endverbatim
  866. * @{
  867. */
  868. /**
  869. * @brief Initializes the FMC_PCCARD device according to the specified
  870. * control parameters in the FMC_PCCARD_HandleTypeDef
  871. * @param Device Pointer to PCCARD device instance
  872. * @param Init Pointer to PCCARD Initialization structure
  873. * @retval HAL status
  874. */
  875. HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
  876. {
  877. /* Check the parameters */
  878. assert_param(IS_FMC_PCCARD_DEVICE(Device));
  879. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  880. assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
  881. assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
  882. assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
  883. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  884. /* Set FMC_PCCARD device control parameters */
  885. MODIFY_REG(Device->PCR4,
  886. (FMC_PCR4_PTYP |
  887. FMC_PCR4_PWAITEN |
  888. FMC_PCR4_PWID |
  889. FMC_PCR4_TCLR |
  890. FMC_PCR4_TAR),
  891. (FMC_PCR_MEMORY_TYPE_PCCARD |
  892. Init->Waitfeature |
  893. FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
  894. (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) |
  895. (Init->TARSetupTime << FMC_PCR4_TAR_Pos)));
  896. return HAL_OK;
  897. }
  898. /**
  899. * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
  900. * parameters in the FMC_NAND_PCC_TimingTypeDef
  901. * @param Device Pointer to PCCARD device instance
  902. * @param Timing Pointer to PCCARD timing structure
  903. * @retval HAL status
  904. */
  905. HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
  906. FMC_NAND_PCC_TimingTypeDef *Timing)
  907. {
  908. /* Check the parameters */
  909. assert_param(IS_FMC_PCCARD_DEVICE(Device));
  910. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  911. assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
  912. assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
  913. assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
  914. assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
  915. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  916. /* Set PCCARD timing parameters */
  917. MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK,
  918. (Timing->SetupTime |
  919. ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) |
  920. ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) |
  921. ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos)));
  922. return HAL_OK;
  923. }
  924. /**
  925. * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
  926. * parameters in the FMC_NAND_PCC_TimingTypeDef
  927. * @param Device Pointer to PCCARD device instance
  928. * @param Timing Pointer to PCCARD timing structure
  929. * @retval HAL status
  930. */
  931. HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
  932. FMC_NAND_PCC_TimingTypeDef *Timing)
  933. {
  934. /* Check the parameters */
  935. assert_param(IS_FMC_PCCARD_DEVICE(Device));
  936. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  937. assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
  938. assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
  939. assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
  940. assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
  941. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  942. /* Set PCCARD timing parameters */
  943. MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK,
  944. (Timing->SetupTime |
  945. ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) |
  946. ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) |
  947. ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos)));
  948. return HAL_OK;
  949. }
  950. /**
  951. * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
  952. * parameters in the FMC_NAND_PCC_TimingTypeDef
  953. * @param Device Pointer to PCCARD device instance
  954. * @param Timing Pointer to PCCARD timing structure
  955. * @retval HAL status
  956. */
  957. HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
  958. FMC_NAND_PCC_TimingTypeDef *Timing)
  959. {
  960. /* Check the parameters */
  961. assert_param(IS_FMC_PCCARD_DEVICE(Device));
  962. #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
  963. assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
  964. assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
  965. assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
  966. assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
  967. #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
  968. /* Set FMC_PCCARD device timing parameters */
  969. MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
  970. (Timing->SetupTime |
  971. (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) |
  972. (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) |
  973. (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos)));
  974. return HAL_OK;
  975. }
  976. /**
  977. * @brief DeInitializes the FMC_PCCARD device
  978. * @param Device Pointer to PCCARD device instance
  979. * @retval HAL status
  980. */
  981. HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
  982. {
  983. /* Check the parameters */
  984. assert_param(IS_FMC_PCCARD_DEVICE(Device));
  985. /* Disable the FMC_PCCARD device */
  986. __FMC_PCCARD_DISABLE(Device);
  987. /* De-initialize the FMC_PCCARD device */
  988. Device->PCR4 = 0x00000018U;
  989. Device->SR4 = 0x00000040U;
  990. Device->PMEM4 = 0xFCFCFCFCU;
  991. Device->PATT4 = 0xFCFCFCFCU;
  992. Device->PIO4 = 0xFCFCFCFCU;
  993. return HAL_OK;
  994. }
  995. /**
  996. * @}
  997. */
  998. #endif /* FMC_Bank4 */
  999. #if defined(FMC_Bank5_6)
  1000. /** @defgroup FMC_LL_SDRAM
  1001. * @brief SDRAM Controller functions
  1002. *
  1003. @verbatim
  1004. ==============================================================================
  1005. ##### How to use SDRAM device driver #####
  1006. ==============================================================================
  1007. [..]
  1008. This driver contains a set of APIs to interface with the FMC SDRAM banks in order
  1009. to run the SDRAM external devices.
  1010. (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
  1011. (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
  1012. (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
  1013. (+) FMC SDRAM bank enable/disable write operation using the functions
  1014. FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
  1015. (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
  1016. @endverbatim
  1017. * @{
  1018. */
  1019. /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
  1020. * @brief Initialization and Configuration functions
  1021. *
  1022. @verbatim
  1023. ==============================================================================
  1024. ##### Initialization and de_initialization functions #####
  1025. ==============================================================================
  1026. [..]
  1027. This section provides functions allowing to:
  1028. (+) Initialize and configure the FMC SDRAM interface
  1029. (+) De-initialize the FMC SDRAM interface
  1030. (+) Configure the FMC clock and associated GPIOs
  1031. @endverbatim
  1032. * @{
  1033. */
  1034. /**
  1035. * @brief Initializes the FMC_SDRAM device according to the specified
  1036. * control parameters in the FMC_SDRAM_InitTypeDef
  1037. * @param Device Pointer to SDRAM device instance
  1038. * @param Init Pointer to SDRAM Initialization structure
  1039. * @retval HAL status
  1040. */
  1041. HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
  1042. {
  1043. /* Check the parameters */
  1044. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1045. assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
  1046. assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
  1047. assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
  1048. assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
  1049. assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
  1050. assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
  1051. assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
  1052. assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
  1053. assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
  1054. assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
  1055. /* Set SDRAM bank configuration parameters */
  1056. if (Init->SDBank == FMC_SDRAM_BANK1)
  1057. {
  1058. MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
  1059. SDCR_CLEAR_MASK,
  1060. (Init->ColumnBitsNumber |
  1061. Init->RowBitsNumber |
  1062. Init->MemoryDataWidth |
  1063. Init->InternalBankNumber |
  1064. Init->CASLatency |
  1065. Init->WriteProtection |
  1066. Init->SDClockPeriod |
  1067. Init->ReadBurst |
  1068. Init->ReadPipeDelay));
  1069. }
  1070. else /* FMC_Bank2_SDRAM */
  1071. {
  1072. MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
  1073. FMC_SDCR1_SDCLK |
  1074. FMC_SDCR1_RBURST |
  1075. FMC_SDCR1_RPIPE,
  1076. (Init->SDClockPeriod |
  1077. Init->ReadBurst |
  1078. Init->ReadPipeDelay));
  1079. MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
  1080. SDCR_CLEAR_MASK,
  1081. (Init->ColumnBitsNumber |
  1082. Init->RowBitsNumber |
  1083. Init->MemoryDataWidth |
  1084. Init->InternalBankNumber |
  1085. Init->CASLatency |
  1086. Init->WriteProtection));
  1087. }
  1088. return HAL_OK;
  1089. }
  1090. /**
  1091. * @brief Initializes the FMC_SDRAM device timing according to the specified
  1092. * parameters in the FMC_SDRAM_TimingTypeDef
  1093. * @param Device Pointer to SDRAM device instance
  1094. * @param Timing Pointer to SDRAM Timing structure
  1095. * @param Bank SDRAM bank number
  1096. * @retval HAL status
  1097. */
  1098. HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
  1099. FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
  1100. {
  1101. /* Check the parameters */
  1102. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1103. assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
  1104. assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
  1105. assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
  1106. assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
  1107. assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
  1108. assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
  1109. assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
  1110. assert_param(IS_FMC_SDRAM_BANK(Bank));
  1111. /* Set SDRAM device timing parameters */
  1112. if (Bank == FMC_SDRAM_BANK1)
  1113. {
  1114. MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
  1115. SDTR_CLEAR_MASK,
  1116. (((Timing->LoadToActiveDelay) - 1U) |
  1117. (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
  1118. (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
  1119. (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
  1120. (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
  1121. (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
  1122. (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
  1123. }
  1124. else /* FMC_Bank2_SDRAM */
  1125. {
  1126. MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
  1127. FMC_SDTR1_TRC |
  1128. FMC_SDTR1_TRP,
  1129. (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
  1130. (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
  1131. MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
  1132. SDTR_CLEAR_MASK,
  1133. (((Timing->LoadToActiveDelay) - 1U) |
  1134. (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
  1135. (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
  1136. (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
  1137. (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
  1138. }
  1139. return HAL_OK;
  1140. }
  1141. /**
  1142. * @brief DeInitializes the FMC_SDRAM peripheral
  1143. * @param Device Pointer to SDRAM device instance
  1144. * @retval HAL status
  1145. */
  1146. HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
  1147. {
  1148. /* Check the parameters */
  1149. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1150. assert_param(IS_FMC_SDRAM_BANK(Bank));
  1151. /* De-initialize the SDRAM device */
  1152. Device->SDCR[Bank] = 0x000002D0U;
  1153. Device->SDTR[Bank] = 0x0FFFFFFFU;
  1154. Device->SDCMR = 0x00000000U;
  1155. Device->SDRTR = 0x00000000U;
  1156. Device->SDSR = 0x00000000U;
  1157. return HAL_OK;
  1158. }
  1159. /**
  1160. * @}
  1161. */
  1162. /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
  1163. * @brief management functions
  1164. *
  1165. @verbatim
  1166. ==============================================================================
  1167. ##### FMC_SDRAM Control functions #####
  1168. ==============================================================================
  1169. [..]
  1170. This subsection provides a set of functions allowing to control dynamically
  1171. the FMC SDRAM interface.
  1172. @endverbatim
  1173. * @{
  1174. */
  1175. /**
  1176. * @brief Enables dynamically FMC_SDRAM write protection.
  1177. * @param Device Pointer to SDRAM device instance
  1178. * @param Bank SDRAM bank number
  1179. * @retval HAL status
  1180. */
  1181. HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
  1182. {
  1183. /* Check the parameters */
  1184. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1185. assert_param(IS_FMC_SDRAM_BANK(Bank));
  1186. /* Enable write protection */
  1187. SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
  1188. return HAL_OK;
  1189. }
  1190. /**
  1191. * @brief Disables dynamically FMC_SDRAM write protection.
  1192. * @param hsdram FMC_SDRAM handle
  1193. * @retval HAL status
  1194. */
  1195. HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
  1196. {
  1197. /* Check the parameters */
  1198. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1199. assert_param(IS_FMC_SDRAM_BANK(Bank));
  1200. /* Disable write protection */
  1201. CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
  1202. return HAL_OK;
  1203. }
  1204. /**
  1205. * @brief Send Command to the FMC SDRAM bank
  1206. * @param Device Pointer to SDRAM device instance
  1207. * @param Command Pointer to SDRAM command structure
  1208. * @param Timing Pointer to SDRAM Timing structure
  1209. * @param Timeout Timeout wait value
  1210. * @retval HAL state
  1211. */
  1212. HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
  1213. FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
  1214. {
  1215. uint32_t tickstart = 0U;
  1216. /* Check the parameters */
  1217. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1218. assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
  1219. assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
  1220. assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
  1221. assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
  1222. /* Set command register */
  1223. MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
  1224. ((Command->CommandMode) | (Command->CommandTarget) |
  1225. (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
  1226. ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
  1227. /* Get tick */
  1228. tickstart = HAL_GetTick();
  1229. /* wait until command is send */
  1230. while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
  1231. {
  1232. /* Check for the Timeout */
  1233. if (Timeout != HAL_MAX_DELAY)
  1234. {
  1235. if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  1236. {
  1237. return HAL_TIMEOUT;
  1238. }
  1239. }
  1240. }
  1241. return HAL_OK;
  1242. }
  1243. /**
  1244. * @brief Program the SDRAM Memory Refresh rate.
  1245. * @param Device Pointer to SDRAM device instance
  1246. * @param RefreshRate The SDRAM refresh rate value.
  1247. * @retval HAL state
  1248. */
  1249. HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
  1250. {
  1251. /* Check the parameters */
  1252. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1253. assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
  1254. /* Set the refresh rate in command register */
  1255. MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
  1256. return HAL_OK;
  1257. }
  1258. /**
  1259. * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
  1260. * @param Device Pointer to SDRAM device instance
  1261. * @param AutoRefreshNumber Specifies the auto Refresh number.
  1262. * @retval None
  1263. */
  1264. HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
  1265. uint32_t AutoRefreshNumber)
  1266. {
  1267. /* Check the parameters */
  1268. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1269. assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
  1270. /* Set the Auto-refresh number in command register */
  1271. MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
  1272. return HAL_OK;
  1273. }
  1274. /**
  1275. * @brief Returns the indicated FMC SDRAM bank mode status.
  1276. * @param Device Pointer to SDRAM device instance
  1277. * @param Bank Defines the FMC SDRAM bank. This parameter can be
  1278. * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
  1279. * @retval The FMC SDRAM bank mode status, could be on of the following values:
  1280. * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
  1281. * FMC_SDRAM_POWER_DOWN_MODE.
  1282. */
  1283. uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
  1284. {
  1285. uint32_t tmpreg;
  1286. /* Check the parameters */
  1287. assert_param(IS_FMC_SDRAM_DEVICE(Device));
  1288. assert_param(IS_FMC_SDRAM_BANK(Bank));
  1289. /* Get the corresponding bank mode */
  1290. if (Bank == FMC_SDRAM_BANK1)
  1291. {
  1292. tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
  1293. }
  1294. else
  1295. {
  1296. tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
  1297. }
  1298. /* Return the mode status */
  1299. return tmpreg;
  1300. }
  1301. /**
  1302. * @}
  1303. */
  1304. /**
  1305. * @}
  1306. */
  1307. #endif /* FMC_Bank5_6 */
  1308. /**
  1309. * @}
  1310. */
  1311. /**
  1312. * @}
  1313. */
  1314. #endif /* HAL_NOR_MODULE_ENABLED */
  1315. /**
  1316. * @}
  1317. */
  1318. /**
  1319. * @}
  1320. */