训练营PLSR题目
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_qspi.c
  4. * @author MCD Application Team
  5. * @brief QSPI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the QuadSPI interface (QSPI).
  8. * + Initialization and de-initialization functions
  9. * + Indirect functional mode management
  10. * + Memory-mapped functional mode management
  11. * + Auto-polling functional mode management
  12. * + Interrupts and flags management
  13. * + DMA channel configuration for indirect functional mode
  14. * + Errors management and abort functionality
  15. *
  16. *
  17. ******************************************************************************
  18. * @attention
  19. *
  20. * Copyright (c) 2016 STMicroelectronics.
  21. * All rights reserved.
  22. *
  23. * This software is licensed under terms that can be found in the LICENSE file
  24. * in the root directory of this software component.
  25. * If no LICENSE file comes with this software, it is provided AS-IS.
  26. *
  27. ******************************************************************************
  28. @verbatim
  29. ===============================================================================
  30. ##### How to use this driver #####
  31. ===============================================================================
  32. [..]
  33. *** Initialization ***
  34. ======================
  35. [..]
  36. (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
  37. (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
  38. (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
  39. (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
  40. (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
  41. (++) If interrupt mode is used, enable and configure QuadSPI global
  42. interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  43. (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
  44. with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
  45. link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
  46. DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  47. (#) Configure the flash size, the clock prescaler, the fifo threshold, the
  48. clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
  49. *** Indirect functional mode ***
  50. ================================
  51. [..]
  52. (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
  53. functions :
  54. (++) Instruction phase : the mode used and if present the instruction opcode.
  55. (++) Address phase : the mode used and if present the size and the address value.
  56. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  57. bytes values.
  58. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  59. (++) Data phase : the mode used and if present the number of bytes.
  60. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  61. if activated.
  62. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  63. (#) If no data is required for the command, it is sent directly to the memory :
  64. (++) In polling mode, the output of the function is done when the transfer is complete.
  65. (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
  66. (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
  67. HAL_QSPI_Transmit_IT() after the command configuration :
  68. (++) In polling mode, the output of the function is done when the transfer is complete.
  69. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  70. is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  71. (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
  72. HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  73. (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
  74. HAL_QSPI_Receive_IT() after the command configuration :
  75. (++) In polling mode, the output of the function is done when the transfer is complete.
  76. (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  77. is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  78. (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
  79. HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  80. *** Auto-polling functional mode ***
  81. ====================================
  82. [..]
  83. (#) Configure the command sequence and the auto-polling functional mode using the
  84. HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
  85. (++) Instruction phase : the mode used and if present the instruction opcode.
  86. (++) Address phase : the mode used and if present the size and the address value.
  87. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  88. bytes values.
  89. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  90. (++) Data phase : the mode used.
  91. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  92. if activated.
  93. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  94. (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
  95. the polling interval and the automatic stop activation.
  96. (#) After the configuration :
  97. (++) In polling mode, the output of the function is done when the status match is reached. The
  98. automatic stop is activated to avoid an infinite loop.
  99. (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
  100. *** Memory-mapped functional mode ***
  101. =====================================
  102. [..]
  103. (#) Configure the command sequence and the memory-mapped functional mode using the
  104. HAL_QSPI_MemoryMapped() functions :
  105. (++) Instruction phase : the mode used and if present the instruction opcode.
  106. (++) Address phase : the mode used and the size.
  107. (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  108. bytes values.
  109. (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  110. (++) Data phase : the mode used.
  111. (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  112. if activated.
  113. (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  114. (++) The timeout activation and the timeout period.
  115. (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
  116. the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
  117. *** Errors management and abort functionality ***
  118. =================================================
  119. [..]
  120. (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
  121. (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
  122. flushes the fifo :
  123. (++) In polling mode, the output of the function is done when the transfer
  124. complete bit is set and the busy bit cleared.
  125. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
  126. the transfer complete bit is set.
  127. *** Control functions ***
  128. =========================
  129. [..]
  130. (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
  131. (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
  132. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
  133. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
  134. (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed.
  135. *** Callback registration ***
  136. =============================================
  137. [..]
  138. The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
  139. allows the user to configure dynamically the driver callbacks.
  140. Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
  141. it allows to register following callbacks:
  142. (+) ErrorCallback : callback when error occurs.
  143. (+) AbortCpltCallback : callback when abort is completed.
  144. (+) FifoThresholdCallback : callback when the fifo threshold is reached.
  145. (+) CmdCpltCallback : callback when a command without data is completed.
  146. (+) RxCpltCallback : callback when a reception transfer is completed.
  147. (+) TxCpltCallback : callback when a transmission transfer is completed.
  148. (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
  149. (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
  150. (+) StatusMatchCallback : callback when a status match occurs.
  151. (+) TimeOutCallback : callback when the timeout perioed expires.
  152. (+) MspInitCallback : QSPI MspInit.
  153. (+) MspDeInitCallback : QSPI MspDeInit.
  154. This function takes as parameters the HAL peripheral handle, the Callback ID
  155. and a pointer to the user callback function.
  156. Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
  157. weak (surcharged) function. It allows to reset following callbacks:
  158. (+) ErrorCallback : callback when error occurs.
  159. (+) AbortCpltCallback : callback when abort is completed.
  160. (+) FifoThresholdCallback : callback when the fifo threshold is reached.
  161. (+) CmdCpltCallback : callback when a command without data is completed.
  162. (+) RxCpltCallback : callback when a reception transfer is completed.
  163. (+) TxCpltCallback : callback when a transmission transfer is completed.
  164. (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
  165. (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
  166. (+) StatusMatchCallback : callback when a status match occurs.
  167. (+) TimeOutCallback : callback when the timeout perioed expires.
  168. (+) MspInitCallback : QSPI MspInit.
  169. (+) MspDeInitCallback : QSPI MspDeInit.
  170. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  171. By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
  172. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  173. Exception done for MspInit and MspDeInit callbacks that are respectively
  174. reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
  175. and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
  176. If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
  177. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  178. Callbacks can be registered/unregistered in READY state only.
  179. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  180. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  181. during the Init/DeInit.
  182. In that case first register the MspInit/MspDeInit user callbacks
  183. using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
  184. or HAL_QSPI_Init function.
  185. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
  186. not defined, the callback registering feature is not available
  187. and weak (surcharged) callbacks are used.
  188. *** Workarounds linked to Silicon Limitation ***
  189. ====================================================
  190. [..]
  191. (#) Workarounds Implemented inside HAL Driver
  192. (++) Extra data written in the FIFO at the end of a read transfer
  193. @endverbatim
  194. ******************************************************************************
  195. */
  196. /* Includes ------------------------------------------------------------------*/
  197. #include "stm32f4xx_hal.h"
  198. #if defined(QUADSPI)
  199. /** @addtogroup STM32F4xx_HAL_Driver
  200. * @{
  201. */
  202. /** @defgroup QSPI QSPI
  203. * @brief QSPI HAL module driver
  204. * @{
  205. */
  206. #ifdef HAL_QSPI_MODULE_ENABLED
  207. /* Private typedef -----------------------------------------------------------*/
  208. /* Private define ------------------------------------------------------------*/
  209. /** @defgroup QSPI_Private_Constants QSPI Private Constants
  210. * @{
  211. */
  212. #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
  213. #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
  214. #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
  215. #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
  216. /**
  217. * @}
  218. */
  219. /* Private macro -------------------------------------------------------------*/
  220. /** @defgroup QSPI_Private_Macros QSPI Private Macros
  221. * @{
  222. */
  223. #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
  224. ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
  225. ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
  226. ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
  227. /**
  228. * @}
  229. */
  230. /* Private variables ---------------------------------------------------------*/
  231. /* Private function prototypes -----------------------------------------------*/
  232. static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
  233. static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
  234. static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
  235. static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
  236. static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
  237. static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
  238. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout);
  239. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
  240. static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
  241. /* Exported functions --------------------------------------------------------*/
  242. /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
  243. * @{
  244. */
  245. /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
  246. * @brief Initialization and Configuration functions
  247. *
  248. @verbatim
  249. ===============================================================================
  250. ##### Initialization and Configuration functions #####
  251. ===============================================================================
  252. [..]
  253. This subsection provides a set of functions allowing to :
  254. (+) Initialize the QuadSPI.
  255. (+) De-initialize the QuadSPI.
  256. @endverbatim
  257. * @{
  258. */
  259. /**
  260. * @brief Initialize the QSPI mode according to the specified parameters
  261. * in the QSPI_InitTypeDef and initialize the associated handle.
  262. * @param hqspi QSPI handle
  263. * @retval HAL status
  264. */
  265. HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
  266. {
  267. HAL_StatusTypeDef status;
  268. uint32_t tickstart = HAL_GetTick();
  269. /* Check the QSPI handle allocation */
  270. if(hqspi == NULL)
  271. {
  272. return HAL_ERROR;
  273. }
  274. /* Check the parameters */
  275. assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
  276. assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
  277. assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
  278. assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
  279. assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
  280. assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
  281. assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
  282. assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
  283. if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
  284. {
  285. assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
  286. }
  287. if(hqspi->State == HAL_QSPI_STATE_RESET)
  288. {
  289. /* Allocate lock resource and initialize it */
  290. hqspi->Lock = HAL_UNLOCKED;
  291. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  292. /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */
  293. hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
  294. hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
  295. hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
  296. hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
  297. hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
  298. hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
  299. hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
  300. hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
  301. hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
  302. hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
  303. if(hqspi->MspInitCallback == NULL)
  304. {
  305. hqspi->MspInitCallback = HAL_QSPI_MspInit;
  306. }
  307. /* Init the low level hardware */
  308. hqspi->MspInitCallback(hqspi);
  309. #else
  310. /* Init the low level hardware : GPIO, CLOCK */
  311. HAL_QSPI_MspInit(hqspi);
  312. #endif
  313. /* Configure the default timeout for the QSPI memory access */
  314. HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
  315. }
  316. /* Configure QSPI FIFO Threshold */
  317. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
  318. ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
  319. /* Wait till BUSY flag reset */
  320. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  321. if(status == HAL_OK)
  322. {
  323. /* Configure QSPI Clock Prescaler and Sample Shift */
  324. MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
  325. ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
  326. hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash));
  327. /* Configure QSPI Flash Size, CS High Time and Clock Mode */
  328. MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
  329. ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
  330. hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
  331. /* Enable the QSPI peripheral */
  332. __HAL_QSPI_ENABLE(hqspi);
  333. /* Set QSPI error code to none */
  334. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  335. /* Initialize the QSPI state */
  336. hqspi->State = HAL_QSPI_STATE_READY;
  337. }
  338. /* Release Lock */
  339. __HAL_UNLOCK(hqspi);
  340. /* Return function status */
  341. return status;
  342. }
  343. /**
  344. * @brief De-Initialize the QSPI peripheral.
  345. * @param hqspi QSPI handle
  346. * @retval HAL status
  347. */
  348. HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
  349. {
  350. /* Check the QSPI handle allocation */
  351. if(hqspi == NULL)
  352. {
  353. return HAL_ERROR;
  354. }
  355. /* Disable the QSPI Peripheral Clock */
  356. __HAL_QSPI_DISABLE(hqspi);
  357. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  358. if(hqspi->MspDeInitCallback == NULL)
  359. {
  360. hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
  361. }
  362. /* DeInit the low level hardware */
  363. hqspi->MspDeInitCallback(hqspi);
  364. #else
  365. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  366. HAL_QSPI_MspDeInit(hqspi);
  367. #endif
  368. /* Set QSPI error code to none */
  369. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  370. /* Initialize the QSPI state */
  371. hqspi->State = HAL_QSPI_STATE_RESET;
  372. /* Release Lock */
  373. __HAL_UNLOCK(hqspi);
  374. return HAL_OK;
  375. }
  376. /**
  377. * @brief Initialize the QSPI MSP.
  378. * @param hqspi QSPI handle
  379. * @retval None
  380. */
  381. __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
  382. {
  383. /* Prevent unused argument(s) compilation warning */
  384. UNUSED(hqspi);
  385. /* NOTE : This function should not be modified, when the callback is needed,
  386. the HAL_QSPI_MspInit can be implemented in the user file
  387. */
  388. }
  389. /**
  390. * @brief DeInitialize the QSPI MSP.
  391. * @param hqspi QSPI handle
  392. * @retval None
  393. */
  394. __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
  395. {
  396. /* Prevent unused argument(s) compilation warning */
  397. UNUSED(hqspi);
  398. /* NOTE : This function should not be modified, when the callback is needed,
  399. the HAL_QSPI_MspDeInit can be implemented in the user file
  400. */
  401. }
  402. /**
  403. * @}
  404. */
  405. /** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions
  406. * @brief QSPI Transmit/Receive functions
  407. *
  408. @verbatim
  409. ===============================================================================
  410. ##### IO operation functions #####
  411. ===============================================================================
  412. [..]
  413. This subsection provides a set of functions allowing to :
  414. (+) Handle the interrupts.
  415. (+) Handle the command sequence.
  416. (+) Transmit data in blocking, interrupt or DMA mode.
  417. (+) Receive data in blocking, interrupt or DMA mode.
  418. (+) Manage the auto-polling functional mode.
  419. (+) Manage the memory-mapped functional mode.
  420. @endverbatim
  421. * @{
  422. */
  423. /**
  424. * @brief Handle QSPI interrupt request.
  425. * @param hqspi QSPI handle
  426. * @retval None
  427. */
  428. void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
  429. {
  430. __IO uint32_t *data_reg;
  431. uint32_t flag = READ_REG(hqspi->Instance->SR);
  432. uint32_t itsource = READ_REG(hqspi->Instance->CR);
  433. /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
  434. if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
  435. {
  436. data_reg = &hqspi->Instance->DR;
  437. if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
  438. {
  439. /* Transmission process */
  440. while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
  441. {
  442. if (hqspi->TxXferCount > 0U)
  443. {
  444. /* Fill the FIFO until the threshold is reached */
  445. *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
  446. hqspi->pTxBuffPtr++;
  447. hqspi->TxXferCount--;
  448. }
  449. else
  450. {
  451. /* No more data available for the transfer */
  452. /* Disable the QSPI FIFO Threshold Interrupt */
  453. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
  454. break;
  455. }
  456. }
  457. }
  458. else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
  459. {
  460. /* Receiving Process */
  461. while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
  462. {
  463. if (hqspi->RxXferCount > 0U)
  464. {
  465. /* Read the FIFO until the threshold is reached */
  466. *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
  467. hqspi->pRxBuffPtr++;
  468. hqspi->RxXferCount--;
  469. }
  470. else
  471. {
  472. /* All data have been received for the transfer */
  473. /* Disable the QSPI FIFO Threshold Interrupt */
  474. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
  475. break;
  476. }
  477. }
  478. }
  479. else
  480. {
  481. /* Nothing to do */
  482. }
  483. /* FIFO Threshold callback */
  484. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  485. hqspi->FifoThresholdCallback(hqspi);
  486. #else
  487. HAL_QSPI_FifoThresholdCallback(hqspi);
  488. #endif
  489. }
  490. /* QSPI Transfer Complete interrupt occurred -------------------------------*/
  491. else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
  492. {
  493. /* Clear interrupt */
  494. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
  495. /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
  496. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
  497. /* Transfer complete callback */
  498. if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
  499. {
  500. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
  501. {
  502. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  503. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  504. /* Disable the DMA channel */
  505. __HAL_DMA_DISABLE(hqspi->hdma);
  506. }
  507. /* Clear Busy bit */
  508. HAL_QSPI_Abort_IT(hqspi);
  509. /* Change state of QSPI */
  510. hqspi->State = HAL_QSPI_STATE_READY;
  511. /* TX Complete callback */
  512. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  513. hqspi->TxCpltCallback(hqspi);
  514. #else
  515. HAL_QSPI_TxCpltCallback(hqspi);
  516. #endif
  517. }
  518. else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
  519. {
  520. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
  521. {
  522. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  523. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  524. /* Disable the DMA channel */
  525. __HAL_DMA_DISABLE(hqspi->hdma);
  526. }
  527. else
  528. {
  529. data_reg = &hqspi->Instance->DR;
  530. while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
  531. {
  532. if (hqspi->RxXferCount > 0U)
  533. {
  534. /* Read the last data received in the FIFO until it is empty */
  535. *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
  536. hqspi->pRxBuffPtr++;
  537. hqspi->RxXferCount--;
  538. }
  539. else
  540. {
  541. /* All data have been received for the transfer */
  542. break;
  543. }
  544. }
  545. }
  546. /* Workaround - Extra data written in the FIFO at the end of a read transfer */
  547. HAL_QSPI_Abort_IT(hqspi);
  548. /* Change state of QSPI */
  549. hqspi->State = HAL_QSPI_STATE_READY;
  550. /* RX Complete callback */
  551. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  552. hqspi->RxCpltCallback(hqspi);
  553. #else
  554. HAL_QSPI_RxCpltCallback(hqspi);
  555. #endif
  556. }
  557. else if(hqspi->State == HAL_QSPI_STATE_BUSY)
  558. {
  559. /* Change state of QSPI */
  560. hqspi->State = HAL_QSPI_STATE_READY;
  561. /* Command Complete callback */
  562. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  563. hqspi->CmdCpltCallback(hqspi);
  564. #else
  565. HAL_QSPI_CmdCpltCallback(hqspi);
  566. #endif
  567. }
  568. else if(hqspi->State == HAL_QSPI_STATE_ABORT)
  569. {
  570. /* Reset functional mode configuration to indirect write mode by default */
  571. CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
  572. /* Change state of QSPI */
  573. hqspi->State = HAL_QSPI_STATE_READY;
  574. if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
  575. {
  576. /* Abort called by the user */
  577. /* Abort Complete callback */
  578. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  579. hqspi->AbortCpltCallback(hqspi);
  580. #else
  581. HAL_QSPI_AbortCpltCallback(hqspi);
  582. #endif
  583. }
  584. else
  585. {
  586. /* Abort due to an error (eg : DMA error) */
  587. /* Error callback */
  588. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  589. hqspi->ErrorCallback(hqspi);
  590. #else
  591. HAL_QSPI_ErrorCallback(hqspi);
  592. #endif
  593. }
  594. }
  595. else
  596. {
  597. /* Nothing to do */
  598. }
  599. }
  600. /* QSPI Status Match interrupt occurred ------------------------------------*/
  601. else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
  602. {
  603. /* Clear interrupt */
  604. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
  605. /* Check if the automatic poll mode stop is activated */
  606. if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
  607. {
  608. /* Disable the QSPI Transfer Error and Status Match Interrupts */
  609. __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
  610. /* Change state of QSPI */
  611. hqspi->State = HAL_QSPI_STATE_READY;
  612. }
  613. /* Status match callback */
  614. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  615. hqspi->StatusMatchCallback(hqspi);
  616. #else
  617. HAL_QSPI_StatusMatchCallback(hqspi);
  618. #endif
  619. }
  620. /* QSPI Transfer Error interrupt occurred ----------------------------------*/
  621. else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
  622. {
  623. /* Clear interrupt */
  624. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
  625. /* Disable all the QSPI Interrupts */
  626. __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
  627. /* Set error code */
  628. hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
  629. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
  630. {
  631. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  632. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  633. /* Disable the DMA channel */
  634. hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
  635. if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
  636. {
  637. /* Set error code to DMA */
  638. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  639. /* Change state of QSPI */
  640. hqspi->State = HAL_QSPI_STATE_READY;
  641. /* Error callback */
  642. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  643. hqspi->ErrorCallback(hqspi);
  644. #else
  645. HAL_QSPI_ErrorCallback(hqspi);
  646. #endif
  647. }
  648. }
  649. else
  650. {
  651. /* Change state of QSPI */
  652. hqspi->State = HAL_QSPI_STATE_READY;
  653. /* Error callback */
  654. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  655. hqspi->ErrorCallback(hqspi);
  656. #else
  657. HAL_QSPI_ErrorCallback(hqspi);
  658. #endif
  659. }
  660. }
  661. /* QSPI Timeout interrupt occurred -----------------------------------------*/
  662. else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
  663. {
  664. /* Clear interrupt */
  665. WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
  666. /* Timeout callback */
  667. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  668. hqspi->TimeOutCallback(hqspi);
  669. #else
  670. HAL_QSPI_TimeOutCallback(hqspi);
  671. #endif
  672. }
  673. else
  674. {
  675. /* Nothing to do */
  676. }
  677. }
  678. /**
  679. * @brief Set the command configuration.
  680. * @param hqspi QSPI handle
  681. * @param cmd : structure that contains the command configuration information
  682. * @param Timeout Timeout duration
  683. * @note This function is used only in Indirect Read or Write Modes
  684. * @retval HAL status
  685. */
  686. HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
  687. {
  688. HAL_StatusTypeDef status;
  689. uint32_t tickstart = HAL_GetTick();
  690. /* Check the parameters */
  691. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  692. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  693. {
  694. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  695. }
  696. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  697. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  698. {
  699. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  700. }
  701. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  702. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  703. {
  704. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  705. }
  706. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  707. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  708. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  709. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  710. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  711. /* Process locked */
  712. __HAL_LOCK(hqspi);
  713. if(hqspi->State == HAL_QSPI_STATE_READY)
  714. {
  715. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  716. /* Update QSPI state */
  717. hqspi->State = HAL_QSPI_STATE_BUSY;
  718. /* Wait till BUSY flag reset */
  719. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
  720. if (status == HAL_OK)
  721. {
  722. /* Call the configuration function */
  723. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  724. if (cmd->DataMode == QSPI_DATA_NONE)
  725. {
  726. /* When there is no data phase, the transfer start as soon as the configuration is done
  727. so wait until TC flag is set to go back in idle state */
  728. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  729. if (status == HAL_OK)
  730. {
  731. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  732. /* Update QSPI state */
  733. hqspi->State = HAL_QSPI_STATE_READY;
  734. }
  735. }
  736. else
  737. {
  738. /* Update QSPI state */
  739. hqspi->State = HAL_QSPI_STATE_READY;
  740. }
  741. }
  742. }
  743. else
  744. {
  745. status = HAL_BUSY;
  746. }
  747. /* Process unlocked */
  748. __HAL_UNLOCK(hqspi);
  749. /* Return function status */
  750. return status;
  751. }
  752. /**
  753. * @brief Set the command configuration in interrupt mode.
  754. * @param hqspi QSPI handle
  755. * @param cmd structure that contains the command configuration information
  756. * @note This function is used only in Indirect Read or Write Modes
  757. * @retval HAL status
  758. */
  759. HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
  760. {
  761. HAL_StatusTypeDef status;
  762. /* Check the parameters */
  763. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  764. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  765. {
  766. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  767. }
  768. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  769. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  770. {
  771. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  772. }
  773. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  774. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  775. {
  776. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  777. }
  778. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  779. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  780. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  781. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  782. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  783. /* Process locked */
  784. __HAL_LOCK(hqspi);
  785. if(hqspi->State == HAL_QSPI_STATE_READY)
  786. {
  787. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  788. /* Update QSPI state */
  789. hqspi->State = HAL_QSPI_STATE_BUSY;
  790. /* Wait till BUSY flag reset */
  791. status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
  792. if (status == HAL_OK)
  793. {
  794. if (cmd->DataMode == QSPI_DATA_NONE)
  795. {
  796. /* Clear interrupt */
  797. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  798. }
  799. /* Call the configuration function */
  800. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  801. if (cmd->DataMode == QSPI_DATA_NONE)
  802. {
  803. /* When there is no data phase, the transfer start as soon as the configuration is done
  804. so activate TC and TE interrupts */
  805. /* Process unlocked */
  806. __HAL_UNLOCK(hqspi);
  807. /* Enable the QSPI Transfer Error Interrupt */
  808. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
  809. }
  810. else
  811. {
  812. /* Update QSPI state */
  813. hqspi->State = HAL_QSPI_STATE_READY;
  814. /* Process unlocked */
  815. __HAL_UNLOCK(hqspi);
  816. }
  817. }
  818. else
  819. {
  820. /* Process unlocked */
  821. __HAL_UNLOCK(hqspi);
  822. }
  823. }
  824. else
  825. {
  826. status = HAL_BUSY;
  827. /* Process unlocked */
  828. __HAL_UNLOCK(hqspi);
  829. }
  830. /* Return function status */
  831. return status;
  832. }
  833. /**
  834. * @brief Transmit an amount of data in blocking mode.
  835. * @param hqspi QSPI handle
  836. * @param pData pointer to data buffer
  837. * @param Timeout Timeout duration
  838. * @note This function is used only in Indirect Write Mode
  839. * @retval HAL status
  840. */
  841. HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
  842. {
  843. HAL_StatusTypeDef status = HAL_OK;
  844. uint32_t tickstart = HAL_GetTick();
  845. __IO uint32_t *data_reg = &hqspi->Instance->DR;
  846. /* Process locked */
  847. __HAL_LOCK(hqspi);
  848. if(hqspi->State == HAL_QSPI_STATE_READY)
  849. {
  850. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  851. if(pData != NULL )
  852. {
  853. /* Update state */
  854. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  855. /* Configure counters and size of the handle */
  856. hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
  857. hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
  858. hqspi->pTxBuffPtr = pData;
  859. /* Configure QSPI: CCR register with functional as indirect write */
  860. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  861. while(hqspi->TxXferCount > 0U)
  862. {
  863. /* Wait until FT flag is set to send data */
  864. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
  865. if (status != HAL_OK)
  866. {
  867. break;
  868. }
  869. *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
  870. hqspi->pTxBuffPtr++;
  871. hqspi->TxXferCount--;
  872. }
  873. if (status == HAL_OK)
  874. {
  875. /* Wait until TC flag is set to go back in idle state */
  876. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  877. if (status == HAL_OK)
  878. {
  879. /* Clear Transfer Complete bit */
  880. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  881. /* Clear Busy bit */
  882. status = HAL_QSPI_Abort(hqspi);
  883. }
  884. }
  885. /* Update QSPI state */
  886. hqspi->State = HAL_QSPI_STATE_READY;
  887. }
  888. else
  889. {
  890. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  891. status = HAL_ERROR;
  892. }
  893. }
  894. else
  895. {
  896. status = HAL_BUSY;
  897. }
  898. /* Process unlocked */
  899. __HAL_UNLOCK(hqspi);
  900. return status;
  901. }
  902. /**
  903. * @brief Receive an amount of data in blocking mode.
  904. * @param hqspi QSPI handle
  905. * @param pData pointer to data buffer
  906. * @param Timeout Timeout duration
  907. * @note This function is used only in Indirect Read Mode
  908. * @retval HAL status
  909. */
  910. HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
  911. {
  912. HAL_StatusTypeDef status = HAL_OK;
  913. uint32_t tickstart = HAL_GetTick();
  914. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  915. __IO uint32_t *data_reg = &hqspi->Instance->DR;
  916. /* Process locked */
  917. __HAL_LOCK(hqspi);
  918. if(hqspi->State == HAL_QSPI_STATE_READY)
  919. {
  920. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  921. if(pData != NULL )
  922. {
  923. /* Update state */
  924. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  925. /* Configure counters and size of the handle */
  926. hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
  927. hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
  928. hqspi->pRxBuffPtr = pData;
  929. /* Configure QSPI: CCR register with functional as indirect read */
  930. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  931. /* Start the transfer by re-writing the address in AR register */
  932. WRITE_REG(hqspi->Instance->AR, addr_reg);
  933. while(hqspi->RxXferCount > 0U)
  934. {
  935. /* Wait until FT or TC flag is set to read received data */
  936. status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
  937. if (status != HAL_OK)
  938. {
  939. break;
  940. }
  941. *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
  942. hqspi->pRxBuffPtr++;
  943. hqspi->RxXferCount--;
  944. }
  945. if (status == HAL_OK)
  946. {
  947. /* Wait until TC flag is set to go back in idle state */
  948. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
  949. if (status == HAL_OK)
  950. {
  951. /* Clear Transfer Complete bit */
  952. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  953. /* Workaround - Extra data written in the FIFO at the end of a read transfer */
  954. status = HAL_QSPI_Abort(hqspi);
  955. }
  956. }
  957. /* Update QSPI state */
  958. hqspi->State = HAL_QSPI_STATE_READY;
  959. }
  960. else
  961. {
  962. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  963. status = HAL_ERROR;
  964. }
  965. }
  966. else
  967. {
  968. status = HAL_BUSY;
  969. }
  970. /* Process unlocked */
  971. __HAL_UNLOCK(hqspi);
  972. return status;
  973. }
  974. /**
  975. * @brief Send an amount of data in non-blocking mode with interrupt.
  976. * @param hqspi QSPI handle
  977. * @param pData pointer to data buffer
  978. * @note This function is used only in Indirect Write Mode
  979. * @retval HAL status
  980. */
  981. HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  982. {
  983. HAL_StatusTypeDef status = HAL_OK;
  984. /* Process locked */
  985. __HAL_LOCK(hqspi);
  986. if(hqspi->State == HAL_QSPI_STATE_READY)
  987. {
  988. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  989. if(pData != NULL )
  990. {
  991. /* Update state */
  992. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  993. /* Configure counters and size of the handle */
  994. hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
  995. hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
  996. hqspi->pTxBuffPtr = pData;
  997. /* Clear interrupt */
  998. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  999. /* Configure QSPI: CCR register with functional as indirect write */
  1000. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  1001. /* Process unlocked */
  1002. __HAL_UNLOCK(hqspi);
  1003. /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
  1004. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
  1005. }
  1006. else
  1007. {
  1008. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1009. status = HAL_ERROR;
  1010. /* Process unlocked */
  1011. __HAL_UNLOCK(hqspi);
  1012. }
  1013. }
  1014. else
  1015. {
  1016. status = HAL_BUSY;
  1017. /* Process unlocked */
  1018. __HAL_UNLOCK(hqspi);
  1019. }
  1020. return status;
  1021. }
  1022. /**
  1023. * @brief Receive an amount of data in non-blocking mode with interrupt.
  1024. * @param hqspi QSPI handle
  1025. * @param pData pointer to data buffer
  1026. * @note This function is used only in Indirect Read Mode
  1027. * @retval HAL status
  1028. */
  1029. HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  1030. {
  1031. HAL_StatusTypeDef status = HAL_OK;
  1032. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  1033. /* Process locked */
  1034. __HAL_LOCK(hqspi);
  1035. if(hqspi->State == HAL_QSPI_STATE_READY)
  1036. {
  1037. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1038. if(pData != NULL )
  1039. {
  1040. /* Update state */
  1041. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  1042. /* Configure counters and size of the handle */
  1043. hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
  1044. hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
  1045. hqspi->pRxBuffPtr = pData;
  1046. /* Clear interrupt */
  1047. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
  1048. /* Configure QSPI: CCR register with functional as indirect read */
  1049. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  1050. /* Start the transfer by re-writing the address in AR register */
  1051. WRITE_REG(hqspi->Instance->AR, addr_reg);
  1052. /* Process unlocked */
  1053. __HAL_UNLOCK(hqspi);
  1054. /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
  1055. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
  1056. }
  1057. else
  1058. {
  1059. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1060. status = HAL_ERROR;
  1061. /* Process unlocked */
  1062. __HAL_UNLOCK(hqspi);
  1063. }
  1064. }
  1065. else
  1066. {
  1067. status = HAL_BUSY;
  1068. /* Process unlocked */
  1069. __HAL_UNLOCK(hqspi);
  1070. }
  1071. return status;
  1072. }
  1073. /**
  1074. * @brief Send an amount of data in non-blocking mode with DMA.
  1075. * @param hqspi QSPI handle
  1076. * @param pData pointer to data buffer
  1077. * @note This function is used only in Indirect Write Mode
  1078. * @note If DMA peripheral access is configured as halfword, the number
  1079. * of data and the fifo threshold should be aligned on halfword
  1080. * @note If DMA peripheral access is configured as word, the number
  1081. * of data and the fifo threshold should be aligned on word
  1082. * @retval HAL status
  1083. */
  1084. HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  1085. {
  1086. HAL_StatusTypeDef status = HAL_OK;
  1087. uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
  1088. /* Process locked */
  1089. __HAL_LOCK(hqspi);
  1090. if(hqspi->State == HAL_QSPI_STATE_READY)
  1091. {
  1092. /* Clear the error code */
  1093. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1094. if(pData != NULL )
  1095. {
  1096. /* Configure counters of the handle */
  1097. if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
  1098. {
  1099. hqspi->TxXferCount = data_size;
  1100. }
  1101. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
  1102. {
  1103. if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
  1104. {
  1105. /* The number of data or the fifo threshold is not aligned on halfword
  1106. => no transfer possible with DMA peripheral access configured as halfword */
  1107. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1108. status = HAL_ERROR;
  1109. /* Process unlocked */
  1110. __HAL_UNLOCK(hqspi);
  1111. }
  1112. else
  1113. {
  1114. hqspi->TxXferCount = (data_size >> 1U);
  1115. }
  1116. }
  1117. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
  1118. {
  1119. if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
  1120. {
  1121. /* The number of data or the fifo threshold is not aligned on word
  1122. => no transfer possible with DMA peripheral access configured as word */
  1123. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1124. status = HAL_ERROR;
  1125. /* Process unlocked */
  1126. __HAL_UNLOCK(hqspi);
  1127. }
  1128. else
  1129. {
  1130. hqspi->TxXferCount = (data_size >> 2U);
  1131. }
  1132. }
  1133. else
  1134. {
  1135. /* Nothing to do */
  1136. }
  1137. if (status == HAL_OK)
  1138. {
  1139. /* Update state */
  1140. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
  1141. /* Clear interrupt */
  1142. __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
  1143. /* Configure size and pointer of the handle */
  1144. hqspi->TxXferSize = hqspi->TxXferCount;
  1145. hqspi->pTxBuffPtr = pData;
  1146. /* Configure QSPI: CCR register with functional mode as indirect write */
  1147. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
  1148. /* Set the QSPI DMA transfer complete callback */
  1149. hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
  1150. /* Set the QSPI DMA Half transfer complete callback */
  1151. hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
  1152. /* Set the DMA error callback */
  1153. hqspi->hdma->XferErrorCallback = QSPI_DMAError;
  1154. /* Clear the DMA abort callback */
  1155. hqspi->hdma->XferAbortCallback = NULL;
  1156. #if defined (QSPI1_V2_1L)
  1157. /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
  1158. AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
  1159. Change the following configuration of DMA peripheral
  1160. - Enable peripheral increment
  1161. - Disable memory increment
  1162. - Set DMA direction as peripheral to memory mode */
  1163. /* Enable peripheral increment mode of the DMA */
  1164. hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
  1165. /* Disable memory increment mode of the DMA */
  1166. hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
  1167. /* Update peripheral/memory increment mode bits */
  1168. MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
  1169. /* Configure the direction of the DMA */
  1170. hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
  1171. #else
  1172. /* Configure the direction of the DMA */
  1173. hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
  1174. #endif /* QSPI1_V2_1L */
  1175. /* Update direction mode bit */
  1176. MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
  1177. /* Enable the QSPI transmit DMA Channel */
  1178. if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK)
  1179. {
  1180. /* Process unlocked */
  1181. __HAL_UNLOCK(hqspi);
  1182. /* Enable the QSPI transfer error Interrupt */
  1183. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
  1184. /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
  1185. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1186. }
  1187. else
  1188. {
  1189. status = HAL_ERROR;
  1190. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  1191. hqspi->State = HAL_QSPI_STATE_READY;
  1192. /* Process unlocked */
  1193. __HAL_UNLOCK(hqspi);
  1194. }
  1195. }
  1196. }
  1197. else
  1198. {
  1199. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1200. status = HAL_ERROR;
  1201. /* Process unlocked */
  1202. __HAL_UNLOCK(hqspi);
  1203. }
  1204. }
  1205. else
  1206. {
  1207. status = HAL_BUSY;
  1208. /* Process unlocked */
  1209. __HAL_UNLOCK(hqspi);
  1210. }
  1211. return status;
  1212. }
  1213. /**
  1214. * @brief Receive an amount of data in non-blocking mode with DMA.
  1215. * @param hqspi QSPI handle
  1216. * @param pData pointer to data buffer.
  1217. * @note This function is used only in Indirect Read Mode
  1218. * @note If DMA peripheral access is configured as halfword, the number
  1219. * of data and the fifo threshold should be aligned on halfword
  1220. * @note If DMA peripheral access is configured as word, the number
  1221. * of data and the fifo threshold should be aligned on word
  1222. * @retval HAL status
  1223. */
  1224. HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
  1225. {
  1226. HAL_StatusTypeDef status = HAL_OK;
  1227. uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
  1228. uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
  1229. /* Process locked */
  1230. __HAL_LOCK(hqspi);
  1231. if(hqspi->State == HAL_QSPI_STATE_READY)
  1232. {
  1233. /* Clear the error code */
  1234. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1235. if(pData != NULL )
  1236. {
  1237. /* Configure counters of the handle */
  1238. if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
  1239. {
  1240. hqspi->RxXferCount = data_size;
  1241. }
  1242. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
  1243. {
  1244. if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
  1245. {
  1246. /* The number of data or the fifo threshold is not aligned on halfword
  1247. => no transfer possible with DMA peripheral access configured as halfword */
  1248. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1249. status = HAL_ERROR;
  1250. /* Process unlocked */
  1251. __HAL_UNLOCK(hqspi);
  1252. }
  1253. else
  1254. {
  1255. hqspi->RxXferCount = (data_size >> 1U);
  1256. }
  1257. }
  1258. else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
  1259. {
  1260. if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
  1261. {
  1262. /* The number of data or the fifo threshold is not aligned on word
  1263. => no transfer possible with DMA peripheral access configured as word */
  1264. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1265. status = HAL_ERROR;
  1266. /* Process unlocked */
  1267. __HAL_UNLOCK(hqspi);
  1268. }
  1269. else
  1270. {
  1271. hqspi->RxXferCount = (data_size >> 2U);
  1272. }
  1273. }
  1274. else
  1275. {
  1276. /* Nothing to do */
  1277. }
  1278. if (status == HAL_OK)
  1279. {
  1280. /* Update state */
  1281. hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
  1282. /* Clear interrupt */
  1283. __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
  1284. /* Configure size and pointer of the handle */
  1285. hqspi->RxXferSize = hqspi->RxXferCount;
  1286. hqspi->pRxBuffPtr = pData;
  1287. /* Set the QSPI DMA transfer complete callback */
  1288. hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
  1289. /* Set the QSPI DMA Half transfer complete callback */
  1290. hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
  1291. /* Set the DMA error callback */
  1292. hqspi->hdma->XferErrorCallback = QSPI_DMAError;
  1293. /* Clear the DMA abort callback */
  1294. hqspi->hdma->XferAbortCallback = NULL;
  1295. #if defined (QSPI1_V2_1L)
  1296. /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
  1297. AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
  1298. Change the following configuration of DMA peripheral
  1299. - Enable peripheral increment
  1300. - Disable memory increment
  1301. - Set DMA direction as memory to peripheral mode
  1302. - 4 Extra words (32-bits) are added for read operation to guarantee
  1303. the last data is transferred from DMA FIFO to RAM memory */
  1304. /* Enable peripheral increment of the DMA */
  1305. hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
  1306. /* Disable memory increment of the DMA */
  1307. hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
  1308. /* Update peripheral/memory increment mode bits */
  1309. MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
  1310. /* Configure the direction of the DMA */
  1311. hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
  1312. /* 4 Extra words (32-bits) are needed for read operation to guarantee
  1313. the last data is transferred from DMA FIFO to RAM memory */
  1314. WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
  1315. /* Update direction mode bit */
  1316. MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
  1317. /* Configure QSPI: CCR register with functional as indirect read */
  1318. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  1319. /* Start the transfer by re-writing the address in AR register */
  1320. WRITE_REG(hqspi->Instance->AR, addr_reg);
  1321. /* Enable the DMA Channel */
  1322. if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK)
  1323. {
  1324. /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
  1325. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1326. /* Process unlocked */
  1327. __HAL_UNLOCK(hqspi);
  1328. /* Enable the QSPI transfer error Interrupt */
  1329. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
  1330. }
  1331. else
  1332. {
  1333. status = HAL_ERROR;
  1334. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  1335. hqspi->State = HAL_QSPI_STATE_READY;
  1336. /* Process unlocked */
  1337. __HAL_UNLOCK(hqspi);
  1338. }
  1339. #else
  1340. /* Configure the direction of the DMA */
  1341. hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
  1342. /* Update direction mode bit */
  1343. MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
  1344. /* Enable the DMA Channel */
  1345. if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK)
  1346. {
  1347. /* Configure QSPI: CCR register with functional as indirect read */
  1348. MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
  1349. /* Start the transfer by re-writing the address in AR register */
  1350. WRITE_REG(hqspi->Instance->AR, addr_reg);
  1351. /* Process unlocked */
  1352. __HAL_UNLOCK(hqspi);
  1353. /* Enable the QSPI transfer error Interrupt */
  1354. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
  1355. /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
  1356. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  1357. }
  1358. else
  1359. {
  1360. status = HAL_ERROR;
  1361. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  1362. hqspi->State = HAL_QSPI_STATE_READY;
  1363. /* Process unlocked */
  1364. __HAL_UNLOCK(hqspi);
  1365. }
  1366. #endif /* QSPI1_V2_1L */
  1367. }
  1368. }
  1369. else
  1370. {
  1371. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
  1372. status = HAL_ERROR;
  1373. /* Process unlocked */
  1374. __HAL_UNLOCK(hqspi);
  1375. }
  1376. }
  1377. else
  1378. {
  1379. status = HAL_BUSY;
  1380. /* Process unlocked */
  1381. __HAL_UNLOCK(hqspi);
  1382. }
  1383. return status;
  1384. }
  1385. /**
  1386. * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
  1387. * @param hqspi QSPI handle
  1388. * @param cmd structure that contains the command configuration information.
  1389. * @param cfg structure that contains the polling configuration information.
  1390. * @param Timeout Timeout duration
  1391. * @note This function is used only in Automatic Polling Mode
  1392. * @retval HAL status
  1393. */
  1394. HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
  1395. {
  1396. HAL_StatusTypeDef status;
  1397. uint32_t tickstart = HAL_GetTick();
  1398. /* Check the parameters */
  1399. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1400. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1401. {
  1402. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1403. }
  1404. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1405. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1406. {
  1407. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1408. }
  1409. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1410. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1411. {
  1412. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1413. }
  1414. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1415. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1416. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1417. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1418. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1419. assert_param(IS_QSPI_INTERVAL(cfg->Interval));
  1420. assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
  1421. assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
  1422. /* Process locked */
  1423. __HAL_LOCK(hqspi);
  1424. if(hqspi->State == HAL_QSPI_STATE_READY)
  1425. {
  1426. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1427. /* Update state */
  1428. hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
  1429. /* Wait till BUSY flag reset */
  1430. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
  1431. if (status == HAL_OK)
  1432. {
  1433. /* Configure QSPI: PSMAR register with the status match value */
  1434. WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
  1435. /* Configure QSPI: PSMKR register with the status mask value */
  1436. WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
  1437. /* Configure QSPI: PIR register with the interval value */
  1438. WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
  1439. /* Configure QSPI: CR register with Match mode and Automatic stop enabled
  1440. (otherwise there will be an infinite loop in blocking mode) */
  1441. MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
  1442. (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
  1443. /* Call the configuration function */
  1444. cmd->NbData = cfg->StatusBytesSize;
  1445. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
  1446. /* Wait until SM flag is set to go back in idle state */
  1447. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
  1448. if (status == HAL_OK)
  1449. {
  1450. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
  1451. /* Update state */
  1452. hqspi->State = HAL_QSPI_STATE_READY;
  1453. }
  1454. }
  1455. }
  1456. else
  1457. {
  1458. status = HAL_BUSY;
  1459. }
  1460. /* Process unlocked */
  1461. __HAL_UNLOCK(hqspi);
  1462. /* Return function status */
  1463. return status;
  1464. }
  1465. /**
  1466. * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
  1467. * @param hqspi QSPI handle
  1468. * @param cmd structure that contains the command configuration information.
  1469. * @param cfg structure that contains the polling configuration information.
  1470. * @note This function is used only in Automatic Polling Mode
  1471. * @retval HAL status
  1472. */
  1473. HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
  1474. {
  1475. HAL_StatusTypeDef status;
  1476. /* Check the parameters */
  1477. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1478. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1479. {
  1480. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1481. }
  1482. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1483. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1484. {
  1485. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1486. }
  1487. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1488. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1489. {
  1490. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1491. }
  1492. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1493. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1494. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1495. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1496. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1497. assert_param(IS_QSPI_INTERVAL(cfg->Interval));
  1498. assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
  1499. assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
  1500. assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
  1501. /* Process locked */
  1502. __HAL_LOCK(hqspi);
  1503. if(hqspi->State == HAL_QSPI_STATE_READY)
  1504. {
  1505. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1506. /* Update state */
  1507. hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
  1508. /* Wait till BUSY flag reset */
  1509. status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
  1510. if (status == HAL_OK)
  1511. {
  1512. /* Configure QSPI: PSMAR register with the status match value */
  1513. WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
  1514. /* Configure QSPI: PSMKR register with the status mask value */
  1515. WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
  1516. /* Configure QSPI: PIR register with the interval value */
  1517. WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
  1518. /* Configure QSPI: CR register with Match mode and Automatic stop mode */
  1519. MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
  1520. (cfg->MatchMode | cfg->AutomaticStop));
  1521. /* Clear interrupt */
  1522. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
  1523. /* Call the configuration function */
  1524. cmd->NbData = cfg->StatusBytesSize;
  1525. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
  1526. /* Process unlocked */
  1527. __HAL_UNLOCK(hqspi);
  1528. /* Enable the QSPI Transfer Error and status match Interrupt */
  1529. __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
  1530. }
  1531. else
  1532. {
  1533. /* Process unlocked */
  1534. __HAL_UNLOCK(hqspi);
  1535. }
  1536. }
  1537. else
  1538. {
  1539. status = HAL_BUSY;
  1540. /* Process unlocked */
  1541. __HAL_UNLOCK(hqspi);
  1542. }
  1543. /* Return function status */
  1544. return status;
  1545. }
  1546. /**
  1547. * @brief Configure the Memory Mapped mode.
  1548. * @param hqspi QSPI handle
  1549. * @param cmd structure that contains the command configuration information.
  1550. * @param cfg structure that contains the memory mapped configuration information.
  1551. * @note This function is used only in Memory mapped Mode
  1552. * @retval HAL status
  1553. */
  1554. HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
  1555. {
  1556. HAL_StatusTypeDef status;
  1557. uint32_t tickstart = HAL_GetTick();
  1558. /* Check the parameters */
  1559. assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
  1560. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  1561. {
  1562. assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
  1563. }
  1564. assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
  1565. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  1566. {
  1567. assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
  1568. }
  1569. assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
  1570. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  1571. {
  1572. assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
  1573. }
  1574. assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
  1575. assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
  1576. assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
  1577. assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
  1578. assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
  1579. assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
  1580. /* Process locked */
  1581. __HAL_LOCK(hqspi);
  1582. if(hqspi->State == HAL_QSPI_STATE_READY)
  1583. {
  1584. hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
  1585. /* Update state */
  1586. hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
  1587. /* Wait till BUSY flag reset */
  1588. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  1589. if (status == HAL_OK)
  1590. {
  1591. /* Configure QSPI: CR register with timeout counter enable */
  1592. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
  1593. if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
  1594. {
  1595. assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
  1596. /* Configure QSPI: LPTR register with the low-power timeout value */
  1597. WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
  1598. /* Clear interrupt */
  1599. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
  1600. /* Enable the QSPI TimeOut Interrupt */
  1601. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
  1602. }
  1603. /* Call the configuration function */
  1604. QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
  1605. }
  1606. }
  1607. else
  1608. {
  1609. status = HAL_BUSY;
  1610. }
  1611. /* Process unlocked */
  1612. __HAL_UNLOCK(hqspi);
  1613. /* Return function status */
  1614. return status;
  1615. }
  1616. /**
  1617. * @brief Transfer Error callback.
  1618. * @param hqspi QSPI handle
  1619. * @retval None
  1620. */
  1621. __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
  1622. {
  1623. /* Prevent unused argument(s) compilation warning */
  1624. UNUSED(hqspi);
  1625. /* NOTE : This function should not be modified, when the callback is needed,
  1626. the HAL_QSPI_ErrorCallback could be implemented in the user file
  1627. */
  1628. }
  1629. /**
  1630. * @brief Abort completed callback.
  1631. * @param hqspi QSPI handle
  1632. * @retval None
  1633. */
  1634. __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
  1635. {
  1636. /* Prevent unused argument(s) compilation warning */
  1637. UNUSED(hqspi);
  1638. /* NOTE: This function should not be modified, when the callback is needed,
  1639. the HAL_QSPI_AbortCpltCallback could be implemented in the user file
  1640. */
  1641. }
  1642. /**
  1643. * @brief Command completed callback.
  1644. * @param hqspi QSPI handle
  1645. * @retval None
  1646. */
  1647. __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
  1648. {
  1649. /* Prevent unused argument(s) compilation warning */
  1650. UNUSED(hqspi);
  1651. /* NOTE: This function should not be modified, when the callback is needed,
  1652. the HAL_QSPI_CmdCpltCallback could be implemented in the user file
  1653. */
  1654. }
  1655. /**
  1656. * @brief Rx Transfer completed callback.
  1657. * @param hqspi QSPI handle
  1658. * @retval None
  1659. */
  1660. __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
  1661. {
  1662. /* Prevent unused argument(s) compilation warning */
  1663. UNUSED(hqspi);
  1664. /* NOTE: This function should not be modified, when the callback is needed,
  1665. the HAL_QSPI_RxCpltCallback could be implemented in the user file
  1666. */
  1667. }
  1668. /**
  1669. * @brief Tx Transfer completed callback.
  1670. * @param hqspi QSPI handle
  1671. * @retval None
  1672. */
  1673. __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
  1674. {
  1675. /* Prevent unused argument(s) compilation warning */
  1676. UNUSED(hqspi);
  1677. /* NOTE: This function should not be modified, when the callback is needed,
  1678. the HAL_QSPI_TxCpltCallback could be implemented in the user file
  1679. */
  1680. }
  1681. /**
  1682. * @brief Rx Half Transfer completed callback.
  1683. * @param hqspi QSPI handle
  1684. * @retval None
  1685. */
  1686. __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
  1687. {
  1688. /* Prevent unused argument(s) compilation warning */
  1689. UNUSED(hqspi);
  1690. /* NOTE: This function should not be modified, when the callback is needed,
  1691. the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
  1692. */
  1693. }
  1694. /**
  1695. * @brief Tx Half Transfer completed callback.
  1696. * @param hqspi QSPI handle
  1697. * @retval None
  1698. */
  1699. __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
  1700. {
  1701. /* Prevent unused argument(s) compilation warning */
  1702. UNUSED(hqspi);
  1703. /* NOTE: This function should not be modified, when the callback is needed,
  1704. the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
  1705. */
  1706. }
  1707. /**
  1708. * @brief FIFO Threshold callback.
  1709. * @param hqspi QSPI handle
  1710. * @retval None
  1711. */
  1712. __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
  1713. {
  1714. /* Prevent unused argument(s) compilation warning */
  1715. UNUSED(hqspi);
  1716. /* NOTE : This function should not be modified, when the callback is needed,
  1717. the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
  1718. */
  1719. }
  1720. /**
  1721. * @brief Status Match callback.
  1722. * @param hqspi QSPI handle
  1723. * @retval None
  1724. */
  1725. __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
  1726. {
  1727. /* Prevent unused argument(s) compilation warning */
  1728. UNUSED(hqspi);
  1729. /* NOTE : This function should not be modified, when the callback is needed,
  1730. the HAL_QSPI_StatusMatchCallback could be implemented in the user file
  1731. */
  1732. }
  1733. /**
  1734. * @brief Timeout callback.
  1735. * @param hqspi QSPI handle
  1736. * @retval None
  1737. */
  1738. __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
  1739. {
  1740. /* Prevent unused argument(s) compilation warning */
  1741. UNUSED(hqspi);
  1742. /* NOTE : This function should not be modified, when the callback is needed,
  1743. the HAL_QSPI_TimeOutCallback could be implemented in the user file
  1744. */
  1745. }
  1746. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  1747. /**
  1748. * @brief Register a User QSPI Callback
  1749. * To be used instead of the weak (surcharged) predefined callback
  1750. * @param hqspi QSPI handle
  1751. * @param CallbackId ID of the callback to be registered
  1752. * This parameter can be one of the following values:
  1753. * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
  1754. * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
  1755. * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
  1756. * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
  1757. * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
  1758. * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
  1759. * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
  1760. * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
  1761. * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
  1762. * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
  1763. * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
  1764. * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
  1765. * @param pCallback pointer to the Callback function
  1766. * @retval status
  1767. */
  1768. HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
  1769. {
  1770. HAL_StatusTypeDef status = HAL_OK;
  1771. if(pCallback == NULL)
  1772. {
  1773. /* Update the error code */
  1774. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1775. return HAL_ERROR;
  1776. }
  1777. /* Process locked */
  1778. __HAL_LOCK(hqspi);
  1779. if(hqspi->State == HAL_QSPI_STATE_READY)
  1780. {
  1781. switch (CallbackId)
  1782. {
  1783. case HAL_QSPI_ERROR_CB_ID :
  1784. hqspi->ErrorCallback = pCallback;
  1785. break;
  1786. case HAL_QSPI_ABORT_CB_ID :
  1787. hqspi->AbortCpltCallback = pCallback;
  1788. break;
  1789. case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
  1790. hqspi->FifoThresholdCallback = pCallback;
  1791. break;
  1792. case HAL_QSPI_CMD_CPLT_CB_ID :
  1793. hqspi->CmdCpltCallback = pCallback;
  1794. break;
  1795. case HAL_QSPI_RX_CPLT_CB_ID :
  1796. hqspi->RxCpltCallback = pCallback;
  1797. break;
  1798. case HAL_QSPI_TX_CPLT_CB_ID :
  1799. hqspi->TxCpltCallback = pCallback;
  1800. break;
  1801. case HAL_QSPI_RX_HALF_CPLT_CB_ID :
  1802. hqspi->RxHalfCpltCallback = pCallback;
  1803. break;
  1804. case HAL_QSPI_TX_HALF_CPLT_CB_ID :
  1805. hqspi->TxHalfCpltCallback = pCallback;
  1806. break;
  1807. case HAL_QSPI_STATUS_MATCH_CB_ID :
  1808. hqspi->StatusMatchCallback = pCallback;
  1809. break;
  1810. case HAL_QSPI_TIMEOUT_CB_ID :
  1811. hqspi->TimeOutCallback = pCallback;
  1812. break;
  1813. case HAL_QSPI_MSP_INIT_CB_ID :
  1814. hqspi->MspInitCallback = pCallback;
  1815. break;
  1816. case HAL_QSPI_MSP_DEINIT_CB_ID :
  1817. hqspi->MspDeInitCallback = pCallback;
  1818. break;
  1819. default :
  1820. /* Update the error code */
  1821. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1822. /* update return status */
  1823. status = HAL_ERROR;
  1824. break;
  1825. }
  1826. }
  1827. else if (hqspi->State == HAL_QSPI_STATE_RESET)
  1828. {
  1829. switch (CallbackId)
  1830. {
  1831. case HAL_QSPI_MSP_INIT_CB_ID :
  1832. hqspi->MspInitCallback = pCallback;
  1833. break;
  1834. case HAL_QSPI_MSP_DEINIT_CB_ID :
  1835. hqspi->MspDeInitCallback = pCallback;
  1836. break;
  1837. default :
  1838. /* Update the error code */
  1839. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1840. /* update return status */
  1841. status = HAL_ERROR;
  1842. break;
  1843. }
  1844. }
  1845. else
  1846. {
  1847. /* Update the error code */
  1848. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1849. /* update return status */
  1850. status = HAL_ERROR;
  1851. }
  1852. /* Release Lock */
  1853. __HAL_UNLOCK(hqspi);
  1854. return status;
  1855. }
  1856. /**
  1857. * @brief Unregister a User QSPI Callback
  1858. * QSPI Callback is redirected to the weak (surcharged) predefined callback
  1859. * @param hqspi QSPI handle
  1860. * @param CallbackId ID of the callback to be unregistered
  1861. * This parameter can be one of the following values:
  1862. * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID
  1863. * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID
  1864. * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID
  1865. * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID
  1866. * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID
  1867. * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID
  1868. * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID
  1869. * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID
  1870. * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID
  1871. * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID
  1872. * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID
  1873. * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID
  1874. * @retval status
  1875. */
  1876. HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId)
  1877. {
  1878. HAL_StatusTypeDef status = HAL_OK;
  1879. /* Process locked */
  1880. __HAL_LOCK(hqspi);
  1881. if(hqspi->State == HAL_QSPI_STATE_READY)
  1882. {
  1883. switch (CallbackId)
  1884. {
  1885. case HAL_QSPI_ERROR_CB_ID :
  1886. hqspi->ErrorCallback = HAL_QSPI_ErrorCallback;
  1887. break;
  1888. case HAL_QSPI_ABORT_CB_ID :
  1889. hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback;
  1890. break;
  1891. case HAL_QSPI_FIFO_THRESHOLD_CB_ID :
  1892. hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback;
  1893. break;
  1894. case HAL_QSPI_CMD_CPLT_CB_ID :
  1895. hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback;
  1896. break;
  1897. case HAL_QSPI_RX_CPLT_CB_ID :
  1898. hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback;
  1899. break;
  1900. case HAL_QSPI_TX_CPLT_CB_ID :
  1901. hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback;
  1902. break;
  1903. case HAL_QSPI_RX_HALF_CPLT_CB_ID :
  1904. hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback;
  1905. break;
  1906. case HAL_QSPI_TX_HALF_CPLT_CB_ID :
  1907. hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback;
  1908. break;
  1909. case HAL_QSPI_STATUS_MATCH_CB_ID :
  1910. hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback;
  1911. break;
  1912. case HAL_QSPI_TIMEOUT_CB_ID :
  1913. hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback;
  1914. break;
  1915. case HAL_QSPI_MSP_INIT_CB_ID :
  1916. hqspi->MspInitCallback = HAL_QSPI_MspInit;
  1917. break;
  1918. case HAL_QSPI_MSP_DEINIT_CB_ID :
  1919. hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
  1920. break;
  1921. default :
  1922. /* Update the error code */
  1923. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1924. /* update return status */
  1925. status = HAL_ERROR;
  1926. break;
  1927. }
  1928. }
  1929. else if (hqspi->State == HAL_QSPI_STATE_RESET)
  1930. {
  1931. switch (CallbackId)
  1932. {
  1933. case HAL_QSPI_MSP_INIT_CB_ID :
  1934. hqspi->MspInitCallback = HAL_QSPI_MspInit;
  1935. break;
  1936. case HAL_QSPI_MSP_DEINIT_CB_ID :
  1937. hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit;
  1938. break;
  1939. default :
  1940. /* Update the error code */
  1941. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1942. /* update return status */
  1943. status = HAL_ERROR;
  1944. break;
  1945. }
  1946. }
  1947. else
  1948. {
  1949. /* Update the error code */
  1950. hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK;
  1951. /* update return status */
  1952. status = HAL_ERROR;
  1953. }
  1954. /* Release Lock */
  1955. __HAL_UNLOCK(hqspi);
  1956. return status;
  1957. }
  1958. #endif
  1959. /**
  1960. * @}
  1961. */
  1962. /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
  1963. * @brief QSPI control and State functions
  1964. *
  1965. @verbatim
  1966. ===============================================================================
  1967. ##### Peripheral Control and State functions #####
  1968. ===============================================================================
  1969. [..]
  1970. This subsection provides a set of functions allowing to :
  1971. (+) Check in run-time the state of the driver.
  1972. (+) Check the error code set during last operation.
  1973. (+) Abort any operation.
  1974. @endverbatim
  1975. * @{
  1976. */
  1977. /**
  1978. * @brief Return the QSPI handle state.
  1979. * @param hqspi QSPI handle
  1980. * @retval HAL state
  1981. */
  1982. HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
  1983. {
  1984. /* Return QSPI handle state */
  1985. return hqspi->State;
  1986. }
  1987. /**
  1988. * @brief Return the QSPI error code.
  1989. * @param hqspi QSPI handle
  1990. * @retval QSPI Error Code
  1991. */
  1992. uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
  1993. {
  1994. return hqspi->ErrorCode;
  1995. }
  1996. /**
  1997. * @brief Abort the current transmission.
  1998. * @param hqspi QSPI handle
  1999. * @retval HAL status
  2000. */
  2001. HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
  2002. {
  2003. HAL_StatusTypeDef status = HAL_OK;
  2004. uint32_t tickstart = HAL_GetTick();
  2005. /* Check if the state is in one of the busy states */
  2006. if (((uint32_t)hqspi->State & 0x2U) != 0U)
  2007. {
  2008. /* Process unlocked */
  2009. __HAL_UNLOCK(hqspi);
  2010. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
  2011. {
  2012. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  2013. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  2014. /* Abort DMA channel */
  2015. status = HAL_DMA_Abort(hqspi->hdma);
  2016. if(status != HAL_OK)
  2017. {
  2018. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  2019. }
  2020. }
  2021. if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
  2022. {
  2023. /* Configure QSPI: CR register with Abort request */
  2024. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  2025. /* Wait until TC flag is set to go back in idle state */
  2026. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
  2027. if (status == HAL_OK)
  2028. {
  2029. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  2030. /* Wait until BUSY flag is reset */
  2031. status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
  2032. }
  2033. if (status == HAL_OK)
  2034. {
  2035. /* Reset functional mode configuration to indirect write mode by default */
  2036. CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
  2037. /* Update state */
  2038. hqspi->State = HAL_QSPI_STATE_READY;
  2039. }
  2040. }
  2041. else
  2042. {
  2043. /* Update state */
  2044. hqspi->State = HAL_QSPI_STATE_READY;
  2045. }
  2046. }
  2047. return status;
  2048. }
  2049. /**
  2050. * @brief Abort the current transmission (non-blocking function)
  2051. * @param hqspi QSPI handle
  2052. * @retval HAL status
  2053. */
  2054. HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
  2055. {
  2056. HAL_StatusTypeDef status = HAL_OK;
  2057. /* Check if the state is in one of the busy states */
  2058. if (((uint32_t)hqspi->State & 0x2U) != 0U)
  2059. {
  2060. /* Process unlocked */
  2061. __HAL_UNLOCK(hqspi);
  2062. /* Update QSPI state */
  2063. hqspi->State = HAL_QSPI_STATE_ABORT;
  2064. /* Disable all interrupts */
  2065. __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
  2066. if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
  2067. {
  2068. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  2069. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  2070. /* Abort DMA channel */
  2071. hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
  2072. if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK)
  2073. {
  2074. /* Change state of QSPI */
  2075. hqspi->State = HAL_QSPI_STATE_READY;
  2076. /* Abort Complete callback */
  2077. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  2078. hqspi->AbortCpltCallback(hqspi);
  2079. #else
  2080. HAL_QSPI_AbortCpltCallback(hqspi);
  2081. #endif
  2082. }
  2083. }
  2084. else
  2085. {
  2086. if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
  2087. {
  2088. /* Clear interrupt */
  2089. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  2090. /* Enable the QSPI Transfer Complete Interrupt */
  2091. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  2092. /* Configure QSPI: CR register with Abort request */
  2093. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  2094. }
  2095. else
  2096. {
  2097. /* Change state of QSPI */
  2098. hqspi->State = HAL_QSPI_STATE_READY;
  2099. }
  2100. }
  2101. }
  2102. return status;
  2103. }
  2104. /** @brief Set QSPI timeout.
  2105. * @param hqspi QSPI handle.
  2106. * @param Timeout Timeout for the QSPI memory access.
  2107. * @retval None
  2108. */
  2109. void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
  2110. {
  2111. hqspi->Timeout = Timeout;
  2112. }
  2113. /** @brief Set QSPI Fifo threshold.
  2114. * @param hqspi QSPI handle.
  2115. * @param Threshold Threshold of the Fifo (value between 1 and 16).
  2116. * @retval HAL status
  2117. */
  2118. HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
  2119. {
  2120. HAL_StatusTypeDef status = HAL_OK;
  2121. /* Process locked */
  2122. __HAL_LOCK(hqspi);
  2123. if(hqspi->State == HAL_QSPI_STATE_READY)
  2124. {
  2125. /* Synchronize init structure with new FIFO threshold value */
  2126. hqspi->Init.FifoThreshold = Threshold;
  2127. /* Configure QSPI FIFO Threshold */
  2128. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
  2129. ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
  2130. }
  2131. else
  2132. {
  2133. status = HAL_BUSY;
  2134. }
  2135. /* Process unlocked */
  2136. __HAL_UNLOCK(hqspi);
  2137. /* Return function status */
  2138. return status;
  2139. }
  2140. /** @brief Get QSPI Fifo threshold.
  2141. * @param hqspi QSPI handle.
  2142. * @retval Fifo threshold (value between 1 and 16)
  2143. */
  2144. uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
  2145. {
  2146. return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
  2147. }
  2148. /** @brief Set FlashID.
  2149. * @param hqspi QSPI handle.
  2150. * @param FlashID Index of the flash memory to be accessed.
  2151. * This parameter can be a value of @ref QSPI_Flash_Select.
  2152. * @note The FlashID is ignored when dual flash mode is enabled.
  2153. * @retval HAL status
  2154. */
  2155. HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID)
  2156. {
  2157. HAL_StatusTypeDef status = HAL_OK;
  2158. /* Check the parameter */
  2159. assert_param(IS_QSPI_FLASH_ID(FlashID));
  2160. /* Process locked */
  2161. __HAL_LOCK(hqspi);
  2162. if(hqspi->State == HAL_QSPI_STATE_READY)
  2163. {
  2164. /* Synchronize init structure with new FlashID value */
  2165. hqspi->Init.FlashID = FlashID;
  2166. /* Configure QSPI FlashID */
  2167. MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID);
  2168. }
  2169. else
  2170. {
  2171. status = HAL_BUSY;
  2172. }
  2173. /* Process unlocked */
  2174. __HAL_UNLOCK(hqspi);
  2175. /* Return function status */
  2176. return status;
  2177. }
  2178. /**
  2179. * @}
  2180. */
  2181. /**
  2182. * @}
  2183. */
  2184. /** @defgroup QSPI_Private_Functions QSPI Private Functions
  2185. * @{
  2186. */
  2187. /**
  2188. * @brief DMA QSPI receive process complete callback.
  2189. * @param hdma DMA handle
  2190. * @retval None
  2191. */
  2192. static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
  2193. {
  2194. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
  2195. hqspi->RxXferCount = 0U;
  2196. /* Enable the QSPI transfer complete Interrupt */
  2197. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  2198. }
  2199. /**
  2200. * @brief DMA QSPI transmit process complete callback.
  2201. * @param hdma DMA handle
  2202. * @retval None
  2203. */
  2204. static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
  2205. {
  2206. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
  2207. hqspi->TxXferCount = 0U;
  2208. /* Enable the QSPI transfer complete Interrupt */
  2209. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  2210. }
  2211. /**
  2212. * @brief DMA QSPI receive process half complete callback.
  2213. * @param hdma DMA handle
  2214. * @retval None
  2215. */
  2216. static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  2217. {
  2218. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
  2219. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  2220. hqspi->RxHalfCpltCallback(hqspi);
  2221. #else
  2222. HAL_QSPI_RxHalfCpltCallback(hqspi);
  2223. #endif
  2224. }
  2225. /**
  2226. * @brief DMA QSPI transmit process half complete callback.
  2227. * @param hdma DMA handle
  2228. * @retval None
  2229. */
  2230. static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  2231. {
  2232. QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent);
  2233. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  2234. hqspi->TxHalfCpltCallback(hqspi);
  2235. #else
  2236. HAL_QSPI_TxHalfCpltCallback(hqspi);
  2237. #endif
  2238. }
  2239. /**
  2240. * @brief DMA QSPI communication error callback.
  2241. * @param hdma DMA handle
  2242. * @retval None
  2243. */
  2244. static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
  2245. {
  2246. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
  2247. /* if DMA error is FIFO error ignore it */
  2248. if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
  2249. {
  2250. hqspi->RxXferCount = 0U;
  2251. hqspi->TxXferCount = 0U;
  2252. hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
  2253. /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
  2254. CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
  2255. /* Abort the QSPI */
  2256. (void)HAL_QSPI_Abort_IT(hqspi);
  2257. }
  2258. }
  2259. /**
  2260. * @brief DMA QSPI abort complete callback.
  2261. * @param hdma DMA handle
  2262. * @retval None
  2263. */
  2264. static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
  2265. {
  2266. QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent);
  2267. hqspi->RxXferCount = 0U;
  2268. hqspi->TxXferCount = 0U;
  2269. if(hqspi->State == HAL_QSPI_STATE_ABORT)
  2270. {
  2271. /* DMA Abort called by QSPI abort */
  2272. /* Clear interrupt */
  2273. __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
  2274. /* Enable the QSPI Transfer Complete Interrupt */
  2275. __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
  2276. /* Configure QSPI: CR register with Abort request */
  2277. SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
  2278. }
  2279. else
  2280. {
  2281. /* DMA Abort called due to a transfer error interrupt */
  2282. /* Change state of QSPI */
  2283. hqspi->State = HAL_QSPI_STATE_READY;
  2284. /* Error callback */
  2285. #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
  2286. hqspi->ErrorCallback(hqspi);
  2287. #else
  2288. HAL_QSPI_ErrorCallback(hqspi);
  2289. #endif
  2290. }
  2291. }
  2292. /**
  2293. * @brief Wait for a flag state until timeout.
  2294. * @param hqspi QSPI handle
  2295. * @param Flag Flag checked
  2296. * @param State Value of the flag expected
  2297. * @param Tickstart Tick start value
  2298. * @param Timeout Duration of the timeout
  2299. * @retval HAL status
  2300. */
  2301. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
  2302. FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
  2303. {
  2304. /* Wait until flag is in expected state */
  2305. while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
  2306. {
  2307. /* Check for the Timeout */
  2308. if (Timeout != HAL_MAX_DELAY)
  2309. {
  2310. if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
  2311. {
  2312. hqspi->State = HAL_QSPI_STATE_ERROR;
  2313. hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
  2314. return HAL_ERROR;
  2315. }
  2316. }
  2317. }
  2318. return HAL_OK;
  2319. }
  2320. /**
  2321. * @brief Wait for a flag state until timeout using CPU cycle.
  2322. * @param hqspi : QSPI handle
  2323. * @param Flag : Flag checked
  2324. * @param State : Value of the flag expected
  2325. * @param Timeout : Duration of the timeout
  2326. * @retval HAL status
  2327. */
  2328. static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout)
  2329. {
  2330. __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U);
  2331. do
  2332. {
  2333. if (count-- == 0U)
  2334. {
  2335. hqspi->State = HAL_QSPI_STATE_ERROR;
  2336. hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
  2337. return HAL_TIMEOUT;
  2338. }
  2339. }
  2340. while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State);
  2341. return HAL_OK;
  2342. }
  2343. /**
  2344. * @brief Configure the communication registers.
  2345. * @param hqspi QSPI handle
  2346. * @param cmd structure that contains the command configuration information
  2347. * @param FunctionalMode functional mode to configured
  2348. * This parameter can be one of the following values:
  2349. * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
  2350. * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
  2351. * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
  2352. * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
  2353. * @retval None
  2354. */
  2355. static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
  2356. {
  2357. assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
  2358. if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
  2359. {
  2360. /* Configure QSPI: DLR register with the number of data to read or write */
  2361. WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
  2362. }
  2363. if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
  2364. {
  2365. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  2366. {
  2367. /* Configure QSPI: ABR register with alternate bytes value */
  2368. WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
  2369. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  2370. {
  2371. /*---- Command with instruction, address and alternate bytes ----*/
  2372. /* Configure QSPI: CCR register with all communications parameters */
  2373. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2374. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2375. cmd->AlternateBytesSize | cmd->AlternateByteMode |
  2376. cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
  2377. cmd->Instruction | FunctionalMode));
  2378. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  2379. {
  2380. /* Configure QSPI: AR register with address value */
  2381. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  2382. }
  2383. }
  2384. else
  2385. {
  2386. /*---- Command with instruction and alternate bytes ----*/
  2387. /* Configure QSPI: CCR register with all communications parameters */
  2388. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2389. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2390. cmd->AlternateBytesSize | cmd->AlternateByteMode |
  2391. cmd->AddressMode | cmd->InstructionMode |
  2392. cmd->Instruction | FunctionalMode));
  2393. }
  2394. }
  2395. else
  2396. {
  2397. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  2398. {
  2399. /*---- Command with instruction and address ----*/
  2400. /* Configure QSPI: CCR register with all communications parameters */
  2401. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2402. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2403. cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
  2404. cmd->InstructionMode | cmd->Instruction | FunctionalMode));
  2405. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  2406. {
  2407. /* Configure QSPI: AR register with address value */
  2408. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  2409. }
  2410. }
  2411. else
  2412. {
  2413. /*---- Command with only instruction ----*/
  2414. /* Configure QSPI: CCR register with all communications parameters */
  2415. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2416. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2417. cmd->AlternateByteMode | cmd->AddressMode |
  2418. cmd->InstructionMode | cmd->Instruction | FunctionalMode));
  2419. }
  2420. }
  2421. }
  2422. else
  2423. {
  2424. if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
  2425. {
  2426. /* Configure QSPI: ABR register with alternate bytes value */
  2427. WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
  2428. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  2429. {
  2430. /*---- Command with address and alternate bytes ----*/
  2431. /* Configure QSPI: CCR register with all communications parameters */
  2432. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2433. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2434. cmd->AlternateBytesSize | cmd->AlternateByteMode |
  2435. cmd->AddressSize | cmd->AddressMode |
  2436. cmd->InstructionMode | FunctionalMode));
  2437. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  2438. {
  2439. /* Configure QSPI: AR register with address value */
  2440. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  2441. }
  2442. }
  2443. else
  2444. {
  2445. /*---- Command with only alternate bytes ----*/
  2446. /* Configure QSPI: CCR register with all communications parameters */
  2447. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2448. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2449. cmd->AlternateBytesSize | cmd->AlternateByteMode |
  2450. cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
  2451. }
  2452. }
  2453. else
  2454. {
  2455. if (cmd->AddressMode != QSPI_ADDRESS_NONE)
  2456. {
  2457. /*---- Command with only address ----*/
  2458. /* Configure QSPI: CCR register with all communications parameters */
  2459. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2460. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2461. cmd->AlternateByteMode | cmd->AddressSize |
  2462. cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
  2463. if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
  2464. {
  2465. /* Configure QSPI: AR register with address value */
  2466. WRITE_REG(hqspi->Instance->AR, cmd->Address);
  2467. }
  2468. }
  2469. else
  2470. {
  2471. /*---- Command with only data phase ----*/
  2472. if (cmd->DataMode != QSPI_DATA_NONE)
  2473. {
  2474. /* Configure QSPI: CCR register with all communications parameters */
  2475. WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
  2476. cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) |
  2477. cmd->AlternateByteMode | cmd->AddressMode |
  2478. cmd->InstructionMode | FunctionalMode));
  2479. }
  2480. }
  2481. }
  2482. }
  2483. }
  2484. /**
  2485. * @}
  2486. */
  2487. /**
  2488. * @}
  2489. */
  2490. #endif /* HAL_QSPI_MODULE_ENABLED */
  2491. /**
  2492. * @}
  2493. */
  2494. /**
  2495. * @}
  2496. */
  2497. #endif /* defined(QUADSPI) */