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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_nor.c
  4. * @author MCD Application Team
  5. * @brief NOR HAL module driver.
  6. * This file provides a generic firmware to drive NOR memories mounted
  7. * as external device.
  8. *
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2016 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. @verbatim
  21. ==============================================================================
  22. ##### How to use this driver #####
  23. ==============================================================================
  24. [..]
  25. This driver is a generic layered driver which contains a set of APIs used to
  26. control NOR flash memories. It uses the FMC/FSMC layer functions to interface
  27. with NOR devices. This driver is used as follows:
  28. (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
  29. with control and timing parameters for both normal and extended mode.
  30. (+) Read NOR flash memory manufacturer code and device IDs using the function
  31. HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
  32. structure declared by the function caller.
  33. (+) Access NOR flash memory by read/write data unit operations using the functions
  34. HAL_NOR_Read(), HAL_NOR_Program().
  35. (+) Perform NOR flash erase block/chip operations using the functions
  36. HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
  37. (+) Read the NOR flash CFI (common flash interface) IDs using the function
  38. HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
  39. structure declared by the function caller.
  40. (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
  41. HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
  42. (+) You can monitor the NOR device HAL state by calling the function
  43. HAL_NOR_GetState()
  44. [..]
  45. (@) This driver is a set of generic APIs which handle standard NOR flash operations.
  46. If a NOR flash device contains different operations and/or implementations,
  47. it should be implemented separately.
  48. *** NOR HAL driver macros list ***
  49. =============================================
  50. [..]
  51. Below the list of most used macros in NOR HAL driver.
  52. (+) NOR_WRITE : NOR memory write data to specified address
  53. *** Callback registration ***
  54. =============================================
  55. [..]
  56. The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
  57. allows the user to configure dynamically the driver callbacks.
  58. Use Functions HAL_NOR_RegisterCallback() to register a user callback,
  59. it allows to register following callbacks:
  60. (+) MspInitCallback : NOR MspInit.
  61. (+) MspDeInitCallback : NOR MspDeInit.
  62. This function takes as parameters the HAL peripheral handle, the Callback ID
  63. and a pointer to the user callback function.
  64. Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
  65. weak (surcharged) function. It allows to reset following callbacks:
  66. (+) MspInitCallback : NOR MspInit.
  67. (+) MspDeInitCallback : NOR MspDeInit.
  68. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  69. By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
  70. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  71. Exception done for MspInit and MspDeInit callbacks that are respectively
  72. reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
  73. and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
  74. If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
  75. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  76. Callbacks can be registered/unregistered in READY state only.
  77. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  78. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  79. during the Init/DeInit.
  80. In that case first register the MspInit/MspDeInit user callbacks
  81. using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
  82. or HAL_NOR_Init function.
  83. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
  84. not defined, the callback registering feature is not available
  85. and weak (surcharged) callbacks are used.
  86. @endverbatim
  87. ******************************************************************************
  88. */
  89. /* Includes ------------------------------------------------------------------*/
  90. #include "stm32f4xx_hal.h"
  91. #if defined(FMC_Bank1) || defined(FSMC_Bank1)
  92. /** @addtogroup STM32F4xx_HAL_Driver
  93. * @{
  94. */
  95. #ifdef HAL_NOR_MODULE_ENABLED
  96. /** @defgroup NOR NOR
  97. * @brief NOR driver modules
  98. * @{
  99. */
  100. /* Private typedef -----------------------------------------------------------*/
  101. /* Private define ------------------------------------------------------------*/
  102. /** @defgroup NOR_Private_Defines NOR Private Defines
  103. * @{
  104. */
  105. /* Constants to define address to set to write a command */
  106. #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
  107. #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
  108. #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
  109. #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
  110. #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
  111. #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
  112. #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
  113. /* Constants to define data to program a command */
  114. #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
  115. #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
  116. #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
  117. #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
  118. #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
  119. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
  120. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
  121. #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
  122. #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
  123. #define NOR_CMD_DATA_CFI (uint16_t)0x0098
  124. #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
  125. #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
  126. #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
  127. #define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
  128. #define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
  129. #define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
  130. #define NOR_CMD_CONFIRM (uint16_t)0x00D0
  131. #define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
  132. #define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
  133. #define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
  134. #define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
  135. /* Mask on NOR STATUS REGISTER */
  136. #define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
  137. #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
  138. #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
  139. #define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
  140. /* Address of the primary command set */
  141. #define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
  142. /* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
  143. #define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
  144. #define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
  145. #define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
  146. #define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
  147. #define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
  148. #define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
  149. #define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
  150. #define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
  151. #define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
  152. #define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
  153. /**
  154. * @}
  155. */
  156. /* Private macro -------------------------------------------------------------*/
  157. /* Private variables ---------------------------------------------------------*/
  158. /** @defgroup NOR_Private_Variables NOR Private Variables
  159. * @{
  160. */
  161. static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
  162. /**
  163. * @}
  164. */
  165. /* Private functions ---------------------------------------------------------*/
  166. /* Exported functions --------------------------------------------------------*/
  167. /** @defgroup NOR_Exported_Functions NOR Exported Functions
  168. * @{
  169. */
  170. /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
  171. * @brief Initialization and Configuration functions
  172. *
  173. @verbatim
  174. ==============================================================================
  175. ##### NOR Initialization and de_initialization functions #####
  176. ==============================================================================
  177. [..]
  178. This section provides functions allowing to initialize/de-initialize
  179. the NOR memory
  180. @endverbatim
  181. * @{
  182. */
  183. /**
  184. * @brief Perform the NOR memory Initialization sequence
  185. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  186. * the configuration information for NOR module.
  187. * @param Timing pointer to NOR control timing structure
  188. * @param ExtTiming pointer to NOR extended mode timing structure
  189. * @retval HAL status
  190. */
  191. HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
  192. FMC_NORSRAM_TimingTypeDef *ExtTiming)
  193. {
  194. uint32_t deviceaddress;
  195. HAL_StatusTypeDef status = HAL_OK;
  196. /* Check the NOR handle parameter */
  197. if (hnor == NULL)
  198. {
  199. return HAL_ERROR;
  200. }
  201. if (hnor->State == HAL_NOR_STATE_RESET)
  202. {
  203. /* Allocate lock resource and initialize it */
  204. hnor->Lock = HAL_UNLOCKED;
  205. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  206. if (hnor->MspInitCallback == NULL)
  207. {
  208. hnor->MspInitCallback = HAL_NOR_MspInit;
  209. }
  210. /* Init the low level hardware */
  211. hnor->MspInitCallback(hnor);
  212. #else
  213. /* Initialize the low level hardware (MSP) */
  214. HAL_NOR_MspInit(hnor);
  215. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  216. }
  217. /* Initialize NOR control Interface */
  218. (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
  219. /* Initialize NOR timing Interface */
  220. (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
  221. /* Initialize NOR extended mode timing Interface */
  222. (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
  223. /* Enable the NORSRAM device */
  224. __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
  225. /* Initialize NOR Memory Data Width*/
  226. if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
  227. {
  228. uwNORMemoryDataWidth = NOR_MEMORY_8B;
  229. }
  230. else
  231. {
  232. uwNORMemoryDataWidth = NOR_MEMORY_16B;
  233. }
  234. /* Initialize the NOR controller state */
  235. hnor->State = HAL_NOR_STATE_READY;
  236. /* Select the NOR device address */
  237. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  238. {
  239. deviceaddress = NOR_MEMORY_ADRESS1;
  240. }
  241. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  242. {
  243. deviceaddress = NOR_MEMORY_ADRESS2;
  244. }
  245. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  246. {
  247. deviceaddress = NOR_MEMORY_ADRESS3;
  248. }
  249. else /* FMC_NORSRAM_BANK4 */
  250. {
  251. deviceaddress = NOR_MEMORY_ADRESS4;
  252. }
  253. if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
  254. {
  255. (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
  256. /* Update the NOR controller state */
  257. hnor->State = HAL_NOR_STATE_PROTECTED;
  258. }
  259. else
  260. {
  261. /* Get the value of the command set */
  262. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
  263. hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
  264. status = HAL_NOR_ReturnToReadMode(hnor);
  265. }
  266. return status;
  267. }
  268. /**
  269. * @brief Perform NOR memory De-Initialization sequence
  270. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  271. * the configuration information for NOR module.
  272. * @retval HAL status
  273. */
  274. HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
  275. {
  276. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  277. if (hnor->MspDeInitCallback == NULL)
  278. {
  279. hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
  280. }
  281. /* DeInit the low level hardware */
  282. hnor->MspDeInitCallback(hnor);
  283. #else
  284. /* De-Initialize the low level hardware (MSP) */
  285. HAL_NOR_MspDeInit(hnor);
  286. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  287. /* Configure the NOR registers with their reset values */
  288. (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
  289. /* Reset the NOR controller state */
  290. hnor->State = HAL_NOR_STATE_RESET;
  291. /* Release Lock */
  292. __HAL_UNLOCK(hnor);
  293. return HAL_OK;
  294. }
  295. /**
  296. * @brief NOR MSP Init
  297. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  298. * the configuration information for NOR module.
  299. * @retval None
  300. */
  301. __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
  302. {
  303. /* Prevent unused argument(s) compilation warning */
  304. UNUSED(hnor);
  305. /* NOTE : This function Should not be modified, when the callback is needed,
  306. the HAL_NOR_MspInit could be implemented in the user file
  307. */
  308. }
  309. /**
  310. * @brief NOR MSP DeInit
  311. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  312. * the configuration information for NOR module.
  313. * @retval None
  314. */
  315. __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
  316. {
  317. /* Prevent unused argument(s) compilation warning */
  318. UNUSED(hnor);
  319. /* NOTE : This function Should not be modified, when the callback is needed,
  320. the HAL_NOR_MspDeInit could be implemented in the user file
  321. */
  322. }
  323. /**
  324. * @brief NOR MSP Wait for Ready/Busy signal
  325. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  326. * the configuration information for NOR module.
  327. * @param Timeout Maximum timeout value
  328. * @retval None
  329. */
  330. __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
  331. {
  332. /* Prevent unused argument(s) compilation warning */
  333. UNUSED(hnor);
  334. UNUSED(Timeout);
  335. /* NOTE : This function Should not be modified, when the callback is needed,
  336. the HAL_NOR_MspWait could be implemented in the user file
  337. */
  338. }
  339. /**
  340. * @}
  341. */
  342. /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
  343. * @brief Input Output and memory control functions
  344. *
  345. @verbatim
  346. ==============================================================================
  347. ##### NOR Input and Output functions #####
  348. ==============================================================================
  349. [..]
  350. This section provides functions allowing to use and control the NOR memory
  351. @endverbatim
  352. * @{
  353. */
  354. /**
  355. * @brief Read NOR flash IDs
  356. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  357. * the configuration information for NOR module.
  358. * @param pNOR_ID pointer to NOR ID structure
  359. * @retval HAL status
  360. */
  361. HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
  362. {
  363. uint32_t deviceaddress;
  364. HAL_NOR_StateTypeDef state;
  365. HAL_StatusTypeDef status = HAL_OK;
  366. /* Check the NOR controller state */
  367. state = hnor->State;
  368. if (state == HAL_NOR_STATE_BUSY)
  369. {
  370. return HAL_BUSY;
  371. }
  372. else if (state == HAL_NOR_STATE_PROTECTED)
  373. {
  374. return HAL_ERROR;
  375. }
  376. else if (state == HAL_NOR_STATE_READY)
  377. {
  378. /* Process Locked */
  379. __HAL_LOCK(hnor);
  380. /* Update the NOR controller state */
  381. hnor->State = HAL_NOR_STATE_BUSY;
  382. /* Select the NOR device address */
  383. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  384. {
  385. deviceaddress = NOR_MEMORY_ADRESS1;
  386. }
  387. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  388. {
  389. deviceaddress = NOR_MEMORY_ADRESS2;
  390. }
  391. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  392. {
  393. deviceaddress = NOR_MEMORY_ADRESS3;
  394. }
  395. else /* FMC_NORSRAM_BANK4 */
  396. {
  397. deviceaddress = NOR_MEMORY_ADRESS4;
  398. }
  399. /* Send read ID command */
  400. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  401. {
  402. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  403. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  404. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
  405. }
  406. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  407. {
  408. NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
  409. }
  410. else
  411. {
  412. /* Primary command set not supported by the driver */
  413. status = HAL_ERROR;
  414. }
  415. if (status != HAL_ERROR)
  416. {
  417. /* Read the NOR IDs */
  418. pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
  419. pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
  420. DEVICE_CODE1_ADDR);
  421. pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
  422. DEVICE_CODE2_ADDR);
  423. pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
  424. DEVICE_CODE3_ADDR);
  425. }
  426. /* Check the NOR controller state */
  427. hnor->State = state;
  428. /* Process unlocked */
  429. __HAL_UNLOCK(hnor);
  430. }
  431. else
  432. {
  433. return HAL_ERROR;
  434. }
  435. return status;
  436. }
  437. /**
  438. * @brief Returns the NOR memory to Read mode.
  439. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  440. * the configuration information for NOR module.
  441. * @retval HAL status
  442. */
  443. HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
  444. {
  445. uint32_t deviceaddress;
  446. HAL_NOR_StateTypeDef state;
  447. HAL_StatusTypeDef status = HAL_OK;
  448. /* Check the NOR controller state */
  449. state = hnor->State;
  450. if (state == HAL_NOR_STATE_BUSY)
  451. {
  452. return HAL_BUSY;
  453. }
  454. else if (state == HAL_NOR_STATE_PROTECTED)
  455. {
  456. return HAL_ERROR;
  457. }
  458. else if (state == HAL_NOR_STATE_READY)
  459. {
  460. /* Process Locked */
  461. __HAL_LOCK(hnor);
  462. /* Update the NOR controller state */
  463. hnor->State = HAL_NOR_STATE_BUSY;
  464. /* Select the NOR device address */
  465. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  466. {
  467. deviceaddress = NOR_MEMORY_ADRESS1;
  468. }
  469. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  470. {
  471. deviceaddress = NOR_MEMORY_ADRESS2;
  472. }
  473. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  474. {
  475. deviceaddress = NOR_MEMORY_ADRESS3;
  476. }
  477. else /* FMC_NORSRAM_BANK4 */
  478. {
  479. deviceaddress = NOR_MEMORY_ADRESS4;
  480. }
  481. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  482. {
  483. NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
  484. }
  485. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  486. {
  487. NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
  488. }
  489. else
  490. {
  491. /* Primary command set not supported by the driver */
  492. status = HAL_ERROR;
  493. }
  494. /* Check the NOR controller state */
  495. hnor->State = state;
  496. /* Process unlocked */
  497. __HAL_UNLOCK(hnor);
  498. }
  499. else
  500. {
  501. return HAL_ERROR;
  502. }
  503. return status;
  504. }
  505. /**
  506. * @brief Read data from NOR memory
  507. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  508. * the configuration information for NOR module.
  509. * @param pAddress pointer to Device address
  510. * @param pData pointer to read data
  511. * @retval HAL status
  512. */
  513. HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  514. {
  515. uint32_t deviceaddress;
  516. HAL_NOR_StateTypeDef state;
  517. HAL_StatusTypeDef status = HAL_OK;
  518. /* Check the NOR controller state */
  519. state = hnor->State;
  520. if (state == HAL_NOR_STATE_BUSY)
  521. {
  522. return HAL_BUSY;
  523. }
  524. else if (state == HAL_NOR_STATE_PROTECTED)
  525. {
  526. return HAL_ERROR;
  527. }
  528. else if (state == HAL_NOR_STATE_READY)
  529. {
  530. /* Process Locked */
  531. __HAL_LOCK(hnor);
  532. /* Update the NOR controller state */
  533. hnor->State = HAL_NOR_STATE_BUSY;
  534. /* Select the NOR device address */
  535. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  536. {
  537. deviceaddress = NOR_MEMORY_ADRESS1;
  538. }
  539. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  540. {
  541. deviceaddress = NOR_MEMORY_ADRESS2;
  542. }
  543. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  544. {
  545. deviceaddress = NOR_MEMORY_ADRESS3;
  546. }
  547. else /* FMC_NORSRAM_BANK4 */
  548. {
  549. deviceaddress = NOR_MEMORY_ADRESS4;
  550. }
  551. /* Send read data command */
  552. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  553. {
  554. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  555. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  556. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
  557. }
  558. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  559. {
  560. NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
  561. }
  562. else
  563. {
  564. /* Primary command set not supported by the driver */
  565. status = HAL_ERROR;
  566. }
  567. if (status != HAL_ERROR)
  568. {
  569. /* Read the data */
  570. *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
  571. }
  572. /* Check the NOR controller state */
  573. hnor->State = state;
  574. /* Process unlocked */
  575. __HAL_UNLOCK(hnor);
  576. }
  577. else
  578. {
  579. return HAL_ERROR;
  580. }
  581. return status;
  582. }
  583. /**
  584. * @brief Program data to NOR memory
  585. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  586. * the configuration information for NOR module.
  587. * @param pAddress Device address
  588. * @param pData pointer to the data to write
  589. * @retval HAL status
  590. */
  591. HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
  592. {
  593. uint32_t deviceaddress;
  594. HAL_StatusTypeDef status = HAL_OK;
  595. /* Check the NOR controller state */
  596. if (hnor->State == HAL_NOR_STATE_BUSY)
  597. {
  598. return HAL_BUSY;
  599. }
  600. else if (hnor->State == HAL_NOR_STATE_READY)
  601. {
  602. /* Process Locked */
  603. __HAL_LOCK(hnor);
  604. /* Update the NOR controller state */
  605. hnor->State = HAL_NOR_STATE_BUSY;
  606. /* Select the NOR device address */
  607. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  608. {
  609. deviceaddress = NOR_MEMORY_ADRESS1;
  610. }
  611. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  612. {
  613. deviceaddress = NOR_MEMORY_ADRESS2;
  614. }
  615. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  616. {
  617. deviceaddress = NOR_MEMORY_ADRESS3;
  618. }
  619. else /* FMC_NORSRAM_BANK4 */
  620. {
  621. deviceaddress = NOR_MEMORY_ADRESS4;
  622. }
  623. /* Send program data command */
  624. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  625. {
  626. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  627. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  628. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
  629. }
  630. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  631. {
  632. NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
  633. }
  634. else
  635. {
  636. /* Primary command set not supported by the driver */
  637. status = HAL_ERROR;
  638. }
  639. if (status != HAL_ERROR)
  640. {
  641. /* Write the data */
  642. NOR_WRITE(pAddress, *pData);
  643. }
  644. /* Check the NOR controller state */
  645. hnor->State = HAL_NOR_STATE_READY;
  646. /* Process unlocked */
  647. __HAL_UNLOCK(hnor);
  648. }
  649. else
  650. {
  651. return HAL_ERROR;
  652. }
  653. return status;
  654. }
  655. /**
  656. * @brief Reads a half-word buffer from the NOR memory.
  657. * @param hnor pointer to the NOR handle
  658. * @param uwAddress NOR memory internal address to read from.
  659. * @param pData pointer to the buffer that receives the data read from the
  660. * NOR memory.
  661. * @param uwBufferSize number of Half word to read.
  662. * @retval HAL status
  663. */
  664. HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
  665. uint32_t uwBufferSize)
  666. {
  667. uint32_t deviceaddress;
  668. uint32_t size = uwBufferSize;
  669. uint32_t address = uwAddress;
  670. uint16_t *data = pData;
  671. HAL_NOR_StateTypeDef state;
  672. HAL_StatusTypeDef status = HAL_OK;
  673. /* Check the NOR controller state */
  674. state = hnor->State;
  675. if (state == HAL_NOR_STATE_BUSY)
  676. {
  677. return HAL_BUSY;
  678. }
  679. else if (state == HAL_NOR_STATE_PROTECTED)
  680. {
  681. return HAL_ERROR;
  682. }
  683. else if (state == HAL_NOR_STATE_READY)
  684. {
  685. /* Process Locked */
  686. __HAL_LOCK(hnor);
  687. /* Update the NOR controller state */
  688. hnor->State = HAL_NOR_STATE_BUSY;
  689. /* Select the NOR device address */
  690. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  691. {
  692. deviceaddress = NOR_MEMORY_ADRESS1;
  693. }
  694. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  695. {
  696. deviceaddress = NOR_MEMORY_ADRESS2;
  697. }
  698. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  699. {
  700. deviceaddress = NOR_MEMORY_ADRESS3;
  701. }
  702. else /* FMC_NORSRAM_BANK4 */
  703. {
  704. deviceaddress = NOR_MEMORY_ADRESS4;
  705. }
  706. /* Send read data command */
  707. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  708. {
  709. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  710. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  711. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
  712. }
  713. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  714. {
  715. NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
  716. }
  717. else
  718. {
  719. /* Primary command set not supported by the driver */
  720. status = HAL_ERROR;
  721. }
  722. if (status != HAL_ERROR)
  723. {
  724. /* Read buffer */
  725. while (size > 0U)
  726. {
  727. *data = *(__IO uint16_t *)address;
  728. data++;
  729. address += 2U;
  730. size--;
  731. }
  732. }
  733. /* Check the NOR controller state */
  734. hnor->State = state;
  735. /* Process unlocked */
  736. __HAL_UNLOCK(hnor);
  737. }
  738. else
  739. {
  740. return HAL_ERROR;
  741. }
  742. return status;
  743. }
  744. /**
  745. * @brief Writes a half-word buffer to the NOR memory. This function must be used
  746. only with S29GL128P NOR memory.
  747. * @param hnor pointer to the NOR handle
  748. * @param uwAddress NOR memory internal start write address
  749. * @param pData pointer to source data buffer.
  750. * @param uwBufferSize Size of the buffer to write
  751. * @retval HAL status
  752. */
  753. HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
  754. uint32_t uwBufferSize)
  755. {
  756. uint16_t *p_currentaddress;
  757. const uint16_t *p_endaddress;
  758. uint16_t *data = pData;
  759. uint32_t deviceaddress;
  760. HAL_StatusTypeDef status = HAL_OK;
  761. /* Check the NOR controller state */
  762. if (hnor->State == HAL_NOR_STATE_BUSY)
  763. {
  764. return HAL_BUSY;
  765. }
  766. else if (hnor->State == HAL_NOR_STATE_READY)
  767. {
  768. /* Process Locked */
  769. __HAL_LOCK(hnor);
  770. /* Update the NOR controller state */
  771. hnor->State = HAL_NOR_STATE_BUSY;
  772. /* Select the NOR device address */
  773. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  774. {
  775. deviceaddress = NOR_MEMORY_ADRESS1;
  776. }
  777. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  778. {
  779. deviceaddress = NOR_MEMORY_ADRESS2;
  780. }
  781. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  782. {
  783. deviceaddress = NOR_MEMORY_ADRESS3;
  784. }
  785. else /* FMC_NORSRAM_BANK4 */
  786. {
  787. deviceaddress = NOR_MEMORY_ADRESS4;
  788. }
  789. /* Initialize variables */
  790. p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
  791. p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
  792. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  793. {
  794. /* Issue unlock command sequence */
  795. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  796. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  797. /* Write Buffer Load Command */
  798. NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
  799. NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
  800. }
  801. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  802. {
  803. /* Write Buffer Load Command */
  804. NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
  805. NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
  806. }
  807. else
  808. {
  809. /* Primary command set not supported by the driver */
  810. status = HAL_ERROR;
  811. }
  812. if (status != HAL_ERROR)
  813. {
  814. /* Load Data into NOR Buffer */
  815. while (p_currentaddress <= p_endaddress)
  816. {
  817. NOR_WRITE(p_currentaddress, *data);
  818. data++;
  819. p_currentaddress ++;
  820. }
  821. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  822. {
  823. NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
  824. }
  825. else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
  826. {
  827. NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
  828. }
  829. }
  830. /* Check the NOR controller state */
  831. hnor->State = HAL_NOR_STATE_READY;
  832. /* Process unlocked */
  833. __HAL_UNLOCK(hnor);
  834. }
  835. else
  836. {
  837. return HAL_ERROR;
  838. }
  839. return status;
  840. }
  841. /**
  842. * @brief Erase the specified block of the NOR memory
  843. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  844. * the configuration information for NOR module.
  845. * @param BlockAddress Block to erase address
  846. * @param Address Device address
  847. * @retval HAL status
  848. */
  849. HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
  850. {
  851. uint32_t deviceaddress;
  852. HAL_StatusTypeDef status = HAL_OK;
  853. /* Check the NOR controller state */
  854. if (hnor->State == HAL_NOR_STATE_BUSY)
  855. {
  856. return HAL_BUSY;
  857. }
  858. else if (hnor->State == HAL_NOR_STATE_READY)
  859. {
  860. /* Process Locked */
  861. __HAL_LOCK(hnor);
  862. /* Update the NOR controller state */
  863. hnor->State = HAL_NOR_STATE_BUSY;
  864. /* Select the NOR device address */
  865. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  866. {
  867. deviceaddress = NOR_MEMORY_ADRESS1;
  868. }
  869. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  870. {
  871. deviceaddress = NOR_MEMORY_ADRESS2;
  872. }
  873. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  874. {
  875. deviceaddress = NOR_MEMORY_ADRESS3;
  876. }
  877. else /* FMC_NORSRAM_BANK4 */
  878. {
  879. deviceaddress = NOR_MEMORY_ADRESS4;
  880. }
  881. /* Send block erase command sequence */
  882. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  883. {
  884. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  885. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  886. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
  887. NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  888. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
  889. NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  890. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
  891. NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  892. NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
  893. }
  894. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  895. {
  896. NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
  897. NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
  898. NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
  899. NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
  900. }
  901. else
  902. {
  903. /* Primary command set not supported by the driver */
  904. status = HAL_ERROR;
  905. }
  906. /* Check the NOR memory status and update the controller state */
  907. hnor->State = HAL_NOR_STATE_READY;
  908. /* Process unlocked */
  909. __HAL_UNLOCK(hnor);
  910. }
  911. else
  912. {
  913. return HAL_ERROR;
  914. }
  915. return status;
  916. }
  917. /**
  918. * @brief Erase the entire NOR chip.
  919. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  920. * the configuration information for NOR module.
  921. * @param Address Device address
  922. * @retval HAL status
  923. */
  924. HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
  925. {
  926. uint32_t deviceaddress;
  927. HAL_StatusTypeDef status = HAL_OK;
  928. UNUSED(Address);
  929. /* Check the NOR controller state */
  930. if (hnor->State == HAL_NOR_STATE_BUSY)
  931. {
  932. return HAL_BUSY;
  933. }
  934. else if (hnor->State == HAL_NOR_STATE_READY)
  935. {
  936. /* Process Locked */
  937. __HAL_LOCK(hnor);
  938. /* Update the NOR controller state */
  939. hnor->State = HAL_NOR_STATE_BUSY;
  940. /* Select the NOR device address */
  941. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  942. {
  943. deviceaddress = NOR_MEMORY_ADRESS1;
  944. }
  945. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  946. {
  947. deviceaddress = NOR_MEMORY_ADRESS2;
  948. }
  949. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  950. {
  951. deviceaddress = NOR_MEMORY_ADRESS3;
  952. }
  953. else /* FMC_NORSRAM_BANK4 */
  954. {
  955. deviceaddress = NOR_MEMORY_ADRESS4;
  956. }
  957. /* Send NOR chip erase command sequence */
  958. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  959. {
  960. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
  961. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
  962. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
  963. NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
  964. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
  965. NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
  966. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
  967. NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
  968. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
  969. }
  970. else
  971. {
  972. /* Primary command set not supported by the driver */
  973. status = HAL_ERROR;
  974. }
  975. /* Check the NOR memory status and update the controller state */
  976. hnor->State = HAL_NOR_STATE_READY;
  977. /* Process unlocked */
  978. __HAL_UNLOCK(hnor);
  979. }
  980. else
  981. {
  982. return HAL_ERROR;
  983. }
  984. return status;
  985. }
  986. /**
  987. * @brief Read NOR flash CFI IDs
  988. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  989. * the configuration information for NOR module.
  990. * @param pNOR_CFI pointer to NOR CFI IDs structure
  991. * @retval HAL status
  992. */
  993. HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
  994. {
  995. uint32_t deviceaddress;
  996. HAL_NOR_StateTypeDef state;
  997. /* Check the NOR controller state */
  998. state = hnor->State;
  999. if (state == HAL_NOR_STATE_BUSY)
  1000. {
  1001. return HAL_BUSY;
  1002. }
  1003. else if (state == HAL_NOR_STATE_PROTECTED)
  1004. {
  1005. return HAL_ERROR;
  1006. }
  1007. else if (state == HAL_NOR_STATE_READY)
  1008. {
  1009. /* Process Locked */
  1010. __HAL_LOCK(hnor);
  1011. /* Update the NOR controller state */
  1012. hnor->State = HAL_NOR_STATE_BUSY;
  1013. /* Select the NOR device address */
  1014. if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
  1015. {
  1016. deviceaddress = NOR_MEMORY_ADRESS1;
  1017. }
  1018. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
  1019. {
  1020. deviceaddress = NOR_MEMORY_ADRESS2;
  1021. }
  1022. else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
  1023. {
  1024. deviceaddress = NOR_MEMORY_ADRESS3;
  1025. }
  1026. else /* FMC_NORSRAM_BANK4 */
  1027. {
  1028. deviceaddress = NOR_MEMORY_ADRESS4;
  1029. }
  1030. /* Send read CFI query command */
  1031. NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
  1032. /* read the NOR CFI information */
  1033. pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
  1034. pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
  1035. pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
  1036. pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
  1037. /* Check the NOR controller state */
  1038. hnor->State = state;
  1039. /* Process unlocked */
  1040. __HAL_UNLOCK(hnor);
  1041. }
  1042. else
  1043. {
  1044. return HAL_ERROR;
  1045. }
  1046. return HAL_OK;
  1047. }
  1048. #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
  1049. /**
  1050. * @brief Register a User NOR Callback
  1051. * To be used instead of the weak (surcharged) predefined callback
  1052. * @param hnor : NOR handle
  1053. * @param CallbackId : ID of the callback to be registered
  1054. * This parameter can be one of the following values:
  1055. * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  1056. * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
  1057. * @param pCallback : pointer to the Callback function
  1058. * @retval status
  1059. */
  1060. HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
  1061. pNOR_CallbackTypeDef pCallback)
  1062. {
  1063. HAL_StatusTypeDef status = HAL_OK;
  1064. HAL_NOR_StateTypeDef state;
  1065. if (pCallback == NULL)
  1066. {
  1067. return HAL_ERROR;
  1068. }
  1069. /* Process locked */
  1070. __HAL_LOCK(hnor);
  1071. state = hnor->State;
  1072. if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
  1073. {
  1074. switch (CallbackId)
  1075. {
  1076. case HAL_NOR_MSP_INIT_CB_ID :
  1077. hnor->MspInitCallback = pCallback;
  1078. break;
  1079. case HAL_NOR_MSP_DEINIT_CB_ID :
  1080. hnor->MspDeInitCallback = pCallback;
  1081. break;
  1082. default :
  1083. /* update return status */
  1084. status = HAL_ERROR;
  1085. break;
  1086. }
  1087. }
  1088. else
  1089. {
  1090. /* update return status */
  1091. status = HAL_ERROR;
  1092. }
  1093. /* Release Lock */
  1094. __HAL_UNLOCK(hnor);
  1095. return status;
  1096. }
  1097. /**
  1098. * @brief Unregister a User NOR Callback
  1099. * NOR Callback is redirected to the weak (surcharged) predefined callback
  1100. * @param hnor : NOR handle
  1101. * @param CallbackId : ID of the callback to be unregistered
  1102. * This parameter can be one of the following values:
  1103. * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
  1104. * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
  1105. * @retval status
  1106. */
  1107. HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
  1108. {
  1109. HAL_StatusTypeDef status = HAL_OK;
  1110. HAL_NOR_StateTypeDef state;
  1111. /* Process locked */
  1112. __HAL_LOCK(hnor);
  1113. state = hnor->State;
  1114. if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
  1115. {
  1116. switch (CallbackId)
  1117. {
  1118. case HAL_NOR_MSP_INIT_CB_ID :
  1119. hnor->MspInitCallback = HAL_NOR_MspInit;
  1120. break;
  1121. case HAL_NOR_MSP_DEINIT_CB_ID :
  1122. hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
  1123. break;
  1124. default :
  1125. /* update return status */
  1126. status = HAL_ERROR;
  1127. break;
  1128. }
  1129. }
  1130. else
  1131. {
  1132. /* update return status */
  1133. status = HAL_ERROR;
  1134. }
  1135. /* Release Lock */
  1136. __HAL_UNLOCK(hnor);
  1137. return status;
  1138. }
  1139. #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
  1140. /**
  1141. * @}
  1142. */
  1143. /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
  1144. * @brief management functions
  1145. *
  1146. @verbatim
  1147. ==============================================================================
  1148. ##### NOR Control functions #####
  1149. ==============================================================================
  1150. [..]
  1151. This subsection provides a set of functions allowing to control dynamically
  1152. the NOR interface.
  1153. @endverbatim
  1154. * @{
  1155. */
  1156. /**
  1157. * @brief Enables dynamically NOR write operation.
  1158. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1159. * the configuration information for NOR module.
  1160. * @retval HAL status
  1161. */
  1162. HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
  1163. {
  1164. /* Check the NOR controller state */
  1165. if (hnor->State == HAL_NOR_STATE_PROTECTED)
  1166. {
  1167. /* Process Locked */
  1168. __HAL_LOCK(hnor);
  1169. /* Update the NOR controller state */
  1170. hnor->State = HAL_NOR_STATE_BUSY;
  1171. /* Enable write operation */
  1172. (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
  1173. /* Update the NOR controller state */
  1174. hnor->State = HAL_NOR_STATE_READY;
  1175. /* Process unlocked */
  1176. __HAL_UNLOCK(hnor);
  1177. }
  1178. else
  1179. {
  1180. return HAL_ERROR;
  1181. }
  1182. return HAL_OK;
  1183. }
  1184. /**
  1185. * @brief Disables dynamically NOR write operation.
  1186. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1187. * the configuration information for NOR module.
  1188. * @retval HAL status
  1189. */
  1190. HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
  1191. {
  1192. /* Check the NOR controller state */
  1193. if (hnor->State == HAL_NOR_STATE_READY)
  1194. {
  1195. /* Process Locked */
  1196. __HAL_LOCK(hnor);
  1197. /* Update the NOR controller state */
  1198. hnor->State = HAL_NOR_STATE_BUSY;
  1199. /* Disable write operation */
  1200. (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
  1201. /* Update the NOR controller state */
  1202. hnor->State = HAL_NOR_STATE_PROTECTED;
  1203. /* Process unlocked */
  1204. __HAL_UNLOCK(hnor);
  1205. }
  1206. else
  1207. {
  1208. return HAL_ERROR;
  1209. }
  1210. return HAL_OK;
  1211. }
  1212. /**
  1213. * @}
  1214. */
  1215. /** @defgroup NOR_Exported_Functions_Group4 NOR State functions
  1216. * @brief Peripheral State functions
  1217. *
  1218. @verbatim
  1219. ==============================================================================
  1220. ##### NOR State functions #####
  1221. ==============================================================================
  1222. [..]
  1223. This subsection permits to get in run-time the status of the NOR controller
  1224. and the data flow.
  1225. @endverbatim
  1226. * @{
  1227. */
  1228. /**
  1229. * @brief return the NOR controller state
  1230. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1231. * the configuration information for NOR module.
  1232. * @retval NOR controller state
  1233. */
  1234. HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
  1235. {
  1236. return hnor->State;
  1237. }
  1238. /**
  1239. * @brief Returns the NOR operation status.
  1240. * @param hnor pointer to a NOR_HandleTypeDef structure that contains
  1241. * the configuration information for NOR module.
  1242. * @param Address Device address
  1243. * @param Timeout NOR programming Timeout
  1244. * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
  1245. * or HAL_NOR_STATUS_TIMEOUT
  1246. */
  1247. HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
  1248. {
  1249. HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
  1250. uint16_t tmpsr1;
  1251. uint16_t tmpsr2;
  1252. uint32_t tickstart;
  1253. /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
  1254. HAL_NOR_MspWait(hnor, Timeout);
  1255. /* Get the NOR memory operation status -------------------------------------*/
  1256. /* Get tick */
  1257. tickstart = HAL_GetTick();
  1258. if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
  1259. {
  1260. while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
  1261. {
  1262. /* Check for the Timeout */
  1263. if (Timeout != HAL_MAX_DELAY)
  1264. {
  1265. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  1266. {
  1267. status = HAL_NOR_STATUS_TIMEOUT;
  1268. }
  1269. }
  1270. /* Read NOR status register (DQ6 and DQ5) */
  1271. tmpsr1 = *(__IO uint16_t *)Address;
  1272. tmpsr2 = *(__IO uint16_t *)Address;
  1273. /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
  1274. if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
  1275. {
  1276. return HAL_NOR_STATUS_SUCCESS ;
  1277. }
  1278. if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1279. {
  1280. status = HAL_NOR_STATUS_ONGOING;
  1281. }
  1282. tmpsr1 = *(__IO uint16_t *)Address;
  1283. tmpsr2 = *(__IO uint16_t *)Address;
  1284. /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
  1285. if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
  1286. {
  1287. return HAL_NOR_STATUS_SUCCESS;
  1288. }
  1289. if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
  1290. {
  1291. return HAL_NOR_STATUS_ERROR;
  1292. }
  1293. }
  1294. }
  1295. else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
  1296. {
  1297. do
  1298. {
  1299. NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
  1300. tmpsr2 = *(__IO uint16_t *)(Address);
  1301. /* Check for the Timeout */
  1302. if (Timeout != HAL_MAX_DELAY)
  1303. {
  1304. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  1305. {
  1306. return HAL_NOR_STATUS_TIMEOUT;
  1307. }
  1308. }
  1309. } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
  1310. NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
  1311. tmpsr1 = *(__IO uint16_t *)(Address);
  1312. if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
  1313. {
  1314. /* Clear the Status Register */
  1315. NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
  1316. status = HAL_NOR_STATUS_ERROR;
  1317. }
  1318. else
  1319. {
  1320. status = HAL_NOR_STATUS_SUCCESS;
  1321. }
  1322. }
  1323. else
  1324. {
  1325. /* Primary command set not supported by the driver */
  1326. status = HAL_NOR_STATUS_ERROR;
  1327. }
  1328. /* Return the operation status */
  1329. return status;
  1330. }
  1331. /**
  1332. * @}
  1333. */
  1334. /**
  1335. * @}
  1336. */
  1337. /**
  1338. * @}
  1339. */
  1340. #endif /* HAL_NOR_MODULE_ENABLED */
  1341. /**
  1342. * @}
  1343. */
  1344. #endif /* FMC_Bank1 || FSMC_Bank1 */