训练营PLSR题目
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
 
 

2406 lines
74 KiB

  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_nand.c
  4. * @author MCD Application Team
  5. * @brief NAND HAL module driver.
  6. * This file provides a generic firmware to drive NAND memories mounted
  7. * as external device.
  8. *
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2016 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. @verbatim
  21. ==============================================================================
  22. ##### How to use this driver #####
  23. ==============================================================================
  24. [..]
  25. This driver is a generic layered driver which contains a set of APIs used to
  26. control NAND flash memories. It uses the FMC/FSMC layer functions to interface
  27. with NAND devices. This driver is used as follows:
  28. (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
  29. with control and timing parameters for both common and attribute spaces.
  30. (+) Read NAND flash memory maker and device IDs using the function
  31. HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
  32. structure declared by the function caller.
  33. (+) Access NAND flash memory by read/write operations using the functions
  34. HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
  35. HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
  36. HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
  37. HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
  38. to read/write page(s)/spare area(s). These functions use specific device
  39. information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
  40. structure. The read/write address information is contained by the Nand_Address_Typedef
  41. structure passed as parameter.
  42. (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
  43. (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
  44. The erase block address information is contained in the Nand_Address_Typedef
  45. structure passed as parameter.
  46. (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
  47. (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
  48. HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
  49. feature or the function HAL_NAND_GetECC() to get the ECC correction code.
  50. (+) You can monitor the NAND device HAL state by calling the function
  51. HAL_NAND_GetState()
  52. [..]
  53. (@) This driver is a set of generic APIs which handle standard NAND flash operations.
  54. If a NAND flash device contains different operations and/or implementations,
  55. it should be implemented separately.
  56. *** Callback registration ***
  57. =============================================
  58. [..]
  59. The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
  60. allows the user to configure dynamically the driver callbacks.
  61. Use Functions HAL_NAND_RegisterCallback() to register a user callback,
  62. it allows to register following callbacks:
  63. (+) MspInitCallback : NAND MspInit.
  64. (+) MspDeInitCallback : NAND MspDeInit.
  65. This function takes as parameters the HAL peripheral handle, the Callback ID
  66. and a pointer to the user callback function.
  67. Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
  68. weak (surcharged) function. It allows to reset following callbacks:
  69. (+) MspInitCallback : NAND MspInit.
  70. (+) MspDeInitCallback : NAND MspDeInit.
  71. This function) takes as parameters the HAL peripheral handle and the Callback ID.
  72. By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
  73. all callbacks are reset to the corresponding legacy weak (surcharged) functions.
  74. Exception done for MspInit and MspDeInit callbacks that are respectively
  75. reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
  76. and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
  77. If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
  78. keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
  79. Callbacks can be registered/unregistered in READY state only.
  80. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
  81. in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
  82. during the Init/DeInit.
  83. In that case first register the MspInit/MspDeInit user callbacks
  84. using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
  85. or HAL_NAND_Init function.
  86. When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
  87. not defined, the callback registering feature is not available
  88. and weak (surcharged) callbacks are used.
  89. @endverbatim
  90. ******************************************************************************
  91. */
  92. /* Includes ------------------------------------------------------------------*/
  93. #include "stm32f4xx_hal.h"
  94. #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  95. /** @addtogroup STM32F4xx_HAL_Driver
  96. * @{
  97. */
  98. #ifdef HAL_NAND_MODULE_ENABLED
  99. /** @defgroup NAND NAND
  100. * @brief NAND HAL module driver
  101. * @{
  102. */
  103. /* Private typedef -----------------------------------------------------------*/
  104. /* Private Constants ------------------------------------------------------------*/
  105. /* Private macro -------------------------------------------------------------*/
  106. /* Private variables ---------------------------------------------------------*/
  107. /* Private function prototypes -----------------------------------------------*/
  108. /* Exported functions ---------------------------------------------------------*/
  109. /** @defgroup NAND_Exported_Functions NAND Exported Functions
  110. * @{
  111. */
  112. /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
  113. * @brief Initialization and Configuration functions
  114. *
  115. @verbatim
  116. ==============================================================================
  117. ##### NAND Initialization and de-initialization functions #####
  118. ==============================================================================
  119. [..]
  120. This section provides functions allowing to initialize/de-initialize
  121. the NAND memory
  122. @endverbatim
  123. * @{
  124. */
  125. /**
  126. * @brief Perform NAND memory Initialization sequence
  127. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  128. * the configuration information for NAND module.
  129. * @param ComSpace_Timing pointer to Common space timing structure
  130. * @param AttSpace_Timing pointer to Attribute space timing structure
  131. * @retval HAL status
  132. */
  133. HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
  134. FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
  135. {
  136. /* Check the NAND handle state */
  137. if (hnand == NULL)
  138. {
  139. return HAL_ERROR;
  140. }
  141. if (hnand->State == HAL_NAND_STATE_RESET)
  142. {
  143. /* Allocate lock resource and initialize it */
  144. hnand->Lock = HAL_UNLOCKED;
  145. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  146. if (hnand->MspInitCallback == NULL)
  147. {
  148. hnand->MspInitCallback = HAL_NAND_MspInit;
  149. }
  150. hnand->ItCallback = HAL_NAND_ITCallback;
  151. /* Init the low level hardware */
  152. hnand->MspInitCallback(hnand);
  153. #else
  154. /* Initialize the low level hardware (MSP) */
  155. HAL_NAND_MspInit(hnand);
  156. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  157. }
  158. /* Initialize NAND control Interface */
  159. (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
  160. /* Initialize NAND common space timing Interface */
  161. (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
  162. /* Initialize NAND attribute space timing Interface */
  163. (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
  164. /* Enable the NAND device */
  165. #if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  166. __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
  167. #else
  168. __FMC_NAND_ENABLE(hnand->Instance);
  169. #endif
  170. /* Update the NAND controller state */
  171. hnand->State = HAL_NAND_STATE_READY;
  172. return HAL_OK;
  173. }
  174. /**
  175. * @brief Perform NAND memory De-Initialization sequence
  176. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  177. * the configuration information for NAND module.
  178. * @retval HAL status
  179. */
  180. HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
  181. {
  182. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  183. if (hnand->MspDeInitCallback == NULL)
  184. {
  185. hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
  186. }
  187. /* DeInit the low level hardware */
  188. hnand->MspDeInitCallback(hnand);
  189. #else
  190. /* Initialize the low level hardware (MSP) */
  191. HAL_NAND_MspDeInit(hnand);
  192. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  193. /* Configure the NAND registers with their reset values */
  194. (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
  195. /* Reset the NAND controller state */
  196. hnand->State = HAL_NAND_STATE_RESET;
  197. /* Release Lock */
  198. __HAL_UNLOCK(hnand);
  199. return HAL_OK;
  200. }
  201. /**
  202. * @brief NAND MSP Init
  203. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  204. * the configuration information for NAND module.
  205. * @retval None
  206. */
  207. __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
  208. {
  209. /* Prevent unused argument(s) compilation warning */
  210. UNUSED(hnand);
  211. /* NOTE : This function Should not be modified, when the callback is needed,
  212. the HAL_NAND_MspInit could be implemented in the user file
  213. */
  214. }
  215. /**
  216. * @brief NAND MSP DeInit
  217. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  218. * the configuration information for NAND module.
  219. * @retval None
  220. */
  221. __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
  222. {
  223. /* Prevent unused argument(s) compilation warning */
  224. UNUSED(hnand);
  225. /* NOTE : This function Should not be modified, when the callback is needed,
  226. the HAL_NAND_MspDeInit could be implemented in the user file
  227. */
  228. }
  229. /**
  230. * @brief This function handles NAND device interrupt request.
  231. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  232. * the configuration information for NAND module.
  233. * @retval HAL status
  234. */
  235. void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
  236. {
  237. /* Check NAND interrupt Rising edge flag */
  238. if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
  239. {
  240. /* NAND interrupt callback*/
  241. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  242. hnand->ItCallback(hnand);
  243. #else
  244. HAL_NAND_ITCallback(hnand);
  245. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  246. /* Clear NAND interrupt Rising edge pending bit */
  247. #if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  248. __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
  249. #else
  250. __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
  251. #endif /* FMC_Bank2_3 || FSMC_Bank2_3 */
  252. }
  253. /* Check NAND interrupt Level flag */
  254. if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
  255. {
  256. /* NAND interrupt callback*/
  257. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  258. hnand->ItCallback(hnand);
  259. #else
  260. HAL_NAND_ITCallback(hnand);
  261. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  262. /* Clear NAND interrupt Level pending bit */
  263. #if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  264. __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
  265. #else
  266. __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
  267. #endif /* FMC_Bank2_3 || FSMC_Bank2_3 */
  268. }
  269. /* Check NAND interrupt Falling edge flag */
  270. if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
  271. {
  272. /* NAND interrupt callback*/
  273. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  274. hnand->ItCallback(hnand);
  275. #else
  276. HAL_NAND_ITCallback(hnand);
  277. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  278. /* Clear NAND interrupt Falling edge pending bit */
  279. #if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  280. __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
  281. #else
  282. __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
  283. #endif /* FMC_Bank2_3 || FSMC_Bank2_3 */
  284. }
  285. /* Check NAND interrupt FIFO empty flag */
  286. if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
  287. {
  288. /* NAND interrupt callback*/
  289. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  290. hnand->ItCallback(hnand);
  291. #else
  292. HAL_NAND_ITCallback(hnand);
  293. #endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
  294. /* Clear NAND interrupt FIFO empty pending bit */
  295. #if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
  296. __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
  297. #else
  298. __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
  299. #endif /* FMC_Bank2_3 || FSMC_Bank2_3 */
  300. }
  301. }
  302. /**
  303. * @brief NAND interrupt feature callback
  304. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  305. * the configuration information for NAND module.
  306. * @retval None
  307. */
  308. __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
  309. {
  310. /* Prevent unused argument(s) compilation warning */
  311. UNUSED(hnand);
  312. /* NOTE : This function Should not be modified, when the callback is needed,
  313. the HAL_NAND_ITCallback could be implemented in the user file
  314. */
  315. }
  316. /**
  317. * @}
  318. */
  319. /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
  320. * @brief Input Output and memory control functions
  321. *
  322. @verbatim
  323. ==============================================================================
  324. ##### NAND Input and Output functions #####
  325. ==============================================================================
  326. [..]
  327. This section provides functions allowing to use and control the NAND
  328. memory
  329. @endverbatim
  330. * @{
  331. */
  332. /**
  333. * @brief Read the NAND memory electronic signature
  334. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  335. * the configuration information for NAND module.
  336. * @param pNAND_ID NAND ID structure
  337. * @retval HAL status
  338. */
  339. HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
  340. {
  341. __IO uint32_t data = 0;
  342. __IO uint32_t data1 = 0;
  343. uint32_t deviceaddress;
  344. /* Check the NAND controller state */
  345. if (hnand->State == HAL_NAND_STATE_BUSY)
  346. {
  347. return HAL_BUSY;
  348. }
  349. else if (hnand->State == HAL_NAND_STATE_READY)
  350. {
  351. /* Process Locked */
  352. __HAL_LOCK(hnand);
  353. /* Update the NAND controller state */
  354. hnand->State = HAL_NAND_STATE_BUSY;
  355. /* Identify the device address */
  356. #if defined(FMC_Bank2_3)
  357. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  358. {
  359. deviceaddress = NAND_DEVICE1;
  360. }
  361. else
  362. {
  363. deviceaddress = NAND_DEVICE2;
  364. }
  365. #else
  366. deviceaddress = NAND_DEVICE;
  367. #endif
  368. /* Send Read ID command sequence */
  369. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
  370. __DSB();
  371. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
  372. __DSB();
  373. /* Read the electronic signature from NAND flash */
  374. #ifdef FSMC_PCR2_PWID
  375. if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
  376. #else /* FMC_PCR2_PWID is defined */
  377. if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
  378. #endif
  379. {
  380. data = *(__IO uint32_t *)deviceaddress;
  381. /* Return the data read */
  382. pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
  383. pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
  384. pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
  385. pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
  386. }
  387. else
  388. {
  389. data = *(__IO uint32_t *)deviceaddress;
  390. data1 = *((__IO uint32_t *)deviceaddress + 4);
  391. /* Return the data read */
  392. pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
  393. pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
  394. pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
  395. pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
  396. }
  397. /* Update the NAND controller state */
  398. hnand->State = HAL_NAND_STATE_READY;
  399. /* Process unlocked */
  400. __HAL_UNLOCK(hnand);
  401. }
  402. else
  403. {
  404. return HAL_ERROR;
  405. }
  406. return HAL_OK;
  407. }
  408. /**
  409. * @brief NAND memory reset
  410. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  411. * the configuration information for NAND module.
  412. * @retval HAL status
  413. */
  414. HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
  415. {
  416. uint32_t deviceaddress;
  417. /* Check the NAND controller state */
  418. if (hnand->State == HAL_NAND_STATE_BUSY)
  419. {
  420. return HAL_BUSY;
  421. }
  422. else if (hnand->State == HAL_NAND_STATE_READY)
  423. {
  424. /* Process Locked */
  425. __HAL_LOCK(hnand);
  426. /* Update the NAND controller state */
  427. hnand->State = HAL_NAND_STATE_BUSY;
  428. /* Identify the device address */
  429. #if defined(FMC_Bank2_3)
  430. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  431. {
  432. deviceaddress = NAND_DEVICE1;
  433. }
  434. else
  435. {
  436. deviceaddress = NAND_DEVICE2;
  437. }
  438. #else
  439. deviceaddress = NAND_DEVICE;
  440. #endif
  441. /* Send NAND reset command */
  442. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
  443. /* Update the NAND controller state */
  444. hnand->State = HAL_NAND_STATE_READY;
  445. /* Process unlocked */
  446. __HAL_UNLOCK(hnand);
  447. }
  448. else
  449. {
  450. return HAL_ERROR;
  451. }
  452. return HAL_OK;
  453. }
  454. /**
  455. * @brief Configure the device: Enter the physical parameters of the device
  456. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  457. * the configuration information for NAND module.
  458. * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
  459. * @retval HAL status
  460. */
  461. HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
  462. {
  463. hnand->Config.PageSize = pDeviceConfig->PageSize;
  464. hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
  465. hnand->Config.BlockSize = pDeviceConfig->BlockSize;
  466. hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
  467. hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
  468. hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
  469. hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
  470. return HAL_OK;
  471. }
  472. /**
  473. * @brief Read Page(s) from NAND memory block (8-bits addressing)
  474. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  475. * the configuration information for NAND module.
  476. * @param pAddress pointer to NAND address structure
  477. * @param pBuffer pointer to destination read buffer
  478. * @param NumPageToRead number of pages to read from block
  479. * @retval HAL status
  480. */
  481. HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
  482. uint32_t NumPageToRead)
  483. {
  484. uint32_t index;
  485. uint32_t tickstart;
  486. uint32_t deviceaddress;
  487. uint32_t numpagesread = 0U;
  488. uint32_t nandaddress;
  489. uint32_t nbpages = NumPageToRead;
  490. uint8_t *buff = pBuffer;
  491. /* Check the NAND controller state */
  492. if (hnand->State == HAL_NAND_STATE_BUSY)
  493. {
  494. return HAL_BUSY;
  495. }
  496. else if (hnand->State == HAL_NAND_STATE_READY)
  497. {
  498. /* Process Locked */
  499. __HAL_LOCK(hnand);
  500. /* Update the NAND controller state */
  501. hnand->State = HAL_NAND_STATE_BUSY;
  502. /* Identify the device address */
  503. #if defined(FMC_Bank2_3)
  504. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  505. {
  506. deviceaddress = NAND_DEVICE1;
  507. }
  508. else
  509. {
  510. deviceaddress = NAND_DEVICE2;
  511. }
  512. #else
  513. deviceaddress = NAND_DEVICE;
  514. #endif
  515. /* NAND raw address calculation */
  516. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  517. /* Page(s) read loop */
  518. while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  519. {
  520. /* Send read page command sequence */
  521. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  522. __DSB();
  523. /* Cards with page size <= 512 bytes */
  524. if ((hnand->Config.PageSize) <= 512U)
  525. {
  526. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  527. {
  528. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  529. __DSB();
  530. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  531. __DSB();
  532. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  533. __DSB();
  534. }
  535. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  536. {
  537. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  538. __DSB();
  539. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  540. __DSB();
  541. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  542. __DSB();
  543. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  544. __DSB();
  545. }
  546. }
  547. else /* (hnand->Config.PageSize) > 512 */
  548. {
  549. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  550. {
  551. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  552. __DSB();
  553. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  554. __DSB();
  555. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  556. __DSB();
  557. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  558. __DSB();
  559. }
  560. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  561. {
  562. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  563. __DSB();
  564. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  565. __DSB();
  566. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  567. __DSB();
  568. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  569. __DSB();
  570. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  571. __DSB();
  572. }
  573. }
  574. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  575. __DSB();
  576. if (hnand->Config.ExtraCommandEnable == ENABLE)
  577. {
  578. /* Get tick */
  579. tickstart = HAL_GetTick();
  580. /* Read status until NAND is ready */
  581. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  582. {
  583. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  584. {
  585. /* Update the NAND controller state */
  586. hnand->State = HAL_NAND_STATE_ERROR;
  587. /* Process unlocked */
  588. __HAL_UNLOCK(hnand);
  589. return HAL_TIMEOUT;
  590. }
  591. }
  592. /* Go back to read mode */
  593. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  594. __DSB();
  595. }
  596. /* Get Data into Buffer */
  597. for (index = 0U; index < hnand->Config.PageSize; index++)
  598. {
  599. *buff = *(uint8_t *)deviceaddress;
  600. buff++;
  601. }
  602. /* Increment read pages number */
  603. numpagesread++;
  604. /* Decrement pages to read */
  605. nbpages--;
  606. /* Increment the NAND address */
  607. nandaddress = (uint32_t)(nandaddress + 1U);
  608. }
  609. /* Update the NAND controller state */
  610. hnand->State = HAL_NAND_STATE_READY;
  611. /* Process unlocked */
  612. __HAL_UNLOCK(hnand);
  613. }
  614. else
  615. {
  616. return HAL_ERROR;
  617. }
  618. return HAL_OK;
  619. }
  620. /**
  621. * @brief Read Page(s) from NAND memory block (16-bits addressing)
  622. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  623. * the configuration information for NAND module.
  624. * @param pAddress pointer to NAND address structure
  625. * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
  626. * @param NumPageToRead number of pages to read from block
  627. * @retval HAL status
  628. */
  629. HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
  630. uint32_t NumPageToRead)
  631. {
  632. uint32_t index;
  633. uint32_t tickstart;
  634. uint32_t deviceaddress;
  635. uint32_t numpagesread = 0U;
  636. uint32_t nandaddress;
  637. uint32_t nbpages = NumPageToRead;
  638. uint16_t *buff = pBuffer;
  639. /* Check the NAND controller state */
  640. if (hnand->State == HAL_NAND_STATE_BUSY)
  641. {
  642. return HAL_BUSY;
  643. }
  644. else if (hnand->State == HAL_NAND_STATE_READY)
  645. {
  646. /* Process Locked */
  647. __HAL_LOCK(hnand);
  648. /* Update the NAND controller state */
  649. hnand->State = HAL_NAND_STATE_BUSY;
  650. /* Identify the device address */
  651. #if defined(FMC_Bank2_3)
  652. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  653. {
  654. deviceaddress = NAND_DEVICE1;
  655. }
  656. else
  657. {
  658. deviceaddress = NAND_DEVICE2;
  659. }
  660. #else
  661. deviceaddress = NAND_DEVICE;
  662. #endif
  663. /* NAND raw address calculation */
  664. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  665. /* Page(s) read loop */
  666. while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  667. {
  668. /* Send read page command sequence */
  669. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  670. __DSB();
  671. /* Cards with page size <= 512 bytes */
  672. if ((hnand->Config.PageSize) <= 512U)
  673. {
  674. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  675. {
  676. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  677. __DSB();
  678. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  679. __DSB();
  680. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  681. __DSB();
  682. }
  683. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  684. {
  685. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  686. __DSB();
  687. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  688. __DSB();
  689. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  690. __DSB();
  691. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  692. __DSB();
  693. }
  694. }
  695. else /* (hnand->Config.PageSize) > 512 */
  696. {
  697. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  698. {
  699. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  700. __DSB();
  701. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  702. __DSB();
  703. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  704. __DSB();
  705. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  706. __DSB();
  707. }
  708. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  709. {
  710. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  711. __DSB();
  712. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  713. __DSB();
  714. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  715. __DSB();
  716. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  717. __DSB();
  718. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  719. __DSB();
  720. }
  721. }
  722. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  723. __DSB();
  724. if (hnand->Config.ExtraCommandEnable == ENABLE)
  725. {
  726. /* Get tick */
  727. tickstart = HAL_GetTick();
  728. /* Read status until NAND is ready */
  729. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  730. {
  731. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  732. {
  733. /* Update the NAND controller state */
  734. hnand->State = HAL_NAND_STATE_ERROR;
  735. /* Process unlocked */
  736. __HAL_UNLOCK(hnand);
  737. return HAL_TIMEOUT;
  738. }
  739. }
  740. /* Go back to read mode */
  741. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  742. __DSB();
  743. }
  744. /* Calculate PageSize */
  745. #if defined(FSMC_PCR2_PWID)
  746. if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
  747. #else
  748. if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
  749. #endif /* FSMC_PCR2_PWID */
  750. {
  751. hnand->Config.PageSize = hnand->Config.PageSize / 2U;
  752. }
  753. else
  754. {
  755. /* Do nothing */
  756. /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
  757. }
  758. /* Get Data into Buffer */
  759. for (index = 0U; index < hnand->Config.PageSize; index++)
  760. {
  761. *buff = *(uint16_t *)deviceaddress;
  762. buff++;
  763. }
  764. /* Increment read pages number */
  765. numpagesread++;
  766. /* Decrement pages to read */
  767. nbpages--;
  768. /* Increment the NAND address */
  769. nandaddress = (uint32_t)(nandaddress + 1U);
  770. }
  771. /* Update the NAND controller state */
  772. hnand->State = HAL_NAND_STATE_READY;
  773. /* Process unlocked */
  774. __HAL_UNLOCK(hnand);
  775. }
  776. else
  777. {
  778. return HAL_ERROR;
  779. }
  780. return HAL_OK;
  781. }
  782. /**
  783. * @brief Write Page(s) to NAND memory block (8-bits addressing)
  784. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  785. * the configuration information for NAND module.
  786. * @param pAddress pointer to NAND address structure
  787. * @param pBuffer pointer to source buffer to write
  788. * @param NumPageToWrite number of pages to write to block
  789. * @retval HAL status
  790. */
  791. HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
  792. uint32_t NumPageToWrite)
  793. {
  794. uint32_t index;
  795. uint32_t tickstart;
  796. uint32_t deviceaddress;
  797. uint32_t numpageswritten = 0U;
  798. uint32_t nandaddress;
  799. uint32_t nbpages = NumPageToWrite;
  800. uint8_t *buff = pBuffer;
  801. /* Check the NAND controller state */
  802. if (hnand->State == HAL_NAND_STATE_BUSY)
  803. {
  804. return HAL_BUSY;
  805. }
  806. else if (hnand->State == HAL_NAND_STATE_READY)
  807. {
  808. /* Process Locked */
  809. __HAL_LOCK(hnand);
  810. /* Update the NAND controller state */
  811. hnand->State = HAL_NAND_STATE_BUSY;
  812. /* Identify the device address */
  813. #if defined(FMC_Bank2_3)
  814. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  815. {
  816. deviceaddress = NAND_DEVICE1;
  817. }
  818. else
  819. {
  820. deviceaddress = NAND_DEVICE2;
  821. }
  822. #else
  823. deviceaddress = NAND_DEVICE;
  824. #endif
  825. /* NAND raw address calculation */
  826. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  827. /* Page(s) write loop */
  828. while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  829. {
  830. /* Send write page command sequence */
  831. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  832. __DSB();
  833. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  834. __DSB();
  835. /* Cards with page size <= 512 bytes */
  836. if ((hnand->Config.PageSize) <= 512U)
  837. {
  838. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  839. {
  840. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  841. __DSB();
  842. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  843. __DSB();
  844. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  845. __DSB();
  846. }
  847. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  848. {
  849. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  850. __DSB();
  851. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  852. __DSB();
  853. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  854. __DSB();
  855. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  856. __DSB();
  857. }
  858. }
  859. else /* (hnand->Config.PageSize) > 512 */
  860. {
  861. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  862. {
  863. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  864. __DSB();
  865. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  866. __DSB();
  867. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  868. __DSB();
  869. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  870. __DSB();
  871. }
  872. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  873. {
  874. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  875. __DSB();
  876. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  877. __DSB();
  878. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  879. __DSB();
  880. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  881. __DSB();
  882. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  883. __DSB();
  884. }
  885. }
  886. /* Write data to memory */
  887. for (index = 0U; index < hnand->Config.PageSize; index++)
  888. {
  889. *(__IO uint8_t *)deviceaddress = *buff;
  890. buff++;
  891. __DSB();
  892. }
  893. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  894. __DSB();
  895. /* Get tick */
  896. tickstart = HAL_GetTick();
  897. /* Read status until NAND is ready */
  898. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  899. {
  900. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  901. {
  902. /* Update the NAND controller state */
  903. hnand->State = HAL_NAND_STATE_ERROR;
  904. /* Process unlocked */
  905. __HAL_UNLOCK(hnand);
  906. return HAL_TIMEOUT;
  907. }
  908. }
  909. /* Increment written pages number */
  910. numpageswritten++;
  911. /* Decrement pages to write */
  912. nbpages--;
  913. /* Increment the NAND address */
  914. nandaddress = (uint32_t)(nandaddress + 1U);
  915. }
  916. /* Update the NAND controller state */
  917. hnand->State = HAL_NAND_STATE_READY;
  918. /* Process unlocked */
  919. __HAL_UNLOCK(hnand);
  920. }
  921. else
  922. {
  923. return HAL_ERROR;
  924. }
  925. return HAL_OK;
  926. }
  927. /**
  928. * @brief Write Page(s) to NAND memory block (16-bits addressing)
  929. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  930. * the configuration information for NAND module.
  931. * @param pAddress pointer to NAND address structure
  932. * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
  933. * @param NumPageToWrite number of pages to write to block
  934. * @retval HAL status
  935. */
  936. HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
  937. uint32_t NumPageToWrite)
  938. {
  939. uint32_t index;
  940. uint32_t tickstart;
  941. uint32_t deviceaddress;
  942. uint32_t numpageswritten = 0U;
  943. uint32_t nandaddress;
  944. uint32_t nbpages = NumPageToWrite;
  945. uint16_t *buff = pBuffer;
  946. /* Check the NAND controller state */
  947. if (hnand->State == HAL_NAND_STATE_BUSY)
  948. {
  949. return HAL_BUSY;
  950. }
  951. else if (hnand->State == HAL_NAND_STATE_READY)
  952. {
  953. /* Process Locked */
  954. __HAL_LOCK(hnand);
  955. /* Update the NAND controller state */
  956. hnand->State = HAL_NAND_STATE_BUSY;
  957. /* Identify the device address */
  958. #if defined(FMC_Bank2_3)
  959. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  960. {
  961. deviceaddress = NAND_DEVICE1;
  962. }
  963. else
  964. {
  965. deviceaddress = NAND_DEVICE2;
  966. }
  967. #else
  968. deviceaddress = NAND_DEVICE;
  969. #endif
  970. /* NAND raw address calculation */
  971. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  972. /* Page(s) write loop */
  973. while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  974. {
  975. /* Send write page command sequence */
  976. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  977. __DSB();
  978. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  979. __DSB();
  980. /* Cards with page size <= 512 bytes */
  981. if ((hnand->Config.PageSize) <= 512U)
  982. {
  983. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  984. {
  985. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  986. __DSB();
  987. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  988. __DSB();
  989. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  990. __DSB();
  991. }
  992. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  993. {
  994. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  995. __DSB();
  996. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  997. __DSB();
  998. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  999. __DSB();
  1000. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1001. __DSB();
  1002. }
  1003. }
  1004. else /* (hnand->Config.PageSize) > 512 */
  1005. {
  1006. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1007. {
  1008. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1009. __DSB();
  1010. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1011. __DSB();
  1012. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1013. __DSB();
  1014. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1015. __DSB();
  1016. }
  1017. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1018. {
  1019. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1020. __DSB();
  1021. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1022. __DSB();
  1023. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1024. __DSB();
  1025. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1026. __DSB();
  1027. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1028. __DSB();
  1029. }
  1030. }
  1031. /* Calculate PageSize */
  1032. #if defined(FSMC_PCR2_PWID)
  1033. if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
  1034. #else
  1035. if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
  1036. #endif /* FSMC_PCR2_PWID */
  1037. {
  1038. hnand->Config.PageSize = hnand->Config.PageSize / 2U;
  1039. }
  1040. else
  1041. {
  1042. /* Do nothing */
  1043. /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
  1044. }
  1045. /* Write data to memory */
  1046. for (index = 0U; index < hnand->Config.PageSize; index++)
  1047. {
  1048. *(__IO uint16_t *)deviceaddress = *buff;
  1049. buff++;
  1050. __DSB();
  1051. }
  1052. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  1053. __DSB();
  1054. /* Get tick */
  1055. tickstart = HAL_GetTick();
  1056. /* Read status until NAND is ready */
  1057. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  1058. {
  1059. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  1060. {
  1061. /* Update the NAND controller state */
  1062. hnand->State = HAL_NAND_STATE_ERROR;
  1063. /* Process unlocked */
  1064. __HAL_UNLOCK(hnand);
  1065. return HAL_TIMEOUT;
  1066. }
  1067. }
  1068. /* Increment written pages number */
  1069. numpageswritten++;
  1070. /* Decrement pages to write */
  1071. nbpages--;
  1072. /* Increment the NAND address */
  1073. nandaddress = (uint32_t)(nandaddress + 1U);
  1074. }
  1075. /* Update the NAND controller state */
  1076. hnand->State = HAL_NAND_STATE_READY;
  1077. /* Process unlocked */
  1078. __HAL_UNLOCK(hnand);
  1079. }
  1080. else
  1081. {
  1082. return HAL_ERROR;
  1083. }
  1084. return HAL_OK;
  1085. }
  1086. /**
  1087. * @brief Read Spare area(s) from NAND memory (8-bits addressing)
  1088. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1089. * the configuration information for NAND module.
  1090. * @param pAddress pointer to NAND address structure
  1091. * @param pBuffer pointer to source buffer to write
  1092. * @param NumSpareAreaToRead Number of spare area to read
  1093. * @retval HAL status
  1094. */
  1095. HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
  1096. uint32_t NumSpareAreaToRead)
  1097. {
  1098. uint32_t index;
  1099. uint32_t tickstart;
  1100. uint32_t deviceaddress;
  1101. uint32_t numsparearearead = 0U;
  1102. uint32_t nandaddress;
  1103. uint32_t columnaddress;
  1104. uint32_t nbspare = NumSpareAreaToRead;
  1105. uint8_t *buff = pBuffer;
  1106. /* Check the NAND controller state */
  1107. if (hnand->State == HAL_NAND_STATE_BUSY)
  1108. {
  1109. return HAL_BUSY;
  1110. }
  1111. else if (hnand->State == HAL_NAND_STATE_READY)
  1112. {
  1113. /* Process Locked */
  1114. __HAL_LOCK(hnand);
  1115. /* Update the NAND controller state */
  1116. hnand->State = HAL_NAND_STATE_BUSY;
  1117. /* Identify the device address */
  1118. #if defined(FMC_Bank2_3)
  1119. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  1120. {
  1121. deviceaddress = NAND_DEVICE1;
  1122. }
  1123. else
  1124. {
  1125. deviceaddress = NAND_DEVICE2;
  1126. }
  1127. #else
  1128. deviceaddress = NAND_DEVICE;
  1129. #endif
  1130. /* NAND raw address calculation */
  1131. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1132. /* Column in page address */
  1133. columnaddress = COLUMN_ADDRESS(hnand);
  1134. /* Spare area(s) read loop */
  1135. while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1136. {
  1137. /* Cards with page size <= 512 bytes */
  1138. if ((hnand->Config.PageSize) <= 512U)
  1139. {
  1140. /* Send read spare area command sequence */
  1141. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1142. __DSB();
  1143. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1144. {
  1145. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1146. __DSB();
  1147. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1148. __DSB();
  1149. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1150. __DSB();
  1151. }
  1152. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1153. {
  1154. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1155. __DSB();
  1156. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1157. __DSB();
  1158. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1159. __DSB();
  1160. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1161. __DSB();
  1162. }
  1163. }
  1164. else /* (hnand->Config.PageSize) > 512 */
  1165. {
  1166. /* Send read spare area command sequence */
  1167. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1168. __DSB();
  1169. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1170. {
  1171. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1172. __DSB();
  1173. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1174. __DSB();
  1175. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1176. __DSB();
  1177. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1178. __DSB();
  1179. }
  1180. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1181. {
  1182. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1183. __DSB();
  1184. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1185. __DSB();
  1186. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1187. __DSB();
  1188. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1189. __DSB();
  1190. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1191. __DSB();
  1192. }
  1193. }
  1194. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  1195. __DSB();
  1196. if (hnand->Config.ExtraCommandEnable == ENABLE)
  1197. {
  1198. /* Get tick */
  1199. tickstart = HAL_GetTick();
  1200. /* Read status until NAND is ready */
  1201. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  1202. {
  1203. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  1204. {
  1205. /* Update the NAND controller state */
  1206. hnand->State = HAL_NAND_STATE_ERROR;
  1207. /* Process unlocked */
  1208. __HAL_UNLOCK(hnand);
  1209. return HAL_TIMEOUT;
  1210. }
  1211. }
  1212. /* Go back to read mode */
  1213. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  1214. __DSB();
  1215. }
  1216. /* Get Data into Buffer */
  1217. for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
  1218. {
  1219. *buff = *(uint8_t *)deviceaddress;
  1220. buff++;
  1221. }
  1222. /* Increment read spare areas number */
  1223. numsparearearead++;
  1224. /* Decrement spare areas to read */
  1225. nbspare--;
  1226. /* Increment the NAND address */
  1227. nandaddress = (uint32_t)(nandaddress + 1U);
  1228. }
  1229. /* Update the NAND controller state */
  1230. hnand->State = HAL_NAND_STATE_READY;
  1231. /* Process unlocked */
  1232. __HAL_UNLOCK(hnand);
  1233. }
  1234. else
  1235. {
  1236. return HAL_ERROR;
  1237. }
  1238. return HAL_OK;
  1239. }
  1240. /**
  1241. * @brief Read Spare area(s) from NAND memory (16-bits addressing)
  1242. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1243. * the configuration information for NAND module.
  1244. * @param pAddress pointer to NAND address structure
  1245. * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
  1246. * @param NumSpareAreaToRead Number of spare area to read
  1247. * @retval HAL status
  1248. */
  1249. HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
  1250. uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
  1251. {
  1252. uint32_t index;
  1253. uint32_t tickstart;
  1254. uint32_t deviceaddress;
  1255. uint32_t numsparearearead = 0U;
  1256. uint32_t nandaddress;
  1257. uint32_t columnaddress;
  1258. uint32_t nbspare = NumSpareAreaToRead;
  1259. uint16_t *buff = pBuffer;
  1260. /* Check the NAND controller state */
  1261. if (hnand->State == HAL_NAND_STATE_BUSY)
  1262. {
  1263. return HAL_BUSY;
  1264. }
  1265. else if (hnand->State == HAL_NAND_STATE_READY)
  1266. {
  1267. /* Process Locked */
  1268. __HAL_LOCK(hnand);
  1269. /* Update the NAND controller state */
  1270. hnand->State = HAL_NAND_STATE_BUSY;
  1271. /* Identify the device address */
  1272. #if defined(FMC_Bank2_3)
  1273. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  1274. {
  1275. deviceaddress = NAND_DEVICE1;
  1276. }
  1277. else
  1278. {
  1279. deviceaddress = NAND_DEVICE2;
  1280. }
  1281. #else
  1282. deviceaddress = NAND_DEVICE;
  1283. #endif
  1284. /* NAND raw address calculation */
  1285. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1286. /* Column in page address */
  1287. columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
  1288. /* Spare area(s) read loop */
  1289. while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1290. {
  1291. /* Cards with page size <= 512 bytes */
  1292. if ((hnand->Config.PageSize) <= 512U)
  1293. {
  1294. /* Send read spare area command sequence */
  1295. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1296. __DSB();
  1297. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1298. {
  1299. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1300. __DSB();
  1301. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1302. __DSB();
  1303. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1304. __DSB();
  1305. }
  1306. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1307. {
  1308. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1309. __DSB();
  1310. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1311. __DSB();
  1312. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1313. __DSB();
  1314. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1315. __DSB();
  1316. }
  1317. }
  1318. else /* (hnand->Config.PageSize) > 512 */
  1319. {
  1320. /* Send read spare area command sequence */
  1321. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1322. __DSB();
  1323. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1324. {
  1325. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1326. __DSB();
  1327. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1328. __DSB();
  1329. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1330. __DSB();
  1331. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1332. __DSB();
  1333. }
  1334. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1335. {
  1336. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1337. __DSB();
  1338. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1339. __DSB();
  1340. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1341. __DSB();
  1342. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1343. __DSB();
  1344. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1345. __DSB();
  1346. }
  1347. }
  1348. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
  1349. __DSB();
  1350. if (hnand->Config.ExtraCommandEnable == ENABLE)
  1351. {
  1352. /* Get tick */
  1353. tickstart = HAL_GetTick();
  1354. /* Read status until NAND is ready */
  1355. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  1356. {
  1357. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  1358. {
  1359. /* Update the NAND controller state */
  1360. hnand->State = HAL_NAND_STATE_ERROR;
  1361. /* Process unlocked */
  1362. __HAL_UNLOCK(hnand);
  1363. return HAL_TIMEOUT;
  1364. }
  1365. }
  1366. /* Go back to read mode */
  1367. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
  1368. __DSB();
  1369. }
  1370. /* Get Data into Buffer */
  1371. for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
  1372. {
  1373. *buff = *(uint16_t *)deviceaddress;
  1374. buff++;
  1375. }
  1376. /* Increment read spare areas number */
  1377. numsparearearead++;
  1378. /* Decrement spare areas to read */
  1379. nbspare--;
  1380. /* Increment the NAND address */
  1381. nandaddress = (uint32_t)(nandaddress + 1U);
  1382. }
  1383. /* Update the NAND controller state */
  1384. hnand->State = HAL_NAND_STATE_READY;
  1385. /* Process unlocked */
  1386. __HAL_UNLOCK(hnand);
  1387. }
  1388. else
  1389. {
  1390. return HAL_ERROR;
  1391. }
  1392. return HAL_OK;
  1393. }
  1394. /**
  1395. * @brief Write Spare area(s) to NAND memory (8-bits addressing)
  1396. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1397. * the configuration information for NAND module.
  1398. * @param pAddress pointer to NAND address structure
  1399. * @param pBuffer pointer to source buffer to write
  1400. * @param NumSpareAreaTowrite number of spare areas to write to block
  1401. * @retval HAL status
  1402. */
  1403. HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
  1404. uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
  1405. {
  1406. uint32_t index;
  1407. uint32_t tickstart;
  1408. uint32_t deviceaddress;
  1409. uint32_t numspareareawritten = 0U;
  1410. uint32_t nandaddress;
  1411. uint32_t columnaddress;
  1412. uint32_t nbspare = NumSpareAreaTowrite;
  1413. uint8_t *buff = pBuffer;
  1414. /* Check the NAND controller state */
  1415. if (hnand->State == HAL_NAND_STATE_BUSY)
  1416. {
  1417. return HAL_BUSY;
  1418. }
  1419. else if (hnand->State == HAL_NAND_STATE_READY)
  1420. {
  1421. /* Process Locked */
  1422. __HAL_LOCK(hnand);
  1423. /* Update the NAND controller state */
  1424. hnand->State = HAL_NAND_STATE_BUSY;
  1425. /* Identify the device address */
  1426. #if defined(FMC_Bank2_3)
  1427. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  1428. {
  1429. deviceaddress = NAND_DEVICE1;
  1430. }
  1431. else
  1432. {
  1433. deviceaddress = NAND_DEVICE2;
  1434. }
  1435. #else
  1436. deviceaddress = NAND_DEVICE;
  1437. #endif
  1438. /* Page address calculation */
  1439. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1440. /* Column in page address */
  1441. columnaddress = COLUMN_ADDRESS(hnand);
  1442. /* Spare area(s) write loop */
  1443. while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1444. {
  1445. /* Cards with page size <= 512 bytes */
  1446. if ((hnand->Config.PageSize) <= 512U)
  1447. {
  1448. /* Send write Spare area command sequence */
  1449. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1450. __DSB();
  1451. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1452. __DSB();
  1453. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1454. {
  1455. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1456. __DSB();
  1457. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1458. __DSB();
  1459. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1460. __DSB();
  1461. }
  1462. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1463. {
  1464. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1465. __DSB();
  1466. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1467. __DSB();
  1468. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1469. __DSB();
  1470. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1471. __DSB();
  1472. }
  1473. }
  1474. else /* (hnand->Config.PageSize) > 512 */
  1475. {
  1476. /* Send write Spare area command sequence */
  1477. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1478. __DSB();
  1479. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1480. __DSB();
  1481. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1482. {
  1483. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1484. __DSB();
  1485. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1486. __DSB();
  1487. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1488. __DSB();
  1489. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1490. __DSB();
  1491. }
  1492. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1493. {
  1494. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1495. __DSB();
  1496. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1497. __DSB();
  1498. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1499. __DSB();
  1500. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1501. __DSB();
  1502. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1503. __DSB();
  1504. }
  1505. }
  1506. /* Write data to memory */
  1507. for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
  1508. {
  1509. *(__IO uint8_t *)deviceaddress = *buff;
  1510. buff++;
  1511. __DSB();
  1512. }
  1513. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  1514. __DSB();
  1515. /* Get tick */
  1516. tickstart = HAL_GetTick();
  1517. /* Read status until NAND is ready */
  1518. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  1519. {
  1520. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  1521. {
  1522. /* Update the NAND controller state */
  1523. hnand->State = HAL_NAND_STATE_ERROR;
  1524. /* Process unlocked */
  1525. __HAL_UNLOCK(hnand);
  1526. return HAL_TIMEOUT;
  1527. }
  1528. }
  1529. /* Increment written spare areas number */
  1530. numspareareawritten++;
  1531. /* Decrement spare areas to write */
  1532. nbspare--;
  1533. /* Increment the NAND address */
  1534. nandaddress = (uint32_t)(nandaddress + 1U);
  1535. }
  1536. /* Update the NAND controller state */
  1537. hnand->State = HAL_NAND_STATE_READY;
  1538. /* Process unlocked */
  1539. __HAL_UNLOCK(hnand);
  1540. }
  1541. else
  1542. {
  1543. return HAL_ERROR;
  1544. }
  1545. return HAL_OK;
  1546. }
  1547. /**
  1548. * @brief Write Spare area(s) to NAND memory (16-bits addressing)
  1549. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1550. * the configuration information for NAND module.
  1551. * @param pAddress pointer to NAND address structure
  1552. * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
  1553. * @param NumSpareAreaTowrite number of spare areas to write to block
  1554. * @retval HAL status
  1555. */
  1556. HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
  1557. uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
  1558. {
  1559. uint32_t index;
  1560. uint32_t tickstart;
  1561. uint32_t deviceaddress;
  1562. uint32_t numspareareawritten = 0U;
  1563. uint32_t nandaddress;
  1564. uint32_t columnaddress;
  1565. uint32_t nbspare = NumSpareAreaTowrite;
  1566. uint16_t *buff = pBuffer;
  1567. /* Check the NAND controller state */
  1568. if (hnand->State == HAL_NAND_STATE_BUSY)
  1569. {
  1570. return HAL_BUSY;
  1571. }
  1572. else if (hnand->State == HAL_NAND_STATE_READY)
  1573. {
  1574. /* Process Locked */
  1575. __HAL_LOCK(hnand);
  1576. /* Update the NAND controller state */
  1577. hnand->State = HAL_NAND_STATE_BUSY;
  1578. /* Identify the device address */
  1579. #if defined(FMC_Bank2_3)
  1580. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  1581. {
  1582. deviceaddress = NAND_DEVICE1;
  1583. }
  1584. else
  1585. {
  1586. deviceaddress = NAND_DEVICE2;
  1587. }
  1588. #else
  1589. deviceaddress = NAND_DEVICE;
  1590. #endif
  1591. /* NAND raw address calculation */
  1592. nandaddress = ARRAY_ADDRESS(pAddress, hnand);
  1593. /* Column in page address */
  1594. columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
  1595. /* Spare area(s) write loop */
  1596. while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
  1597. {
  1598. /* Cards with page size <= 512 bytes */
  1599. if ((hnand->Config.PageSize) <= 512U)
  1600. {
  1601. /* Send write Spare area command sequence */
  1602. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
  1603. __DSB();
  1604. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1605. __DSB();
  1606. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1607. {
  1608. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1609. __DSB();
  1610. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1611. __DSB();
  1612. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1613. __DSB();
  1614. }
  1615. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1616. {
  1617. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
  1618. __DSB();
  1619. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1620. __DSB();
  1621. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1622. __DSB();
  1623. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1624. __DSB();
  1625. }
  1626. }
  1627. else /* (hnand->Config.PageSize) > 512 */
  1628. {
  1629. /* Send write Spare area command sequence */
  1630. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
  1631. __DSB();
  1632. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
  1633. __DSB();
  1634. if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
  1635. {
  1636. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1637. __DSB();
  1638. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1639. __DSB();
  1640. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1641. __DSB();
  1642. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1643. __DSB();
  1644. }
  1645. else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
  1646. {
  1647. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
  1648. __DSB();
  1649. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
  1650. __DSB();
  1651. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
  1652. __DSB();
  1653. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
  1654. __DSB();
  1655. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
  1656. __DSB();
  1657. }
  1658. }
  1659. /* Write data to memory */
  1660. for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
  1661. {
  1662. *(__IO uint16_t *)deviceaddress = *buff;
  1663. buff++;
  1664. __DSB();
  1665. }
  1666. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
  1667. __DSB();
  1668. /* Get tick */
  1669. tickstart = HAL_GetTick();
  1670. /* Read status until NAND is ready */
  1671. while (HAL_NAND_Read_Status(hnand) != NAND_READY)
  1672. {
  1673. if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
  1674. {
  1675. /* Update the NAND controller state */
  1676. hnand->State = HAL_NAND_STATE_ERROR;
  1677. /* Process unlocked */
  1678. __HAL_UNLOCK(hnand);
  1679. return HAL_TIMEOUT;
  1680. }
  1681. }
  1682. /* Increment written spare areas number */
  1683. numspareareawritten++;
  1684. /* Decrement spare areas to write */
  1685. nbspare--;
  1686. /* Increment the NAND address */
  1687. nandaddress = (uint32_t)(nandaddress + 1U);
  1688. }
  1689. /* Update the NAND controller state */
  1690. hnand->State = HAL_NAND_STATE_READY;
  1691. /* Process unlocked */
  1692. __HAL_UNLOCK(hnand);
  1693. }
  1694. else
  1695. {
  1696. return HAL_ERROR;
  1697. }
  1698. return HAL_OK;
  1699. }
  1700. /**
  1701. * @brief NAND memory Block erase
  1702. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1703. * the configuration information for NAND module.
  1704. * @param pAddress pointer to NAND address structure
  1705. * @retval HAL status
  1706. */
  1707. HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
  1708. {
  1709. uint32_t deviceaddress;
  1710. /* Check the NAND controller state */
  1711. if (hnand->State == HAL_NAND_STATE_BUSY)
  1712. {
  1713. return HAL_BUSY;
  1714. }
  1715. else if (hnand->State == HAL_NAND_STATE_READY)
  1716. {
  1717. /* Process Locked */
  1718. __HAL_LOCK(hnand);
  1719. /* Update the NAND controller state */
  1720. hnand->State = HAL_NAND_STATE_BUSY;
  1721. /* Identify the device address */
  1722. #if defined(FMC_Bank2_3)
  1723. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  1724. {
  1725. deviceaddress = NAND_DEVICE1;
  1726. }
  1727. else
  1728. {
  1729. deviceaddress = NAND_DEVICE2;
  1730. }
  1731. #else
  1732. deviceaddress = NAND_DEVICE;
  1733. #endif
  1734. /* Send Erase block command sequence */
  1735. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
  1736. __DSB();
  1737. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1738. __DSB();
  1739. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1740. __DSB();
  1741. *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
  1742. __DSB();
  1743. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
  1744. __DSB();
  1745. /* Update the NAND controller state */
  1746. hnand->State = HAL_NAND_STATE_READY;
  1747. /* Process unlocked */
  1748. __HAL_UNLOCK(hnand);
  1749. }
  1750. else
  1751. {
  1752. return HAL_ERROR;
  1753. }
  1754. return HAL_OK;
  1755. }
  1756. /**
  1757. * @brief Increment the NAND memory address
  1758. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1759. * the configuration information for NAND module.
  1760. * @param pAddress pointer to NAND address structure
  1761. * @retval The new status of the increment address operation. It can be:
  1762. * - NAND_VALID_ADDRESS: When the new address is valid address
  1763. * - NAND_INVALID_ADDRESS: When the new address is invalid address
  1764. */
  1765. uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
  1766. {
  1767. uint32_t status = NAND_VALID_ADDRESS;
  1768. /* Increment page address */
  1769. pAddress->Page++;
  1770. /* Check NAND address is valid */
  1771. if (pAddress->Page == hnand->Config.BlockSize)
  1772. {
  1773. pAddress->Page = 0;
  1774. pAddress->Block++;
  1775. if (pAddress->Block == hnand->Config.PlaneSize)
  1776. {
  1777. pAddress->Block = 0;
  1778. pAddress->Plane++;
  1779. if (pAddress->Plane == (hnand->Config.PlaneNbr))
  1780. {
  1781. status = NAND_INVALID_ADDRESS;
  1782. }
  1783. }
  1784. }
  1785. return (status);
  1786. }
  1787. #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
  1788. /**
  1789. * @brief Register a User NAND Callback
  1790. * To be used instead of the weak (surcharged) predefined callback
  1791. * @param hnand : NAND handle
  1792. * @param CallbackId : ID of the callback to be registered
  1793. * This parameter can be one of the following values:
  1794. * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
  1795. * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
  1796. * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
  1797. * @param pCallback : pointer to the Callback function
  1798. * @retval status
  1799. */
  1800. HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
  1801. pNAND_CallbackTypeDef pCallback)
  1802. {
  1803. HAL_StatusTypeDef status = HAL_OK;
  1804. if (pCallback == NULL)
  1805. {
  1806. return HAL_ERROR;
  1807. }
  1808. /* Process locked */
  1809. __HAL_LOCK(hnand);
  1810. if (hnand->State == HAL_NAND_STATE_READY)
  1811. {
  1812. switch (CallbackId)
  1813. {
  1814. case HAL_NAND_MSP_INIT_CB_ID :
  1815. hnand->MspInitCallback = pCallback;
  1816. break;
  1817. case HAL_NAND_MSP_DEINIT_CB_ID :
  1818. hnand->MspDeInitCallback = pCallback;
  1819. break;
  1820. case HAL_NAND_IT_CB_ID :
  1821. hnand->ItCallback = pCallback;
  1822. break;
  1823. default :
  1824. /* update return status */
  1825. status = HAL_ERROR;
  1826. break;
  1827. }
  1828. }
  1829. else if (hnand->State == HAL_NAND_STATE_RESET)
  1830. {
  1831. switch (CallbackId)
  1832. {
  1833. case HAL_NAND_MSP_INIT_CB_ID :
  1834. hnand->MspInitCallback = pCallback;
  1835. break;
  1836. case HAL_NAND_MSP_DEINIT_CB_ID :
  1837. hnand->MspDeInitCallback = pCallback;
  1838. break;
  1839. default :
  1840. /* update return status */
  1841. status = HAL_ERROR;
  1842. break;
  1843. }
  1844. }
  1845. else
  1846. {
  1847. /* update return status */
  1848. status = HAL_ERROR;
  1849. }
  1850. /* Release Lock */
  1851. __HAL_UNLOCK(hnand);
  1852. return status;
  1853. }
  1854. /**
  1855. * @brief Unregister a User NAND Callback
  1856. * NAND Callback is redirected to the weak (surcharged) predefined callback
  1857. * @param hnand : NAND handle
  1858. * @param CallbackId : ID of the callback to be unregistered
  1859. * This parameter can be one of the following values:
  1860. * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
  1861. * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
  1862. * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
  1863. * @retval status
  1864. */
  1865. HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
  1866. {
  1867. HAL_StatusTypeDef status = HAL_OK;
  1868. /* Process locked */
  1869. __HAL_LOCK(hnand);
  1870. if (hnand->State == HAL_NAND_STATE_READY)
  1871. {
  1872. switch (CallbackId)
  1873. {
  1874. case HAL_NAND_MSP_INIT_CB_ID :
  1875. hnand->MspInitCallback = HAL_NAND_MspInit;
  1876. break;
  1877. case HAL_NAND_MSP_DEINIT_CB_ID :
  1878. hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
  1879. break;
  1880. case HAL_NAND_IT_CB_ID :
  1881. hnand->ItCallback = HAL_NAND_ITCallback;
  1882. break;
  1883. default :
  1884. /* update return status */
  1885. status = HAL_ERROR;
  1886. break;
  1887. }
  1888. }
  1889. else if (hnand->State == HAL_NAND_STATE_RESET)
  1890. {
  1891. switch (CallbackId)
  1892. {
  1893. case HAL_NAND_MSP_INIT_CB_ID :
  1894. hnand->MspInitCallback = HAL_NAND_MspInit;
  1895. break;
  1896. case HAL_NAND_MSP_DEINIT_CB_ID :
  1897. hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
  1898. break;
  1899. default :
  1900. /* update return status */
  1901. status = HAL_ERROR;
  1902. break;
  1903. }
  1904. }
  1905. else
  1906. {
  1907. /* update return status */
  1908. status = HAL_ERROR;
  1909. }
  1910. /* Release Lock */
  1911. __HAL_UNLOCK(hnand);
  1912. return status;
  1913. }
  1914. #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
  1915. /**
  1916. * @}
  1917. */
  1918. /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
  1919. * @brief management functions
  1920. *
  1921. @verbatim
  1922. ==============================================================================
  1923. ##### NAND Control functions #####
  1924. ==============================================================================
  1925. [..]
  1926. This subsection provides a set of functions allowing to control dynamically
  1927. the NAND interface.
  1928. @endverbatim
  1929. * @{
  1930. */
  1931. /**
  1932. * @brief Enables dynamically NAND ECC feature.
  1933. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1934. * the configuration information for NAND module.
  1935. * @retval HAL status
  1936. */
  1937. HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
  1938. {
  1939. /* Check the NAND controller state */
  1940. if (hnand->State == HAL_NAND_STATE_BUSY)
  1941. {
  1942. return HAL_BUSY;
  1943. }
  1944. else if (hnand->State == HAL_NAND_STATE_READY)
  1945. {
  1946. /* Update the NAND state */
  1947. hnand->State = HAL_NAND_STATE_BUSY;
  1948. /* Enable ECC feature */
  1949. (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
  1950. /* Update the NAND state */
  1951. hnand->State = HAL_NAND_STATE_READY;
  1952. }
  1953. else
  1954. {
  1955. return HAL_ERROR;
  1956. }
  1957. return HAL_OK;
  1958. }
  1959. /**
  1960. * @brief Disables dynamically FMC_NAND ECC feature.
  1961. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1962. * the configuration information for NAND module.
  1963. * @retval HAL status
  1964. */
  1965. HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
  1966. {
  1967. /* Check the NAND controller state */
  1968. if (hnand->State == HAL_NAND_STATE_BUSY)
  1969. {
  1970. return HAL_BUSY;
  1971. }
  1972. else if (hnand->State == HAL_NAND_STATE_READY)
  1973. {
  1974. /* Update the NAND state */
  1975. hnand->State = HAL_NAND_STATE_BUSY;
  1976. /* Disable ECC feature */
  1977. (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
  1978. /* Update the NAND state */
  1979. hnand->State = HAL_NAND_STATE_READY;
  1980. }
  1981. else
  1982. {
  1983. return HAL_ERROR;
  1984. }
  1985. return HAL_OK;
  1986. }
  1987. /**
  1988. * @brief Disables dynamically NAND ECC feature.
  1989. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  1990. * the configuration information for NAND module.
  1991. * @param ECCval pointer to ECC value
  1992. * @param Timeout maximum timeout to wait
  1993. * @retval HAL status
  1994. */
  1995. HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
  1996. {
  1997. HAL_StatusTypeDef status;
  1998. /* Check the NAND controller state */
  1999. if (hnand->State == HAL_NAND_STATE_BUSY)
  2000. {
  2001. return HAL_BUSY;
  2002. }
  2003. else if (hnand->State == HAL_NAND_STATE_READY)
  2004. {
  2005. /* Update the NAND state */
  2006. hnand->State = HAL_NAND_STATE_BUSY;
  2007. /* Get NAND ECC value */
  2008. status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
  2009. /* Update the NAND state */
  2010. hnand->State = HAL_NAND_STATE_READY;
  2011. }
  2012. else
  2013. {
  2014. return HAL_ERROR;
  2015. }
  2016. return status;
  2017. }
  2018. /**
  2019. * @}
  2020. */
  2021. /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
  2022. * @brief Peripheral State functions
  2023. *
  2024. @verbatim
  2025. ==============================================================================
  2026. ##### NAND State functions #####
  2027. ==============================================================================
  2028. [..]
  2029. This subsection permits to get in run-time the status of the NAND controller
  2030. and the data flow.
  2031. @endverbatim
  2032. * @{
  2033. */
  2034. /**
  2035. * @brief return the NAND state
  2036. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  2037. * the configuration information for NAND module.
  2038. * @retval HAL state
  2039. */
  2040. HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
  2041. {
  2042. return hnand->State;
  2043. }
  2044. /**
  2045. * @brief NAND memory read status
  2046. * @param hnand pointer to a NAND_HandleTypeDef structure that contains
  2047. * the configuration information for NAND module.
  2048. * @retval NAND status
  2049. */
  2050. uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
  2051. {
  2052. uint32_t data;
  2053. uint32_t deviceaddress;
  2054. UNUSED(hnand);
  2055. /* Identify the device address */
  2056. #if defined(FMC_Bank2_3)
  2057. if (hnand->Init.NandBank == FMC_NAND_BANK2)
  2058. {
  2059. deviceaddress = NAND_DEVICE1;
  2060. }
  2061. else
  2062. {
  2063. deviceaddress = NAND_DEVICE2;
  2064. }
  2065. #else
  2066. deviceaddress = NAND_DEVICE;
  2067. #endif
  2068. /* Send Read status operation command */
  2069. *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
  2070. /* Read status register data */
  2071. data = *(__IO uint8_t *)deviceaddress;
  2072. /* Return the status */
  2073. if ((data & NAND_ERROR) == NAND_ERROR)
  2074. {
  2075. return NAND_ERROR;
  2076. }
  2077. else if ((data & NAND_READY) == NAND_READY)
  2078. {
  2079. return NAND_READY;
  2080. }
  2081. else
  2082. {
  2083. return NAND_BUSY;
  2084. }
  2085. }
  2086. /**
  2087. * @}
  2088. */
  2089. /**
  2090. * @}
  2091. */
  2092. /**
  2093. * @}
  2094. */
  2095. #endif /* HAL_NAND_MODULE_ENABLED */
  2096. /**
  2097. * @}
  2098. */
  2099. #endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */