训练营PLSR题目
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_i2s_ex.c
  4. * @author MCD Application Team
  5. * @brief I2S HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of I2S extension peripheral:
  8. * + Extension features Functions
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * Copyright (c) 2016 STMicroelectronics.
  13. * All rights reserved.
  14. *
  15. * This software is licensed under terms that can be found in the LICENSE file
  16. * in the root directory of this software component.
  17. * If no LICENSE file comes with this software, it is provided AS-IS.
  18. *
  19. ******************************************************************************
  20. @verbatim
  21. ==============================================================================
  22. ##### I2S Extension features #####
  23. ==============================================================================
  24. [..]
  25. (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
  26. data simultaneously using two data lines. Each SPI peripheral has an extended block
  27. called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
  28. (#) The extension block is not a full SPI IP, it is used only as I2S slave to
  29. implement full duplex mode. The extension block uses the same clock sources
  30. as its master.
  31. (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
  32. [..]
  33. (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
  34. I2Sx can be I2S2 or I2S3.
  35. ##### How to use this driver #####
  36. ===============================================================================
  37. [..]
  38. Three operation modes are available within this driver :
  39. *** Polling mode IO operation ***
  40. =================================
  41. [..]
  42. (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2SEx_TransmitReceive()
  43. *** Interrupt mode IO operation ***
  44. ===================================
  45. [..]
  46. (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2SEx_TransmitReceive_IT()
  47. (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
  48. add his own code by customization of function pointer HAL_I2SEx_TxRxCpltCallback
  49. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  50. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  51. *** DMA mode IO operation ***
  52. ==============================
  53. [..]
  54. (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2SEx_TransmitReceive_DMA()
  55. (+) At transmission/reception end of transfer HAL_I2SEx_TxRxCpltCallback is executed and user can
  56. add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback
  57. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  58. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  59. (+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the
  60. communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
  61. In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data
  62. inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer.
  63. @endverbatim
  64. Additional Figure: The Extended block uses the same clock sources as its master.
  65. +-----------------------+
  66. I2Sx_SCK | |
  67. ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
  68. +--|-->| |
  69. | | +-----------------------+
  70. | |
  71. I2S_WS | |
  72. ------>| |
  73. | | +-----------------------+
  74. | +-->| |
  75. | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
  76. +----->| |
  77. +-----------------------+
  78. */
  79. /* Includes ------------------------------------------------------------------*/
  80. #include "stm32f4xx_hal.h"
  81. /** @addtogroup STM32F4xx_HAL_Driver
  82. * @{
  83. */
  84. #ifdef HAL_I2S_MODULE_ENABLED
  85. /** @defgroup I2SEx I2SEx
  86. * @brief I2S Extended HAL module driver
  87. * @{
  88. */
  89. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  90. /* Private typedef -----------------------------------------------------------*/
  91. /** @defgroup I2SEx_Private_Typedef I2S Extended Private Typedef
  92. * @{
  93. */
  94. typedef enum
  95. {
  96. I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
  97. I2S_USE_I2SEXT = 0x01U, /*!< I2Sx_ext should be used */
  98. } I2S_UseTypeDef;
  99. /**
  100. * @}
  101. */
  102. /* Private define ------------------------------------------------------------*/
  103. /* Private macro -------------------------------------------------------------*/
  104. /* Private variables ---------------------------------------------------------*/
  105. /* Private function prototypes -----------------------------------------------*/
  106. /** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
  107. * @{
  108. */
  109. static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
  110. static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
  111. static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
  112. static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
  113. static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
  114. static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
  115. static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
  116. static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
  117. uint32_t Flag,
  118. uint32_t State,
  119. uint32_t Timeout,
  120. I2S_UseTypeDef i2sUsed);
  121. /**
  122. * @}
  123. */
  124. /**
  125. * @}
  126. */
  127. /* Private functions ---------------------------------------------------------*/
  128. /* Exported functions --------------------------------------------------------*/
  129. /** @addtogroup I2SEx I2SEx
  130. * @{
  131. */
  132. /** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
  133. * @{
  134. */
  135. /** @defgroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
  136. * @brief I2SEx IO operation functions
  137. *
  138. @verbatim
  139. ===============================================================================
  140. ##### IO operation functions#####
  141. ===============================================================================
  142. [..]
  143. This subsection provides a set of functions allowing to manage the I2S data
  144. transfers.
  145. (#) There are two modes of transfer:
  146. (++) Blocking mode : The communication is performed in the polling mode.
  147. The status of all data processing is returned by the same function
  148. after finishing transfer.
  149. (++) No-Blocking mode : The communication is performed using Interrupts
  150. or DMA. These functions return the status of the transfer startup.
  151. The end of the data processing will be indicated through the
  152. dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
  153. using DMA mode.
  154. (#) Blocking mode functions are :
  155. (++) HAL_I2SEx_TransmitReceive()
  156. (#) No-Blocking mode functions with Interrupt are :
  157. (++) HAL_I2SEx_TransmitReceive_IT()
  158. (++) HAL_I2SEx_FullDuplex_IRQHandler()
  159. (#) No-Blocking mode functions with DMA are :
  160. (++) HAL_I2SEx_TransmitReceive_DMA()
  161. (#) A set of Transfer Complete Callback are provided in non Blocking mode:
  162. (++) HAL_I2SEx_TxRxCpltCallback()
  163. @endverbatim
  164. * @{
  165. */
  166. /**
  167. * @brief Full-Duplex Transmit/Receive data in blocking mode.
  168. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  169. * the configuration information for I2S module
  170. * @param pTxData a 16-bit pointer to the Transmit data buffer.
  171. * @param pRxData a 16-bit pointer to the Receive data buffer.
  172. * @param Size number of data sample to be sent:
  173. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  174. * configuration phase, the Size parameter means the number of 16-bit data length
  175. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  176. * the Size parameter means the number of 16-bit data length.
  177. * @param Timeout Timeout duration
  178. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  179. * between Master and Slave(example: audio streaming).
  180. * @retval HAL status
  181. */
  182. HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
  183. uint16_t *pTxData,
  184. uint16_t *pRxData,
  185. uint16_t Size,
  186. uint32_t Timeout)
  187. {
  188. uint32_t tmp1 = 0U;
  189. HAL_StatusTypeDef errorcode = HAL_OK;
  190. if (hi2s->State != HAL_I2S_STATE_READY)
  191. {
  192. errorcode = HAL_BUSY;
  193. goto error;
  194. }
  195. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  196. {
  197. return HAL_ERROR;
  198. }
  199. /* Process Locked */
  200. __HAL_LOCK(hi2s);
  201. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  202. /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
  203. is selected during the I2S configuration phase, the Size parameter means the number
  204. of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
  205. frame is selected the Size parameter means the number of 16-bit data length. */
  206. if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  207. {
  208. hi2s->TxXferSize = (Size << 1U);
  209. hi2s->TxXferCount = (Size << 1U);
  210. hi2s->RxXferSize = (Size << 1U);
  211. hi2s->RxXferCount = (Size << 1U);
  212. }
  213. else
  214. {
  215. hi2s->TxXferSize = Size;
  216. hi2s->TxXferCount = Size;
  217. hi2s->RxXferSize = Size;
  218. hi2s->RxXferCount = Size;
  219. }
  220. /* Set state and reset error code */
  221. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  222. hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
  223. tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
  224. /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
  225. if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
  226. {
  227. /* Prepare the First Data before enabling the I2S */
  228. hi2s->Instance->DR = (*pTxData++);
  229. hi2s->TxXferCount--;
  230. /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
  231. __HAL_I2SEXT_ENABLE(hi2s);
  232. /* Enable I2Sx peripheral */
  233. __HAL_I2S_ENABLE(hi2s);
  234. /* Check if Master Receiver mode is selected */
  235. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX)
  236. {
  237. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  238. access to the SPI_SR register. */
  239. __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
  240. }
  241. while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
  242. {
  243. if (hi2s->TxXferCount > 0U)
  244. {
  245. /* Wait until TXE flag is set */
  246. if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
  247. {
  248. /* Set the error code */
  249. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  250. errorcode = HAL_ERROR;
  251. goto error;
  252. }
  253. /* Write Data on DR register */
  254. hi2s->Instance->DR = (*pTxData++);
  255. hi2s->TxXferCount--;
  256. /* Check if an underrun occurs */
  257. if ((__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_TX))
  258. {
  259. /* Clear Underrun flag */
  260. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  261. /* Set the error code */
  262. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  263. }
  264. }
  265. if (hi2s->RxXferCount > 0U)
  266. {
  267. /* Wait until RXNE flag is set */
  268. if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
  269. {
  270. /* Set the error code */
  271. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  272. errorcode = HAL_ERROR;
  273. goto error;
  274. }
  275. /* Read Data from DR register */
  276. (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
  277. hi2s->RxXferCount--;
  278. /* Check if an overrun occurs */
  279. if (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
  280. {
  281. /* Clear Overrun flag */
  282. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  283. /* Set the error code */
  284. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  285. }
  286. }
  287. }
  288. }
  289. /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
  290. else
  291. {
  292. /* Prepare the First Data before enabling the I2S */
  293. I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
  294. hi2s->TxXferCount--;
  295. /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
  296. __HAL_I2SEXT_ENABLE(hi2s);
  297. /* Enable I2S peripheral before the I2Sext*/
  298. __HAL_I2S_ENABLE(hi2s);
  299. /* Check if Master Receiver mode is selected */
  300. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  301. {
  302. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  303. access to the SPI_SR register. */
  304. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  305. }
  306. while ((hi2s->RxXferCount > 0U) || (hi2s->TxXferCount > 0U))
  307. {
  308. if (hi2s->TxXferCount > 0U)
  309. {
  310. /* Wait until TXE flag is set */
  311. if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
  312. {
  313. /* Set the error code */
  314. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  315. errorcode = HAL_ERROR;
  316. goto error;
  317. }
  318. /* Write Data on DR register */
  319. I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
  320. hi2s->TxXferCount--;
  321. /* Check if an underrun occurs */
  322. if ((__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) && (tmp1 == I2S_MODE_SLAVE_RX))
  323. {
  324. /* Clear Underrun flag */
  325. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  326. /* Set the error code */
  327. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  328. }
  329. }
  330. if (hi2s->RxXferCount > 0U)
  331. {
  332. /* Wait until RXNE flag is set */
  333. if (I2SEx_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
  334. {
  335. /* Set the error code */
  336. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  337. errorcode = HAL_ERROR;
  338. goto error;
  339. }
  340. /* Read Data from DR register */
  341. (*pRxData++) = hi2s->Instance->DR;
  342. hi2s->RxXferCount--;
  343. /* Check if an overrun occurs */
  344. if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
  345. {
  346. /* Clear Overrun flag */
  347. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  348. /* Set the error code */
  349. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  350. }
  351. }
  352. }
  353. }
  354. if (hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
  355. {
  356. errorcode = HAL_ERROR;
  357. }
  358. error :
  359. hi2s->State = HAL_I2S_STATE_READY;
  360. __HAL_UNLOCK(hi2s);
  361. return errorcode;
  362. }
  363. /**
  364. * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
  365. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  366. * the configuration information for I2S module
  367. * @param pTxData a 16-bit pointer to the Transmit data buffer.
  368. * @param pRxData a 16-bit pointer to the Receive data buffer.
  369. * @param Size number of data sample to be sent:
  370. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  371. * configuration phase, the Size parameter means the number of 16-bit data length
  372. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  373. * the Size parameter means the number of 16-bit data length.
  374. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  375. * between Master and Slave(example: audio streaming).
  376. * @retval HAL status
  377. */
  378. HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
  379. uint16_t *pTxData,
  380. uint16_t *pRxData,
  381. uint16_t Size)
  382. {
  383. uint32_t tmp1 = 0U;
  384. HAL_StatusTypeDef errorcode = HAL_OK;
  385. if (hi2s->State != HAL_I2S_STATE_READY)
  386. {
  387. errorcode = HAL_BUSY;
  388. goto error;
  389. }
  390. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  391. {
  392. return HAL_ERROR;
  393. }
  394. /* Process Locked */
  395. __HAL_LOCK(hi2s);
  396. hi2s->pTxBuffPtr = pTxData;
  397. hi2s->pRxBuffPtr = pRxData;
  398. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  399. /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
  400. is selected during the I2S configuration phase, the Size parameter means the number
  401. of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
  402. frame is selected the Size parameter means the number of 16-bit data length. */
  403. if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  404. {
  405. hi2s->TxXferSize = (Size << 1U);
  406. hi2s->TxXferCount = (Size << 1U);
  407. hi2s->RxXferSize = (Size << 1U);
  408. hi2s->RxXferCount = (Size << 1U);
  409. }
  410. else
  411. {
  412. hi2s->TxXferSize = Size;
  413. hi2s->TxXferCount = Size;
  414. hi2s->RxXferSize = Size;
  415. hi2s->RxXferCount = Size;
  416. }
  417. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  418. hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
  419. /* Set the function for IT treatment */
  420. if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
  421. {
  422. /* Enable I2Sext RXNE and ERR interrupts */
  423. __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  424. /* Enable I2Sx TXE and ERR interrupts */
  425. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  426. /* Transmit First data */
  427. hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
  428. hi2s->TxXferCount--;
  429. if (hi2s->TxXferCount == 0U)
  430. {
  431. /* Disable TXE and ERR interrupt */
  432. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  433. }
  434. }
  435. else /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
  436. {
  437. /* Enable I2Sext TXE and ERR interrupts */
  438. __HAL_I2SEXT_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  439. /* Enable I2Sext RXNE and ERR interrupts */
  440. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  441. /* Transmit First data */
  442. I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
  443. hi2s->TxXferCount--;
  444. if (hi2s->TxXferCount == 0U)
  445. {
  446. /* Disable I2Sext TXE and ERR interrupt */
  447. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  448. }
  449. }
  450. /* Enable I2Sext peripheral */
  451. __HAL_I2SEXT_ENABLE(hi2s);
  452. /* Enable I2S peripheral */
  453. __HAL_I2S_ENABLE(hi2s);
  454. error :
  455. __HAL_UNLOCK(hi2s);
  456. return errorcode;
  457. }
  458. /**
  459. * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
  460. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  461. * the configuration information for I2S module
  462. * @param pTxData a 16-bit pointer to the Transmit data buffer.
  463. * @param pRxData a 16-bit pointer to the Receive data buffer.
  464. * @param Size number of data sample to be sent:
  465. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  466. * configuration phase, the Size parameter means the number of 16-bit data length
  467. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  468. * the Size parameter means the number of 16-bit data length.
  469. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  470. * between Master and Slave(example: audio streaming).
  471. * @retval HAL status
  472. */
  473. HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
  474. uint16_t *pTxData,
  475. uint16_t *pRxData,
  476. uint16_t Size)
  477. {
  478. uint32_t *tmp = NULL;
  479. uint32_t tmp1 = 0U;
  480. HAL_StatusTypeDef errorcode = HAL_OK;
  481. if (hi2s->State != HAL_I2S_STATE_READY)
  482. {
  483. errorcode = HAL_BUSY;
  484. goto error;
  485. }
  486. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  487. {
  488. return HAL_ERROR;
  489. }
  490. /* Process Locked */
  491. __HAL_LOCK(hi2s);
  492. hi2s->pTxBuffPtr = pTxData;
  493. hi2s->pRxBuffPtr = pRxData;
  494. tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  495. /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
  496. is selected during the I2S configuration phase, the Size parameter means the number
  497. of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
  498. frame is selected the Size parameter means the number of 16-bit data length. */
  499. if ((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
  500. {
  501. hi2s->TxXferSize = (Size << 1U);
  502. hi2s->TxXferCount = (Size << 1U);
  503. hi2s->RxXferSize = (Size << 1U);
  504. hi2s->RxXferCount = (Size << 1U);
  505. }
  506. else
  507. {
  508. hi2s->TxXferSize = Size;
  509. hi2s->TxXferCount = Size;
  510. hi2s->RxXferSize = Size;
  511. hi2s->RxXferCount = Size;
  512. }
  513. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  514. hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
  515. /* Set the I2S Rx DMA Half transfer complete callback */
  516. hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
  517. /* Set the I2S Rx DMA transfer complete callback */
  518. hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
  519. /* Set the I2S Rx DMA error callback */
  520. hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
  521. /* Set the I2S Tx DMA Half transfer complete callback as NULL */
  522. hi2s->hdmatx->XferHalfCpltCallback = NULL;
  523. /* Set the I2S Tx DMA transfer complete callback as NULL */
  524. hi2s->hdmatx->XferCpltCallback = NULL;
  525. /* Set the I2S Tx DMA error callback */
  526. hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
  527. tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
  528. /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
  529. if ((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
  530. {
  531. /* Enable the Rx DMA Stream */
  532. tmp = (uint32_t *)&pRxData;
  533. HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
  534. /* Enable Rx DMA Request */
  535. SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
  536. /* Enable the Tx DMA Stream */
  537. tmp = (uint32_t *)&pTxData;
  538. HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
  539. /* Enable Tx DMA Request */
  540. SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  541. /* Check if the I2S is already enabled */
  542. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  543. {
  544. /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
  545. __HAL_I2SEXT_ENABLE(hi2s);
  546. /* Enable I2S peripheral after the I2Sext */
  547. __HAL_I2S_ENABLE(hi2s);
  548. }
  549. }
  550. else
  551. {
  552. /* Check if Master Receiver mode is selected */
  553. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  554. {
  555. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  556. access to the SPI_SR register. */
  557. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  558. }
  559. /* Enable the Tx DMA Stream */
  560. tmp = (uint32_t *)&pTxData;
  561. HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t *)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
  562. /* Enable Tx DMA Request */
  563. SET_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
  564. /* Enable the Rx DMA Stream */
  565. tmp = (uint32_t *)&pRxData;
  566. HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t *)tmp, hi2s->RxXferSize);
  567. /* Enable Rx DMA Request */
  568. SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  569. /* Check if the I2S is already enabled */
  570. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  571. {
  572. /* Enable I2Sext(transmitter) before enabling I2Sx peripheral */
  573. __HAL_I2SEXT_ENABLE(hi2s);
  574. /* Enable I2S peripheral before the I2Sext */
  575. __HAL_I2S_ENABLE(hi2s);
  576. }
  577. }
  578. error :
  579. __HAL_UNLOCK(hi2s);
  580. return errorcode;
  581. }
  582. /**
  583. * @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
  584. * @param hi2s I2S handle
  585. * @retval HAL status
  586. */
  587. void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
  588. {
  589. __IO uint32_t i2ssr = hi2s->Instance->SR;
  590. __IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
  591. __IO uint32_t i2scr2 = hi2s->Instance->CR2;
  592. __IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2;
  593. /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
  594. if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
  595. {
  596. /* I2S in mode Transmitter -------------------------------------------------*/
  597. if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET))
  598. {
  599. /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
  600. the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
  601. I2SEx_TxISR_I2S(hi2s);
  602. }
  603. /* I2Sext in mode Receiver -----------------------------------------------*/
  604. if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET))
  605. {
  606. /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
  607. the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
  608. I2SEx_RxISR_I2SExt(hi2s);
  609. }
  610. /* I2Sext Overrun error interrupt occurred --------------------------------*/
  611. if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
  612. {
  613. /* Disable RXNE and ERR interrupt */
  614. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  615. /* Disable TXE and ERR interrupt */
  616. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  617. /* Clear Overrun flag */
  618. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  619. /* Set the I2S State ready */
  620. hi2s->State = HAL_I2S_STATE_READY;
  621. /* Set the error code and execute error callback*/
  622. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  623. /* Call user error callback */
  624. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  625. hi2s->ErrorCallback(hi2s);
  626. #else
  627. HAL_I2S_ErrorCallback(hi2s);
  628. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  629. }
  630. /* I2S Underrun error interrupt occurred ----------------------------------*/
  631. if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
  632. {
  633. /* Disable TXE and ERR interrupt */
  634. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  635. /* Disable RXNE and ERR interrupt */
  636. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  637. /* Clear underrun flag */
  638. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  639. /* Set the I2S State ready */
  640. hi2s->State = HAL_I2S_STATE_READY;
  641. /* Set the error code and execute error callback*/
  642. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  643. /* Call user error callback */
  644. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  645. hi2s->ErrorCallback(hi2s);
  646. #else
  647. HAL_I2S_ErrorCallback(hi2s);
  648. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  649. }
  650. }
  651. /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
  652. else
  653. {
  654. /* I2Sext in mode Transmitter ----------------------------------------------*/
  655. if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET))
  656. {
  657. /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
  658. the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
  659. I2SEx_TxISR_I2SExt(hi2s);
  660. }
  661. /* I2S in mode Receiver --------------------------------------------------*/
  662. if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET))
  663. {
  664. /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
  665. the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
  666. I2SEx_RxISR_I2S(hi2s);
  667. }
  668. /* I2S Overrun error interrupt occurred -------------------------------------*/
  669. if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET))
  670. {
  671. /* Disable RXNE and ERR interrupt */
  672. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  673. /* Disable TXE and ERR interrupt */
  674. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  675. /* Set the I2S State ready */
  676. hi2s->State = HAL_I2S_STATE_READY;
  677. /* Set the error code and execute error callback*/
  678. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  679. /* Call user error callback */
  680. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  681. hi2s->ErrorCallback(hi2s);
  682. #else
  683. HAL_I2S_ErrorCallback(hi2s);
  684. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  685. }
  686. /* I2Sext Underrun error interrupt occurred -------------------------------*/
  687. if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
  688. {
  689. /* Disable TXE and ERR interrupt */
  690. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  691. /* Disable RXNE and ERR interrupt */
  692. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  693. /* Set the I2S State ready */
  694. hi2s->State = HAL_I2S_STATE_READY;
  695. /* Set the error code and execute error callback*/
  696. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  697. /* Call user error callback */
  698. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  699. hi2s->ErrorCallback(hi2s);
  700. #else
  701. HAL_I2S_ErrorCallback(hi2s);
  702. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  703. }
  704. }
  705. }
  706. /**
  707. * @brief Tx and Rx Transfer half completed callback
  708. * @param hi2s I2S handle
  709. * @retval None
  710. */
  711. __weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  712. {
  713. /* Prevent unused argument(s) compilation warning */
  714. UNUSED(hi2s);
  715. /* NOTE : This function Should not be modified, when the callback is needed,
  716. the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file
  717. */
  718. }
  719. /**
  720. * @brief Tx and Rx Transfer completed callback
  721. * @param hi2s I2S handle
  722. * @retval None
  723. */
  724. __weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
  725. {
  726. /* Prevent unused argument(s) compilation warning */
  727. UNUSED(hi2s);
  728. /* NOTE : This function should not be modified, when the callback is needed,
  729. the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
  730. */
  731. }
  732. /**
  733. * @}
  734. */
  735. /**
  736. * @}
  737. */
  738. /** @addtogroup I2SEx_Private_Functions I2S Extended Private Functions
  739. * @{
  740. */
  741. /**
  742. * @brief DMA I2S transmit receive process half complete callback
  743. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  744. * the configuration information for the specified DMA module.
  745. * @retval None
  746. */
  747. static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
  748. {
  749. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  750. /* Call user TxRx Half complete callback */
  751. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  752. hi2s->TxRxHalfCpltCallback(hi2s);
  753. #else
  754. HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
  755. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  756. }
  757. /**
  758. * @brief DMA I2S transmit receive process complete callback
  759. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  760. * the configuration information for the specified DMA module.
  761. * @retval None
  762. */
  763. static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
  764. {
  765. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  766. /* If DMA is configured in DMA_NORMAL mode */
  767. if (hdma->Init.Mode == DMA_NORMAL)
  768. {
  769. if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
  770. ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
  771. /* Disable Tx & Rx DMA Requests */
  772. {
  773. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
  774. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  775. }
  776. else
  777. {
  778. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  779. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
  780. }
  781. hi2s->RxXferCount = 0U;
  782. hi2s->TxXferCount = 0U;
  783. hi2s->State = HAL_I2S_STATE_READY;
  784. }
  785. /* Call user TxRx complete callback */
  786. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  787. hi2s->TxRxCpltCallback(hi2s);
  788. #else
  789. HAL_I2SEx_TxRxCpltCallback(hi2s);
  790. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  791. }
  792. /**
  793. * @brief DMA I2S communication error callback
  794. * @param hdma DMA handle
  795. * @retval None
  796. */
  797. static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
  798. {
  799. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
  800. /* Disable Rx and Tx DMA Request */
  801. CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  802. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  803. hi2s->TxXferCount = 0U;
  804. hi2s->RxXferCount = 0U;
  805. hi2s->State = HAL_I2S_STATE_READY;
  806. /* Set the error code and execute error callback*/
  807. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  808. /* Call user error callback */
  809. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  810. hi2s->ErrorCallback(hi2s);
  811. #else
  812. HAL_I2S_ErrorCallback(hi2s);
  813. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  814. }
  815. /**
  816. * @brief I2S Full-Duplex IT handler transmit function
  817. * @param hi2s I2S handle
  818. * @retval None
  819. */
  820. static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s)
  821. {
  822. /* Write Data on DR register */
  823. hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
  824. hi2s->TxXferCount--;
  825. if (hi2s->TxXferCount == 0U)
  826. {
  827. /* Disable TXE and ERR interrupt */
  828. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  829. if (hi2s->RxXferCount == 0U)
  830. {
  831. hi2s->State = HAL_I2S_STATE_READY;
  832. /* Call user TxRx complete callback */
  833. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  834. hi2s->TxRxCpltCallback(hi2s);
  835. #else
  836. HAL_I2SEx_TxRxCpltCallback(hi2s);
  837. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  838. }
  839. }
  840. }
  841. /**
  842. * @brief I2SExt Full-Duplex IT handler transmit function
  843. * @param hi2s I2S handle
  844. * @retval None
  845. */
  846. static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s)
  847. {
  848. /* Write Data on DR register */
  849. I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
  850. hi2s->TxXferCount--;
  851. if (hi2s->TxXferCount == 0U)
  852. {
  853. /* Disable I2Sext TXE and ERR interrupt */
  854. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  855. if (hi2s->RxXferCount == 0U)
  856. {
  857. hi2s->State = HAL_I2S_STATE_READY;
  858. /* Call user TxRx complete callback */
  859. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  860. hi2s->TxRxCpltCallback(hi2s);
  861. #else
  862. HAL_I2SEx_TxRxCpltCallback(hi2s);
  863. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  864. }
  865. }
  866. }
  867. /**
  868. * @brief I2S Full-Duplex IT handler receive function
  869. * @param hi2s I2S handle
  870. * @retval None
  871. */
  872. static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s)
  873. {
  874. /* Read Data from DR register */
  875. (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
  876. hi2s->RxXferCount--;
  877. if (hi2s->RxXferCount == 0U)
  878. {
  879. /* Disable RXNE and ERR interrupt */
  880. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  881. if (hi2s->TxXferCount == 0U)
  882. {
  883. hi2s->State = HAL_I2S_STATE_READY;
  884. /* Call user TxRx complete callback */
  885. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  886. hi2s->TxRxCpltCallback(hi2s);
  887. #else
  888. HAL_I2SEx_TxRxCpltCallback(hi2s);
  889. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  890. }
  891. }
  892. }
  893. /**
  894. * @brief I2SExt Full-Duplex IT handler receive function
  895. * @param hi2s I2S handle
  896. * @retval None
  897. */
  898. static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
  899. {
  900. /* Read Data from DR register */
  901. (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
  902. hi2s->RxXferCount--;
  903. if (hi2s->RxXferCount == 0U)
  904. {
  905. /* Disable I2Sext RXNE and ERR interrupt */
  906. __HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  907. if (hi2s->TxXferCount == 0U)
  908. {
  909. hi2s->State = HAL_I2S_STATE_READY;
  910. /* Call user TxRx complete callback */
  911. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  912. hi2s->TxRxCpltCallback(hi2s);
  913. #else
  914. HAL_I2SEx_TxRxCpltCallback(hi2s);
  915. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  916. }
  917. }
  918. }
  919. /**
  920. * @brief This function handles I2S Communication Timeout.
  921. * @param hi2s I2S handle
  922. * @param Flag Flag checked
  923. * @param State Value of the flag expected
  924. * @param Timeout Duration of the timeout
  925. * @param i2sUsed I2S instance reference
  926. * @retval HAL status
  927. */
  928. static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
  929. uint32_t Flag,
  930. uint32_t State,
  931. uint32_t Timeout,
  932. I2S_UseTypeDef i2sUsed)
  933. {
  934. uint32_t tickstart = HAL_GetTick();
  935. if (i2sUsed == I2S_USE_I2S)
  936. {
  937. /* Wait until flag is reset */
  938. while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
  939. {
  940. if (Timeout != HAL_MAX_DELAY)
  941. {
  942. if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  943. {
  944. /* Set the I2S State ready */
  945. hi2s->State = HAL_I2S_STATE_READY;
  946. /* Process Unlocked */
  947. __HAL_UNLOCK(hi2s);
  948. return HAL_TIMEOUT;
  949. }
  950. }
  951. }
  952. }
  953. else /* i2sUsed == I2S_USE_I2SEXT */
  954. {
  955. /* Wait until flag is reset */
  956. while (((__HAL_I2SEXT_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
  957. {
  958. if (Timeout != HAL_MAX_DELAY)
  959. {
  960. if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
  961. {
  962. /* Set the I2S State ready */
  963. hi2s->State = HAL_I2S_STATE_READY;
  964. /* Process Unlocked */
  965. __HAL_UNLOCK(hi2s);
  966. return HAL_TIMEOUT;
  967. }
  968. }
  969. }
  970. }
  971. return HAL_OK;
  972. }
  973. /**
  974. * @}
  975. */
  976. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  977. /**
  978. * @}
  979. */
  980. #endif /* HAL_I2S_MODULE_ENABLED */
  981. /**
  982. * @}
  983. */