训练营PLSR题目
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_i2s.c
  4. * @author MCD Application Team
  5. * @brief I2S HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Integrated Interchip Sound (I2S) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral State and Errors functions
  11. ******************************************************************************
  12. * @attention
  13. *
  14. * Copyright (c) 2016 STMicroelectronics.
  15. * All rights reserved.
  16. *
  17. * This software is licensed under terms that can be found in the LICENSE file
  18. * in the root directory of this software component.
  19. * If no LICENSE file comes with this software, it is provided AS-IS.
  20. *
  21. ******************************************************************************
  22. @verbatim
  23. ===============================================================================
  24. ##### How to use this driver #####
  25. ===============================================================================
  26. [..]
  27. The I2S HAL driver can be used as follow:
  28. (#) Declare a I2S_HandleTypeDef handle structure.
  29. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  30. (##) Enable the SPIx interface clock.
  31. (##) I2S pins configuration:
  32. (+++) Enable the clock for the I2S GPIOs.
  33. (+++) Configure these I2S pins as alternate function pull-up.
  34. (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  35. and HAL_I2S_Receive_IT() APIs).
  36. (+++) Configure the I2Sx interrupt priority.
  37. (+++) Enable the NVIC I2S IRQ handle.
  38. (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  39. and HAL_I2S_Receive_DMA() APIs:
  40. (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
  41. (+++) Enable the DMAx interface clock.
  42. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  43. (+++) Configure the DMA Tx/Rx Stream/Channel.
  44. (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
  45. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  46. DMA Tx/Rx Stream/Channel.
  47. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  48. using HAL_I2S_Init() function.
  49. -@- The specific I2S interrupts (Transmission complete interrupt,
  50. RXNE interrupt and Error Interrupts) will be managed using the macros
  51. __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
  52. -@- Make sure that either:
  53. (+@) I2S PLL clock is configured or
  54. (+@) External clock source is configured after setting correctly
  55. the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
  56. (#) Three mode of operations are available within this driver :
  57. *** Polling mode IO operation ***
  58. =================================
  59. [..]
  60. (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  61. (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  62. *** Interrupt mode IO operation ***
  63. ===================================
  64. [..]
  65. (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  66. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  67. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  68. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  69. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  70. (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  71. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  72. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  73. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  74. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  75. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  76. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  77. *** DMA mode IO operation ***
  78. ==============================
  79. [..]
  80. (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  81. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  82. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  83. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  84. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  85. (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  86. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  87. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  88. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  89. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  90. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  91. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  92. (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  93. (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  94. (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  95. In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
  96. HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
  97. In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
  98. inside DR register and avoid using DeInit/Init process for the next transfer.
  99. *** I2S HAL driver macros list ***
  100. ===================================
  101. [..]
  102. Below the list of most used macros in I2S HAL driver.
  103. (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  104. (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
  105. (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
  106. (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
  107. (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
  108. (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
  109. [..]
  110. (@) You can refer to the I2S HAL driver header file for more useful macros
  111. *** I2S HAL driver macros list ***
  112. ===================================
  113. [..]
  114. Callback registration:
  115. (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
  116. allows the user to configure dynamically the driver callbacks.
  117. Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
  118. Function HAL_I2S_RegisterCallback() allows to register following callbacks:
  119. (++) TxCpltCallback : I2S Tx Completed callback
  120. (++) RxCpltCallback : I2S Rx Completed callback
  121. (++) TxRxCpltCallback : I2S TxRx Completed callback
  122. (++) TxHalfCpltCallback : I2S Tx Half Completed callback
  123. (++) RxHalfCpltCallback : I2S Rx Half Completed callback
  124. (++) ErrorCallback : I2S Error callback
  125. (++) MspInitCallback : I2S Msp Init callback
  126. (++) MspDeInitCallback : I2S Msp DeInit callback
  127. This function takes as parameters the HAL peripheral handle, the Callback ID
  128. and a pointer to the user callback function.
  129. (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
  130. weak function.
  131. HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
  132. and the Callback ID.
  133. This function allows to reset following callbacks:
  134. (++) TxCpltCallback : I2S Tx Completed callback
  135. (++) RxCpltCallback : I2S Rx Completed callback
  136. (++) TxRxCpltCallback : I2S TxRx Completed callback
  137. (++) TxHalfCpltCallback : I2S Tx Half Completed callback
  138. (++) RxHalfCpltCallback : I2S Rx Half Completed callback
  139. (++) ErrorCallback : I2S Error callback
  140. (++) MspInitCallback : I2S Msp Init callback
  141. (++) MspDeInitCallback : I2S Msp DeInit callback
  142. [..]
  143. By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
  144. all callbacks are set to the corresponding weak functions:
  145. examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
  146. Exception done for MspInit and MspDeInit functions that are
  147. reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
  148. these callbacks are null (not registered beforehand).
  149. If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
  150. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
  151. [..]
  152. Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
  153. Exception done MspInit/MspDeInit functions that can be registered/unregistered
  154. in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
  155. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  156. Then, the user first registers the MspInit/MspDeInit user callbacks
  157. using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
  158. or HAL_I2S_Init() function.
  159. [..]
  160. When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
  161. not defined, the callback registering feature is not available
  162. and weak (surcharged) callbacks are used.
  163. @endverbatim
  164. */
  165. /* Includes ------------------------------------------------------------------*/
  166. #include "stm32f4xx_hal.h"
  167. #ifdef HAL_I2S_MODULE_ENABLED
  168. /** @addtogroup STM32F4xx_HAL_Driver
  169. * @{
  170. */
  171. /** @defgroup I2S I2S
  172. * @brief I2S HAL module driver
  173. * @{
  174. */
  175. /* Private typedef -----------------------------------------------------------*/
  176. /* Private define ------------------------------------------------------------*/
  177. #define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
  178. /* Private macro -------------------------------------------------------------*/
  179. /* Private variables ---------------------------------------------------------*/
  180. /* Private function prototypes -----------------------------------------------*/
  181. /** @defgroup I2S_Private_Functions I2S Private Functions
  182. * @{
  183. */
  184. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
  185. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
  186. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
  187. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
  188. static void I2S_DMAError(DMA_HandleTypeDef *hdma);
  189. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
  190. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
  191. static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
  192. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
  193. uint32_t Timeout);
  194. /**
  195. * @}
  196. */
  197. /* Exported functions ---------------------------------------------------------*/
  198. /** @defgroup I2S_Exported_Functions I2S Exported Functions
  199. * @{
  200. */
  201. /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
  202. * @brief Initialization and Configuration functions
  203. *
  204. @verbatim
  205. ===============================================================================
  206. ##### Initialization and de-initialization functions #####
  207. ===============================================================================
  208. [..] This subsection provides a set of functions allowing to initialize and
  209. de-initialize the I2Sx peripheral in simplex mode:
  210. (+) User must Implement HAL_I2S_MspInit() function in which he configures
  211. all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  212. (+) Call the function HAL_I2S_Init() to configure the selected device with
  213. the selected configuration:
  214. (++) Mode
  215. (++) Standard
  216. (++) Data Format
  217. (++) MCLK Output
  218. (++) Audio frequency
  219. (++) Polarity
  220. (++) Full duplex mode
  221. (+) Call the function HAL_I2S_DeInit() to restore the default configuration
  222. of the selected I2Sx peripheral.
  223. @endverbatim
  224. * @{
  225. */
  226. /**
  227. * @brief Initializes the I2S according to the specified parameters
  228. * in the I2S_InitTypeDef and create the associated handle.
  229. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  230. * the configuration information for I2S module
  231. * @retval HAL status
  232. */
  233. HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
  234. {
  235. uint32_t i2sdiv;
  236. uint32_t i2sodd;
  237. uint32_t packetlength;
  238. uint32_t tmp;
  239. uint32_t i2sclk;
  240. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  241. uint16_t tmpreg;
  242. #endif
  243. /* Check the I2S handle allocation */
  244. if (hi2s == NULL)
  245. {
  246. return HAL_ERROR;
  247. }
  248. /* Check the I2S parameters */
  249. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  250. assert_param(IS_I2S_MODE(hi2s->Init.Mode));
  251. assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
  252. assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
  253. assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
  254. assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
  255. assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
  256. assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
  257. if (hi2s->State == HAL_I2S_STATE_RESET)
  258. {
  259. /* Allocate lock resource and initialize it */
  260. hi2s->Lock = HAL_UNLOCKED;
  261. /* Initialize Default I2S IrqHandler ISR */
  262. hi2s->IrqHandlerISR = I2S_IRQHandler;
  263. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  264. /* Init the I2S Callback settings */
  265. hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
  266. hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
  267. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  268. hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
  269. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  270. hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
  271. hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
  272. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  273. hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
  274. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  275. hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
  276. if (hi2s->MspInitCallback == NULL)
  277. {
  278. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  279. }
  280. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  281. hi2s->MspInitCallback(hi2s);
  282. #else
  283. /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
  284. HAL_I2S_MspInit(hi2s);
  285. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  286. }
  287. hi2s->State = HAL_I2S_STATE_BUSY;
  288. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
  289. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  290. CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
  291. SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  292. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
  293. hi2s->Instance->I2SPR = 0x0002U;
  294. /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
  295. /* If the requested audio frequency is not the default, compute the prescaler */
  296. if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
  297. {
  298. /* Check the frame length (For the Prescaler computing) ********************/
  299. if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
  300. {
  301. /* Packet length is 16 bits */
  302. packetlength = 16U;
  303. }
  304. else
  305. {
  306. /* Packet length is 32 bits */
  307. packetlength = 32U;
  308. }
  309. /* I2S standard */
  310. if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
  311. {
  312. /* In I2S standard packet length is multiplied by 2 */
  313. packetlength = packetlength * 2U;
  314. }
  315. /* Get the source clock value **********************************************/
  316. #if defined(I2S_APB1_APB2_FEATURE)
  317. if (IS_I2S_APB1_INSTANCE(hi2s->Instance))
  318. {
  319. i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1);
  320. }
  321. else
  322. {
  323. i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2);
  324. }
  325. #else
  326. i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
  327. #endif /* I2S_APB1_APB2_FEATURE */
  328. /* Compute the Real divider depending on the MCLK output state, with a floating point */
  329. if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
  330. {
  331. /* MCLK output is enabled */
  332. if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
  333. {
  334. tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  335. }
  336. else
  337. {
  338. tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  339. }
  340. }
  341. else
  342. {
  343. /* MCLK output is disabled */
  344. tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  345. }
  346. /* Remove the flatting point */
  347. tmp = tmp / 10U;
  348. /* Check the parity of the divider */
  349. i2sodd = (uint32_t)(tmp & (uint32_t)1U);
  350. /* Compute the i2sdiv prescaler */
  351. i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
  352. /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
  353. i2sodd = (uint32_t)(i2sodd << 8U);
  354. }
  355. else
  356. {
  357. /* Set the default values */
  358. i2sdiv = 2U;
  359. i2sodd = 0U;
  360. }
  361. /* Test if the divider is 1 or 0 or greater than 0xFF */
  362. if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
  363. {
  364. /* Set the error code and execute error callback*/
  365. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
  366. return HAL_ERROR;
  367. }
  368. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
  369. /* Write to SPIx I2SPR register the computed value */
  370. hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
  371. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  372. /* And configure the I2S with the I2S_InitStruct values */
  373. MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
  374. SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
  375. SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  376. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
  377. (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
  378. hi2s->Init.Standard | hi2s->Init.DataFormat | \
  379. hi2s->Init.CPOL));
  380. #if defined(SPI_I2SCFGR_ASTRTEN)
  381. if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
  382. {
  383. /* Write to SPIx I2SCFGR */
  384. SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
  385. }
  386. #endif /* SPI_I2SCFGR_ASTRTEN */
  387. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  388. /* Configure the I2S extended if the full duplex mode is enabled */
  389. assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
  390. if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
  391. {
  392. /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
  393. hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
  394. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  395. CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
  396. SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  397. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
  398. I2SxEXT(hi2s->Instance)->I2SPR = 2U;
  399. /* Get the I2SCFGR register value */
  400. tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
  401. /* Get the mode to be configured for the extended I2S */
  402. if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
  403. {
  404. tmp = I2S_MODE_SLAVE_RX;
  405. }
  406. else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */
  407. {
  408. tmp = I2S_MODE_SLAVE_TX;
  409. }
  410. /* Configure the I2S Slave with the I2S Master parameter values */
  411. tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
  412. (uint16_t)tmp | \
  413. (uint16_t)hi2s->Init.Standard | \
  414. (uint16_t)hi2s->Init.DataFormat | \
  415. (uint16_t)hi2s->Init.CPOL);
  416. /* Write to SPIx I2SCFGR */
  417. WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
  418. }
  419. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  420. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  421. hi2s->State = HAL_I2S_STATE_READY;
  422. return HAL_OK;
  423. }
  424. /**
  425. * @brief DeInitializes the I2S peripheral
  426. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  427. * the configuration information for I2S module
  428. * @retval HAL status
  429. */
  430. HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
  431. {
  432. /* Check the I2S handle allocation */
  433. if (hi2s == NULL)
  434. {
  435. return HAL_ERROR;
  436. }
  437. /* Check the parameters */
  438. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  439. hi2s->State = HAL_I2S_STATE_BUSY;
  440. /* Disable the I2S Peripheral Clock */
  441. __HAL_I2S_DISABLE(hi2s);
  442. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  443. if (hi2s->MspDeInitCallback == NULL)
  444. {
  445. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  446. }
  447. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  448. hi2s->MspDeInitCallback(hi2s);
  449. #else
  450. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  451. HAL_I2S_MspDeInit(hi2s);
  452. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  453. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  454. hi2s->State = HAL_I2S_STATE_RESET;
  455. /* Release Lock */
  456. __HAL_UNLOCK(hi2s);
  457. return HAL_OK;
  458. }
  459. /**
  460. * @brief I2S MSP Init
  461. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  462. * the configuration information for I2S module
  463. * @retval None
  464. */
  465. __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
  466. {
  467. /* Prevent unused argument(s) compilation warning */
  468. UNUSED(hi2s);
  469. /* NOTE : This function Should not be modified, when the callback is needed,
  470. the HAL_I2S_MspInit could be implemented in the user file
  471. */
  472. }
  473. /**
  474. * @brief I2S MSP DeInit
  475. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  476. * the configuration information for I2S module
  477. * @retval None
  478. */
  479. __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
  480. {
  481. /* Prevent unused argument(s) compilation warning */
  482. UNUSED(hi2s);
  483. /* NOTE : This function Should not be modified, when the callback is needed,
  484. the HAL_I2S_MspDeInit could be implemented in the user file
  485. */
  486. }
  487. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  488. /**
  489. * @brief Register a User I2S Callback
  490. * To be used instead of the weak predefined callback
  491. * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
  492. * the configuration information for the specified I2S.
  493. * @param CallbackID ID of the callback to be registered
  494. * @param pCallback pointer to the Callback function
  495. * @retval HAL status
  496. */
  497. HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
  498. pI2S_CallbackTypeDef pCallback)
  499. {
  500. HAL_StatusTypeDef status = HAL_OK;
  501. if (pCallback == NULL)
  502. {
  503. /* Update the error code */
  504. hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
  505. return HAL_ERROR;
  506. }
  507. /* Process locked */
  508. __HAL_LOCK(hi2s);
  509. if (HAL_I2S_STATE_READY == hi2s->State)
  510. {
  511. switch (CallbackID)
  512. {
  513. case HAL_I2S_TX_COMPLETE_CB_ID :
  514. hi2s->TxCpltCallback = pCallback;
  515. break;
  516. case HAL_I2S_RX_COMPLETE_CB_ID :
  517. hi2s->RxCpltCallback = pCallback;
  518. break;
  519. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  520. case HAL_I2S_TX_RX_COMPLETE_CB_ID :
  521. hi2s->TxRxCpltCallback = pCallback;
  522. break;
  523. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  524. case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
  525. hi2s->TxHalfCpltCallback = pCallback;
  526. break;
  527. case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
  528. hi2s->RxHalfCpltCallback = pCallback;
  529. break;
  530. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  531. case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
  532. hi2s->TxRxHalfCpltCallback = pCallback;
  533. break;
  534. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  535. case HAL_I2S_ERROR_CB_ID :
  536. hi2s->ErrorCallback = pCallback;
  537. break;
  538. case HAL_I2S_MSPINIT_CB_ID :
  539. hi2s->MspInitCallback = pCallback;
  540. break;
  541. case HAL_I2S_MSPDEINIT_CB_ID :
  542. hi2s->MspDeInitCallback = pCallback;
  543. break;
  544. default :
  545. /* Update the error code */
  546. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  547. /* Return error status */
  548. status = HAL_ERROR;
  549. break;
  550. }
  551. }
  552. else if (HAL_I2S_STATE_RESET == hi2s->State)
  553. {
  554. switch (CallbackID)
  555. {
  556. case HAL_I2S_MSPINIT_CB_ID :
  557. hi2s->MspInitCallback = pCallback;
  558. break;
  559. case HAL_I2S_MSPDEINIT_CB_ID :
  560. hi2s->MspDeInitCallback = pCallback;
  561. break;
  562. default :
  563. /* Update the error code */
  564. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  565. /* Return error status */
  566. status = HAL_ERROR;
  567. break;
  568. }
  569. }
  570. else
  571. {
  572. /* Update the error code */
  573. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  574. /* Return error status */
  575. status = HAL_ERROR;
  576. }
  577. /* Release Lock */
  578. __HAL_UNLOCK(hi2s);
  579. return status;
  580. }
  581. /**
  582. * @brief Unregister an I2S Callback
  583. * I2S callback is redirected to the weak predefined callback
  584. * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
  585. * the configuration information for the specified I2S.
  586. * @param CallbackID ID of the callback to be unregistered
  587. * @retval HAL status
  588. */
  589. HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
  590. {
  591. HAL_StatusTypeDef status = HAL_OK;
  592. /* Process locked */
  593. __HAL_LOCK(hi2s);
  594. if (HAL_I2S_STATE_READY == hi2s->State)
  595. {
  596. switch (CallbackID)
  597. {
  598. case HAL_I2S_TX_COMPLETE_CB_ID :
  599. hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
  600. break;
  601. case HAL_I2S_RX_COMPLETE_CB_ID :
  602. hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
  603. break;
  604. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  605. case HAL_I2S_TX_RX_COMPLETE_CB_ID :
  606. hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
  607. break;
  608. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  609. case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
  610. hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
  611. break;
  612. case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
  613. hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
  614. break;
  615. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  616. case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
  617. hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
  618. break;
  619. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  620. case HAL_I2S_ERROR_CB_ID :
  621. hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
  622. break;
  623. case HAL_I2S_MSPINIT_CB_ID :
  624. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  625. break;
  626. case HAL_I2S_MSPDEINIT_CB_ID :
  627. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  628. break;
  629. default :
  630. /* Update the error code */
  631. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  632. /* Return error status */
  633. status = HAL_ERROR;
  634. break;
  635. }
  636. }
  637. else if (HAL_I2S_STATE_RESET == hi2s->State)
  638. {
  639. switch (CallbackID)
  640. {
  641. case HAL_I2S_MSPINIT_CB_ID :
  642. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  643. break;
  644. case HAL_I2S_MSPDEINIT_CB_ID :
  645. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  646. break;
  647. default :
  648. /* Update the error code */
  649. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  650. /* Return error status */
  651. status = HAL_ERROR;
  652. break;
  653. }
  654. }
  655. else
  656. {
  657. /* Update the error code */
  658. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  659. /* Return error status */
  660. status = HAL_ERROR;
  661. }
  662. /* Release Lock */
  663. __HAL_UNLOCK(hi2s);
  664. return status;
  665. }
  666. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  667. /**
  668. * @}
  669. */
  670. /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
  671. * @brief Data transfers functions
  672. *
  673. @verbatim
  674. ===============================================================================
  675. ##### IO operation functions #####
  676. ===============================================================================
  677. [..]
  678. This subsection provides a set of functions allowing to manage the I2S data
  679. transfers.
  680. (#) There are two modes of transfer:
  681. (++) Blocking mode : The communication is performed in the polling mode.
  682. The status of all data processing is returned by the same function
  683. after finishing transfer.
  684. (++) No-Blocking mode : The communication is performed using Interrupts
  685. or DMA. These functions return the status of the transfer startup.
  686. The end of the data processing will be indicated through the
  687. dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
  688. using DMA mode.
  689. (#) Blocking mode functions are :
  690. (++) HAL_I2S_Transmit()
  691. (++) HAL_I2S_Receive()
  692. (#) No-Blocking mode functions with Interrupt are :
  693. (++) HAL_I2S_Transmit_IT()
  694. (++) HAL_I2S_Receive_IT()
  695. (#) No-Blocking mode functions with DMA are :
  696. (++) HAL_I2S_Transmit_DMA()
  697. (++) HAL_I2S_Receive_DMA()
  698. (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
  699. (++) HAL_I2S_TxCpltCallback()
  700. (++) HAL_I2S_RxCpltCallback()
  701. (++) HAL_I2S_ErrorCallback()
  702. @endverbatim
  703. * @{
  704. */
  705. /**
  706. * @brief Transmit an amount of data in blocking mode
  707. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  708. * the configuration information for I2S module
  709. * @param pData a 16-bit pointer to data buffer.
  710. * @param Size number of data sample to be sent:
  711. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  712. * configuration phase, the Size parameter means the number of 16-bit data length
  713. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  714. * the Size parameter means the number of 24-bit or 32-bit data length.
  715. * @param Timeout Timeout duration
  716. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  717. * between Master and Slave(example: audio streaming).
  718. * @retval HAL status
  719. */
  720. HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  721. {
  722. uint32_t tmpreg_cfgr;
  723. if ((pData == NULL) || (Size == 0U))
  724. {
  725. return HAL_ERROR;
  726. }
  727. /* Process Locked */
  728. __HAL_LOCK(hi2s);
  729. if (hi2s->State != HAL_I2S_STATE_READY)
  730. {
  731. __HAL_UNLOCK(hi2s);
  732. return HAL_BUSY;
  733. }
  734. /* Set state and reset error code */
  735. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  736. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  737. hi2s->pTxBuffPtr = pData;
  738. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  739. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  740. {
  741. hi2s->TxXferSize = (Size << 1U);
  742. hi2s->TxXferCount = (Size << 1U);
  743. }
  744. else
  745. {
  746. hi2s->TxXferSize = Size;
  747. hi2s->TxXferCount = Size;
  748. }
  749. tmpreg_cfgr = hi2s->Instance->I2SCFGR;
  750. /* Check if the I2S is already enabled */
  751. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  752. {
  753. /* Enable I2S peripheral */
  754. __HAL_I2S_ENABLE(hi2s);
  755. }
  756. /* Wait until TXE flag is set */
  757. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
  758. {
  759. /* Set the error code */
  760. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  761. hi2s->State = HAL_I2S_STATE_READY;
  762. __HAL_UNLOCK(hi2s);
  763. return HAL_ERROR;
  764. }
  765. while (hi2s->TxXferCount > 0U)
  766. {
  767. hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
  768. hi2s->pTxBuffPtr++;
  769. hi2s->TxXferCount--;
  770. /* Wait until TXE flag is set */
  771. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
  772. {
  773. /* Set the error code */
  774. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  775. hi2s->State = HAL_I2S_STATE_READY;
  776. __HAL_UNLOCK(hi2s);
  777. return HAL_ERROR;
  778. }
  779. /* Check if an underrun occurs */
  780. if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
  781. {
  782. /* Clear underrun flag */
  783. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  784. /* Set the error code */
  785. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  786. }
  787. }
  788. /* Check if Slave mode is selected */
  789. if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
  790. || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
  791. {
  792. /* Wait until Busy flag is reset */
  793. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
  794. {
  795. /* Set the error code */
  796. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  797. hi2s->State = HAL_I2S_STATE_READY;
  798. __HAL_UNLOCK(hi2s);
  799. return HAL_ERROR;
  800. }
  801. }
  802. hi2s->State = HAL_I2S_STATE_READY;
  803. __HAL_UNLOCK(hi2s);
  804. return HAL_OK;
  805. }
  806. /**
  807. * @brief Receive an amount of data in blocking mode
  808. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  809. * the configuration information for I2S module
  810. * @param pData a 16-bit pointer to data buffer.
  811. * @param Size number of data sample to be sent:
  812. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  813. * configuration phase, the Size parameter means the number of 16-bit data length
  814. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  815. * the Size parameter means the number of 24-bit or 32-bit data length.
  816. * @param Timeout Timeout duration
  817. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  818. * between Master and Slave(example: audio streaming).
  819. * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
  820. * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
  821. * @retval HAL status
  822. */
  823. HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  824. {
  825. uint32_t tmpreg_cfgr;
  826. if ((pData == NULL) || (Size == 0U))
  827. {
  828. return HAL_ERROR;
  829. }
  830. /* Process Locked */
  831. __HAL_LOCK(hi2s);
  832. if (hi2s->State != HAL_I2S_STATE_READY)
  833. {
  834. __HAL_UNLOCK(hi2s);
  835. return HAL_BUSY;
  836. }
  837. /* Set state and reset error code */
  838. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  839. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  840. hi2s->pRxBuffPtr = pData;
  841. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  842. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  843. {
  844. hi2s->RxXferSize = (Size << 1U);
  845. hi2s->RxXferCount = (Size << 1U);
  846. }
  847. else
  848. {
  849. hi2s->RxXferSize = Size;
  850. hi2s->RxXferCount = Size;
  851. }
  852. /* Check if the I2S is already enabled */
  853. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  854. {
  855. /* Enable I2S peripheral */
  856. __HAL_I2S_ENABLE(hi2s);
  857. }
  858. /* Check if Master Receiver mode is selected */
  859. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  860. {
  861. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  862. access to the SPI_SR register. */
  863. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  864. }
  865. /* Receive data */
  866. while (hi2s->RxXferCount > 0U)
  867. {
  868. /* Wait until RXNE flag is set */
  869. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
  870. {
  871. /* Set the error code */
  872. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  873. hi2s->State = HAL_I2S_STATE_READY;
  874. __HAL_UNLOCK(hi2s);
  875. return HAL_ERROR;
  876. }
  877. (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
  878. hi2s->pRxBuffPtr++;
  879. hi2s->RxXferCount--;
  880. /* Check if an overrun occurs */
  881. if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
  882. {
  883. /* Clear overrun flag */
  884. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  885. /* Set the error code */
  886. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  887. }
  888. }
  889. hi2s->State = HAL_I2S_STATE_READY;
  890. __HAL_UNLOCK(hi2s);
  891. return HAL_OK;
  892. }
  893. /**
  894. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  895. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  896. * the configuration information for I2S module
  897. * @param pData a 16-bit pointer to data buffer.
  898. * @param Size number of data sample to be sent:
  899. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  900. * configuration phase, the Size parameter means the number of 16-bit data length
  901. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  902. * the Size parameter means the number of 24-bit or 32-bit data length.
  903. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  904. * between Master and Slave(example: audio streaming).
  905. * @retval HAL status
  906. */
  907. HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  908. {
  909. uint32_t tmpreg_cfgr;
  910. if ((pData == NULL) || (Size == 0U))
  911. {
  912. return HAL_ERROR;
  913. }
  914. /* Process Locked */
  915. __HAL_LOCK(hi2s);
  916. if (hi2s->State != HAL_I2S_STATE_READY)
  917. {
  918. __HAL_UNLOCK(hi2s);
  919. return HAL_BUSY;
  920. }
  921. /* Set state and reset error code */
  922. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  923. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  924. hi2s->pTxBuffPtr = pData;
  925. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  926. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  927. {
  928. hi2s->TxXferSize = (Size << 1U);
  929. hi2s->TxXferCount = (Size << 1U);
  930. }
  931. else
  932. {
  933. hi2s->TxXferSize = Size;
  934. hi2s->TxXferCount = Size;
  935. }
  936. /* Enable TXE and ERR interrupt */
  937. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  938. /* Check if the I2S is already enabled */
  939. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  940. {
  941. /* Enable I2S peripheral */
  942. __HAL_I2S_ENABLE(hi2s);
  943. }
  944. __HAL_UNLOCK(hi2s);
  945. return HAL_OK;
  946. }
  947. /**
  948. * @brief Receive an amount of data in non-blocking mode with Interrupt
  949. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  950. * the configuration information for I2S module
  951. * @param pData a 16-bit pointer to the Receive data buffer.
  952. * @param Size number of data sample to be sent:
  953. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  954. * configuration phase, the Size parameter means the number of 16-bit data length
  955. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  956. * the Size parameter means the number of 24-bit or 32-bit data length.
  957. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  958. * between Master and Slave(example: audio streaming).
  959. * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
  960. * between Master and Slave otherwise the I2S interrupt should be optimized.
  961. * @retval HAL status
  962. */
  963. HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  964. {
  965. uint32_t tmpreg_cfgr;
  966. if ((pData == NULL) || (Size == 0U))
  967. {
  968. return HAL_ERROR;
  969. }
  970. /* Process Locked */
  971. __HAL_LOCK(hi2s);
  972. if (hi2s->State != HAL_I2S_STATE_READY)
  973. {
  974. __HAL_UNLOCK(hi2s);
  975. return HAL_BUSY;
  976. }
  977. /* Set state and reset error code */
  978. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  979. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  980. hi2s->pRxBuffPtr = pData;
  981. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  982. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  983. {
  984. hi2s->RxXferSize = (Size << 1U);
  985. hi2s->RxXferCount = (Size << 1U);
  986. }
  987. else
  988. {
  989. hi2s->RxXferSize = Size;
  990. hi2s->RxXferCount = Size;
  991. }
  992. /* Enable RXNE and ERR interrupt */
  993. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  994. /* Check if the I2S is already enabled */
  995. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  996. {
  997. /* Enable I2S peripheral */
  998. __HAL_I2S_ENABLE(hi2s);
  999. }
  1000. __HAL_UNLOCK(hi2s);
  1001. return HAL_OK;
  1002. }
  1003. /**
  1004. * @brief Transmit an amount of data in non-blocking mode with DMA
  1005. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1006. * the configuration information for I2S module
  1007. * @param pData a 16-bit pointer to the Transmit data buffer.
  1008. * @param Size number of data sample to be sent:
  1009. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  1010. * configuration phase, the Size parameter means the number of 16-bit data length
  1011. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  1012. * the Size parameter means the number of 24-bit or 32-bit data length.
  1013. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  1014. * between Master and Slave(example: audio streaming).
  1015. * @retval HAL status
  1016. */
  1017. HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  1018. {
  1019. uint32_t tmpreg_cfgr;
  1020. if ((pData == NULL) || (Size == 0U))
  1021. {
  1022. return HAL_ERROR;
  1023. }
  1024. /* Process Locked */
  1025. __HAL_LOCK(hi2s);
  1026. if (hi2s->State != HAL_I2S_STATE_READY)
  1027. {
  1028. __HAL_UNLOCK(hi2s);
  1029. return HAL_BUSY;
  1030. }
  1031. /* Set state and reset error code */
  1032. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  1033. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  1034. hi2s->pTxBuffPtr = pData;
  1035. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  1036. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  1037. {
  1038. hi2s->TxXferSize = (Size << 1U);
  1039. hi2s->TxXferCount = (Size << 1U);
  1040. }
  1041. else
  1042. {
  1043. hi2s->TxXferSize = Size;
  1044. hi2s->TxXferCount = Size;
  1045. }
  1046. /* Set the I2S Tx DMA Half transfer complete callback */
  1047. hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
  1048. /* Set the I2S Tx DMA transfer complete callback */
  1049. hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
  1050. /* Set the DMA error callback */
  1051. hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
  1052. /* Enable the Tx DMA Stream/Channel */
  1053. if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
  1054. (uint32_t)hi2s->pTxBuffPtr,
  1055. (uint32_t)&hi2s->Instance->DR,
  1056. hi2s->TxXferSize))
  1057. {
  1058. /* Update SPI error code */
  1059. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1060. hi2s->State = HAL_I2S_STATE_READY;
  1061. __HAL_UNLOCK(hi2s);
  1062. return HAL_ERROR;
  1063. }
  1064. /* Check if the I2S is already enabled */
  1065. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  1066. {
  1067. /* Enable I2S peripheral */
  1068. __HAL_I2S_ENABLE(hi2s);
  1069. }
  1070. /* Check if the I2S Tx request is already enabled */
  1071. if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
  1072. {
  1073. /* Enable Tx DMA Request */
  1074. SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1075. }
  1076. __HAL_UNLOCK(hi2s);
  1077. return HAL_OK;
  1078. }
  1079. /**
  1080. * @brief Receive an amount of data in non-blocking mode with DMA
  1081. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1082. * the configuration information for I2S module
  1083. * @param pData a 16-bit pointer to the Receive data buffer.
  1084. * @param Size number of data sample to be sent:
  1085. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  1086. * configuration phase, the Size parameter means the number of 16-bit data length
  1087. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  1088. * the Size parameter means the number of 24-bit or 32-bit data length.
  1089. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  1090. * between Master and Slave(example: audio streaming).
  1091. * @retval HAL status
  1092. */
  1093. HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  1094. {
  1095. uint32_t tmpreg_cfgr;
  1096. if ((pData == NULL) || (Size == 0U))
  1097. {
  1098. return HAL_ERROR;
  1099. }
  1100. /* Process Locked */
  1101. __HAL_LOCK(hi2s);
  1102. if (hi2s->State != HAL_I2S_STATE_READY)
  1103. {
  1104. __HAL_UNLOCK(hi2s);
  1105. return HAL_BUSY;
  1106. }
  1107. /* Set state and reset error code */
  1108. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  1109. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  1110. hi2s->pRxBuffPtr = pData;
  1111. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  1112. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  1113. {
  1114. hi2s->RxXferSize = (Size << 1U);
  1115. hi2s->RxXferCount = (Size << 1U);
  1116. }
  1117. else
  1118. {
  1119. hi2s->RxXferSize = Size;
  1120. hi2s->RxXferCount = Size;
  1121. }
  1122. /* Set the I2S Rx DMA Half transfer complete callback */
  1123. hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
  1124. /* Set the I2S Rx DMA transfer complete callback */
  1125. hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
  1126. /* Set the DMA error callback */
  1127. hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
  1128. /* Check if Master Receiver mode is selected */
  1129. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  1130. {
  1131. /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
  1132. access to the SPI_SR register. */
  1133. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  1134. }
  1135. /* Enable the Rx DMA Stream/Channel */
  1136. if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
  1137. hi2s->RxXferSize))
  1138. {
  1139. /* Update SPI error code */
  1140. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1141. hi2s->State = HAL_I2S_STATE_READY;
  1142. __HAL_UNLOCK(hi2s);
  1143. return HAL_ERROR;
  1144. }
  1145. /* Check if the I2S is already enabled */
  1146. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  1147. {
  1148. /* Enable I2S peripheral */
  1149. __HAL_I2S_ENABLE(hi2s);
  1150. }
  1151. /* Check if the I2S Rx request is already enabled */
  1152. if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
  1153. {
  1154. /* Enable Rx DMA Request */
  1155. SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1156. }
  1157. __HAL_UNLOCK(hi2s);
  1158. return HAL_OK;
  1159. }
  1160. /**
  1161. * @brief Pauses the audio DMA Stream/Channel playing from the Media.
  1162. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1163. * the configuration information for I2S module
  1164. * @retval HAL status
  1165. */
  1166. HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
  1167. {
  1168. /* Process Locked */
  1169. __HAL_LOCK(hi2s);
  1170. if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1171. {
  1172. /* Disable the I2S DMA Tx request */
  1173. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1174. }
  1175. else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1176. {
  1177. /* Disable the I2S DMA Rx request */
  1178. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1179. }
  1180. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  1181. else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  1182. {
  1183. /* Pause the audio file playing by disabling the I2S DMA request */
  1184. CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
  1185. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
  1186. }
  1187. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  1188. else
  1189. {
  1190. /* nothing to do */
  1191. }
  1192. /* Process Unlocked */
  1193. __HAL_UNLOCK(hi2s);
  1194. return HAL_OK;
  1195. }
  1196. /**
  1197. * @brief Resumes the audio DMA Stream/Channel playing from the Media.
  1198. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1199. * the configuration information for I2S module
  1200. * @retval HAL status
  1201. */
  1202. HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
  1203. {
  1204. /* Process Locked */
  1205. __HAL_LOCK(hi2s);
  1206. if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1207. {
  1208. /* Enable the I2S DMA Tx request */
  1209. SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1210. }
  1211. else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1212. {
  1213. /* Enable the I2S DMA Rx request */
  1214. SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1215. }
  1216. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  1217. else if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  1218. {
  1219. /* Pause the audio file playing by disabling the I2S DMA request */
  1220. SET_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  1221. SET_BIT(I2SxEXT(hi2s->Instance)->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  1222. /* If the I2Sext peripheral is still not enabled, enable it */
  1223. if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
  1224. {
  1225. /* Enable I2Sext peripheral */
  1226. __HAL_I2SEXT_ENABLE(hi2s);
  1227. }
  1228. }
  1229. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  1230. else
  1231. {
  1232. /* nothing to do */
  1233. }
  1234. /* If the I2S peripheral is still not enabled, enable it */
  1235. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  1236. {
  1237. /* Enable I2S peripheral */
  1238. __HAL_I2S_ENABLE(hi2s);
  1239. }
  1240. /* Process Unlocked */
  1241. __HAL_UNLOCK(hi2s);
  1242. return HAL_OK;
  1243. }
  1244. /**
  1245. * @brief Stops the audio DMA Stream/Channel playing from the Media.
  1246. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1247. * the configuration information for I2S module
  1248. * @retval HAL status
  1249. */
  1250. HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
  1251. {
  1252. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  1253. uint32_t tickstart;
  1254. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  1255. HAL_StatusTypeDef errorcode = HAL_OK;
  1256. /* The Lock is not implemented on this API to allow the user application
  1257. to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
  1258. when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
  1259. and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
  1260. */
  1261. if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
  1262. {
  1263. /* Abort the I2S DMA tx Stream/Channel */
  1264. if (hi2s->hdmatx != NULL)
  1265. {
  1266. /* Disable the I2S DMA tx Stream/Channel */
  1267. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
  1268. {
  1269. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1270. errorcode = HAL_ERROR;
  1271. }
  1272. }
  1273. /* Wait until TXE flag is set */
  1274. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
  1275. {
  1276. /* Set the error code */
  1277. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  1278. hi2s->State = HAL_I2S_STATE_READY;
  1279. errorcode = HAL_ERROR;
  1280. }
  1281. /* Wait until BSY flag is Reset */
  1282. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
  1283. {
  1284. /* Set the error code */
  1285. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  1286. hi2s->State = HAL_I2S_STATE_READY;
  1287. errorcode = HAL_ERROR;
  1288. }
  1289. /* Disable I2S peripheral */
  1290. __HAL_I2S_DISABLE(hi2s);
  1291. /* Clear UDR flag */
  1292. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  1293. /* Disable the I2S Tx DMA requests */
  1294. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1295. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  1296. if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  1297. {
  1298. /* Abort the I2S DMA rx Stream/Channel */
  1299. if (hi2s->hdmarx != NULL)
  1300. {
  1301. /* Disable the I2S DMA rx Stream/Channel */
  1302. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
  1303. {
  1304. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1305. errorcode = HAL_ERROR;
  1306. }
  1307. }
  1308. /* Disable I2Sext peripheral */
  1309. __HAL_I2SEXT_DISABLE(hi2s);
  1310. /* Clear OVR flag */
  1311. __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s);
  1312. /* Disable the I2SxEXT DMA request */
  1313. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
  1314. if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)
  1315. {
  1316. /* Set the error code */
  1317. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
  1318. /* Set the I2S State ready */
  1319. hi2s->State = HAL_I2S_STATE_READY;
  1320. errorcode = HAL_ERROR;
  1321. }
  1322. else
  1323. {
  1324. /* Read DR to Flush RX Data */
  1325. READ_REG(I2SxEXT(hi2s->Instance)->DR);
  1326. }
  1327. }
  1328. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  1329. }
  1330. else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
  1331. {
  1332. /* Abort the I2S DMA rx Stream/Channel */
  1333. if (hi2s->hdmarx != NULL)
  1334. {
  1335. /* Disable the I2S DMA rx Stream/Channel */
  1336. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
  1337. {
  1338. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1339. errorcode = HAL_ERROR;
  1340. }
  1341. }
  1342. #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
  1343. if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
  1344. {
  1345. /* Abort the I2S DMA tx Stream/Channel */
  1346. if (hi2s->hdmatx != NULL)
  1347. {
  1348. /* Disable the I2S DMA tx Stream/Channel */
  1349. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
  1350. {
  1351. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1352. errorcode = HAL_ERROR;
  1353. }
  1354. }
  1355. tickstart = HAL_GetTick();
  1356. /* Wait until TXE flag is set */
  1357. while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET)
  1358. {
  1359. if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
  1360. {
  1361. /* Set the error code */
  1362. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  1363. /* Set the I2S State ready */
  1364. hi2s->State = HAL_I2S_STATE_READY;
  1365. errorcode = HAL_ERROR;
  1366. }
  1367. }
  1368. /* Wait until BSY flag is Reset */
  1369. while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET)
  1370. {
  1371. if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG))
  1372. {
  1373. /* Set the error code */
  1374. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  1375. /* Set the I2S State ready */
  1376. hi2s->State = HAL_I2S_STATE_READY;
  1377. errorcode = HAL_ERROR;
  1378. }
  1379. }
  1380. /* Disable I2Sext peripheral */
  1381. __HAL_I2SEXT_DISABLE(hi2s);
  1382. /* Clear UDR flag */
  1383. __HAL_I2SEXT_CLEAR_UDRFLAG(hi2s);
  1384. /* Disable the I2SxEXT DMA request */
  1385. CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
  1386. }
  1387. #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
  1388. /* Disable I2S peripheral */
  1389. __HAL_I2S_DISABLE(hi2s);
  1390. /* Clear OVR flag */
  1391. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  1392. /* Disable the I2S Rx DMA request */
  1393. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1394. if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
  1395. {
  1396. /* Set the error code */
  1397. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
  1398. /* Set the I2S State ready */
  1399. hi2s->State = HAL_I2S_STATE_READY;
  1400. errorcode = HAL_ERROR;
  1401. }
  1402. else
  1403. {
  1404. /* Read DR to Flush RX Data */
  1405. READ_REG((hi2s->Instance)->DR);
  1406. }
  1407. }
  1408. hi2s->State = HAL_I2S_STATE_READY;
  1409. return errorcode;
  1410. }
  1411. /**
  1412. * @brief This function handles I2S interrupt request.
  1413. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1414. * the configuration information for I2S module
  1415. * @retval None
  1416. */
  1417. void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  1418. {
  1419. /* Call the IrqHandler ISR set during HAL_I2S_INIT */
  1420. hi2s->IrqHandlerISR(hi2s);
  1421. }
  1422. /**
  1423. * @brief Tx Transfer Half completed callbacks
  1424. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1425. * the configuration information for I2S module
  1426. * @retval None
  1427. */
  1428. __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  1429. {
  1430. /* Prevent unused argument(s) compilation warning */
  1431. UNUSED(hi2s);
  1432. /* NOTE : This function Should not be modified, when the callback is needed,
  1433. the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
  1434. */
  1435. }
  1436. /**
  1437. * @brief Tx Transfer completed callbacks
  1438. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1439. * the configuration information for I2S module
  1440. * @retval None
  1441. */
  1442. __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
  1443. {
  1444. /* Prevent unused argument(s) compilation warning */
  1445. UNUSED(hi2s);
  1446. /* NOTE : This function Should not be modified, when the callback is needed,
  1447. the HAL_I2S_TxCpltCallback could be implemented in the user file
  1448. */
  1449. }
  1450. /**
  1451. * @brief Rx Transfer half completed callbacks
  1452. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1453. * the configuration information for I2S module
  1454. * @retval None
  1455. */
  1456. __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  1457. {
  1458. /* Prevent unused argument(s) compilation warning */
  1459. UNUSED(hi2s);
  1460. /* NOTE : This function Should not be modified, when the callback is needed,
  1461. the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
  1462. */
  1463. }
  1464. /**
  1465. * @brief Rx Transfer completed callbacks
  1466. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1467. * the configuration information for I2S module
  1468. * @retval None
  1469. */
  1470. __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
  1471. {
  1472. /* Prevent unused argument(s) compilation warning */
  1473. UNUSED(hi2s);
  1474. /* NOTE : This function Should not be modified, when the callback is needed,
  1475. the HAL_I2S_RxCpltCallback could be implemented in the user file
  1476. */
  1477. }
  1478. /**
  1479. * @brief I2S error callbacks
  1480. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1481. * the configuration information for I2S module
  1482. * @retval None
  1483. */
  1484. __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
  1485. {
  1486. /* Prevent unused argument(s) compilation warning */
  1487. UNUSED(hi2s);
  1488. /* NOTE : This function Should not be modified, when the callback is needed,
  1489. the HAL_I2S_ErrorCallback could be implemented in the user file
  1490. */
  1491. }
  1492. /**
  1493. * @}
  1494. */
  1495. /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
  1496. * @brief Peripheral State functions
  1497. *
  1498. @verbatim
  1499. ===============================================================================
  1500. ##### Peripheral State and Errors functions #####
  1501. ===============================================================================
  1502. [..]
  1503. This subsection permits to get in run-time the status of the peripheral
  1504. and the data flow.
  1505. @endverbatim
  1506. * @{
  1507. */
  1508. /**
  1509. * @brief Return the I2S state
  1510. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1511. * the configuration information for I2S module
  1512. * @retval HAL state
  1513. */
  1514. HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
  1515. {
  1516. return hi2s->State;
  1517. }
  1518. /**
  1519. * @brief Return the I2S error code
  1520. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1521. * the configuration information for I2S module
  1522. * @retval I2S Error Code
  1523. */
  1524. uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
  1525. {
  1526. return hi2s->ErrorCode;
  1527. }
  1528. /**
  1529. * @}
  1530. */
  1531. /**
  1532. * @}
  1533. */
  1534. /** @addtogroup I2S_Private_Functions I2S Private Functions
  1535. * @{
  1536. */
  1537. /**
  1538. * @brief DMA I2S transmit process complete callback
  1539. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1540. * the configuration information for the specified DMA module.
  1541. * @retval None
  1542. */
  1543. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
  1544. {
  1545. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1546. /* if DMA is configured in DMA_NORMAL Mode */
  1547. if (hdma->Init.Mode == DMA_NORMAL)
  1548. {
  1549. /* Disable Tx DMA Request */
  1550. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1551. hi2s->TxXferCount = 0U;
  1552. hi2s->State = HAL_I2S_STATE_READY;
  1553. }
  1554. /* Call user Tx complete callback */
  1555. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1556. hi2s->TxCpltCallback(hi2s);
  1557. #else
  1558. HAL_I2S_TxCpltCallback(hi2s);
  1559. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1560. }
  1561. /**
  1562. * @brief DMA I2S transmit process half complete callback
  1563. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1564. * the configuration information for the specified DMA module.
  1565. * @retval None
  1566. */
  1567. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  1568. {
  1569. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1570. /* Call user Tx half complete callback */
  1571. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1572. hi2s->TxHalfCpltCallback(hi2s);
  1573. #else
  1574. HAL_I2S_TxHalfCpltCallback(hi2s);
  1575. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1576. }
  1577. /**
  1578. * @brief DMA I2S receive process complete callback
  1579. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1580. * the configuration information for the specified DMA module.
  1581. * @retval None
  1582. */
  1583. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
  1584. {
  1585. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1586. /* if DMA is configured in DMA_NORMAL Mode */
  1587. if (hdma->Init.Mode == DMA_NORMAL)
  1588. {
  1589. /* Disable Rx DMA Request */
  1590. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1591. hi2s->RxXferCount = 0U;
  1592. hi2s->State = HAL_I2S_STATE_READY;
  1593. }
  1594. /* Call user Rx complete callback */
  1595. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1596. hi2s->RxCpltCallback(hi2s);
  1597. #else
  1598. HAL_I2S_RxCpltCallback(hi2s);
  1599. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1600. }
  1601. /**
  1602. * @brief DMA I2S receive process half complete callback
  1603. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1604. * the configuration information for the specified DMA module.
  1605. * @retval None
  1606. */
  1607. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  1608. {
  1609. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1610. /* Call user Rx half complete callback */
  1611. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1612. hi2s->RxHalfCpltCallback(hi2s);
  1613. #else
  1614. HAL_I2S_RxHalfCpltCallback(hi2s);
  1615. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1616. }
  1617. /**
  1618. * @brief DMA I2S communication error callback
  1619. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1620. * the configuration information for the specified DMA module.
  1621. * @retval None
  1622. */
  1623. static void I2S_DMAError(DMA_HandleTypeDef *hdma)
  1624. {
  1625. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1626. /* Disable Rx and Tx DMA Request */
  1627. CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  1628. hi2s->TxXferCount = 0U;
  1629. hi2s->RxXferCount = 0U;
  1630. hi2s->State = HAL_I2S_STATE_READY;
  1631. /* Set the error code and execute error callback*/
  1632. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1633. /* Call user error callback */
  1634. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1635. hi2s->ErrorCallback(hi2s);
  1636. #else
  1637. HAL_I2S_ErrorCallback(hi2s);
  1638. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1639. }
  1640. /**
  1641. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  1642. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1643. * the configuration information for I2S module
  1644. * @retval None
  1645. */
  1646. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
  1647. {
  1648. /* Transmit data */
  1649. hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
  1650. hi2s->pTxBuffPtr++;
  1651. hi2s->TxXferCount--;
  1652. if (hi2s->TxXferCount == 0U)
  1653. {
  1654. /* Disable TXE and ERR interrupt */
  1655. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1656. hi2s->State = HAL_I2S_STATE_READY;
  1657. /* Call user Tx complete callback */
  1658. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1659. hi2s->TxCpltCallback(hi2s);
  1660. #else
  1661. HAL_I2S_TxCpltCallback(hi2s);
  1662. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1663. }
  1664. }
  1665. /**
  1666. * @brief Receive an amount of data in non-blocking mode with Interrupt
  1667. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1668. * the configuration information for I2S module
  1669. * @retval None
  1670. */
  1671. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
  1672. {
  1673. /* Receive data */
  1674. (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
  1675. hi2s->pRxBuffPtr++;
  1676. hi2s->RxXferCount--;
  1677. if (hi2s->RxXferCount == 0U)
  1678. {
  1679. /* Disable RXNE and ERR interrupt */
  1680. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  1681. hi2s->State = HAL_I2S_STATE_READY;
  1682. /* Call user Rx complete callback */
  1683. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1684. hi2s->RxCpltCallback(hi2s);
  1685. #else
  1686. HAL_I2S_RxCpltCallback(hi2s);
  1687. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1688. }
  1689. }
  1690. /**
  1691. * @brief This function handles I2S interrupt request.
  1692. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
  1693. * the configuration information for I2S module
  1694. * @retval None
  1695. */
  1696. static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  1697. {
  1698. __IO uint32_t i2ssr = hi2s->Instance->SR;
  1699. if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1700. {
  1701. /* I2S in mode Receiver ------------------------------------------------*/
  1702. if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
  1703. {
  1704. I2S_Receive_IT(hi2s);
  1705. }
  1706. /* I2S Overrun error interrupt occurred -------------------------------------*/
  1707. if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
  1708. {
  1709. /* Disable RXNE and ERR interrupt */
  1710. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  1711. /* Clear Overrun flag */
  1712. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  1713. /* Set the I2S State ready */
  1714. hi2s->State = HAL_I2S_STATE_READY;
  1715. /* Set the error code and execute error callback*/
  1716. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  1717. /* Call user error callback */
  1718. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1719. hi2s->ErrorCallback(hi2s);
  1720. #else
  1721. HAL_I2S_ErrorCallback(hi2s);
  1722. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1723. }
  1724. }
  1725. if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1726. {
  1727. /* I2S in mode Transmitter -----------------------------------------------*/
  1728. if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
  1729. {
  1730. I2S_Transmit_IT(hi2s);
  1731. }
  1732. /* I2S Underrun error interrupt occurred --------------------------------*/
  1733. if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
  1734. {
  1735. /* Disable TXE and ERR interrupt */
  1736. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1737. /* Clear Underrun flag */
  1738. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  1739. /* Set the I2S State ready */
  1740. hi2s->State = HAL_I2S_STATE_READY;
  1741. /* Set the error code and execute error callback*/
  1742. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  1743. /* Call user error callback */
  1744. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1745. hi2s->ErrorCallback(hi2s);
  1746. #else
  1747. HAL_I2S_ErrorCallback(hi2s);
  1748. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1749. }
  1750. }
  1751. }
  1752. /**
  1753. * @brief This function handles I2S Communication Timeout.
  1754. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1755. * the configuration information for I2S module
  1756. * @param Flag Flag checked
  1757. * @param State Value of the flag expected
  1758. * @param Timeout Duration of the timeout
  1759. * @retval HAL status
  1760. */
  1761. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
  1762. uint32_t Timeout)
  1763. {
  1764. uint32_t tickstart;
  1765. /* Get tick */
  1766. tickstart = HAL_GetTick();
  1767. /* Wait until flag is set to status*/
  1768. while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
  1769. {
  1770. if (Timeout != HAL_MAX_DELAY)
  1771. {
  1772. if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
  1773. {
  1774. /* Set the I2S State ready */
  1775. hi2s->State = HAL_I2S_STATE_READY;
  1776. /* Process Unlocked */
  1777. __HAL_UNLOCK(hi2s);
  1778. return HAL_TIMEOUT;
  1779. }
  1780. }
  1781. }
  1782. return HAL_OK;
  1783. }
  1784. /**
  1785. * @}
  1786. */
  1787. /**
  1788. * @}
  1789. */
  1790. /**
  1791. * @}
  1792. */
  1793. #endif /* HAL_I2S_MODULE_ENABLED */