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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_dsi.c
  4. * @author MCD Application Team
  5. * @brief DSI HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the DSI peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral Control functions
  11. * + Peripheral State and Errors functions
  12. ******************************************************************************
  13. * @attention
  14. *
  15. * Copyright (c) 2016 STMicroelectronics.
  16. * All rights reserved.
  17. *
  18. * This software is licensed under terms that can be found in the LICENSE file
  19. * in the root directory of this software component.
  20. * If no LICENSE file comes with this software, it is provided AS-IS.
  21. *
  22. ******************************************************************************
  23. @verbatim
  24. ==============================================================================
  25. ##### How to use this driver #####
  26. ==============================================================================
  27. [..]
  28. The DSI HAL driver can be used as follows:
  29. (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
  30. (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
  31. (##) Enable the DSI interface clock
  32. (##) NVIC configuration if you need to use interrupt process
  33. (+++) Configure the DSI interrupt priority
  34. (+++) Enable the NVIC DSI IRQ Channel
  35. (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
  36. TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
  37. *** Configuration ***
  38. =========================
  39. [..]
  40. (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
  41. command mode.
  42. (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
  43. (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
  44. (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
  45. (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
  46. Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
  47. to write DSI short packets, long packets and to read DSI packets.
  48. (#) The DSI Host Offers two Low power modes :
  49. (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
  50. It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
  51. and HAL_DSI_ExitULPMData()
  52. (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
  53. It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
  54. and HAL_DSI_ExitULPM()
  55. (#) To control DSI state you can use the following function: HAL_DSI_GetState()
  56. *** Error management ***
  57. ========================
  58. [..]
  59. (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
  60. When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
  61. the error code by calling function HAL_DSI_GetError()
  62. *** DSI HAL driver macros list ***
  63. =============================================
  64. [..]
  65. Below the list of most used macros in DSI HAL driver.
  66. (+) __HAL_DSI_ENABLE: Enable the DSI Host.
  67. (+) __HAL_DSI_DISABLE: Disable the DSI Host.
  68. (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
  69. (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
  70. (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
  71. (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
  72. (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
  73. (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
  74. (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
  75. (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
  76. (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
  77. (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
  78. (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
  79. [..]
  80. (@) You can refer to the DSI HAL driver header file for more useful macros
  81. *** Callback registration ***
  82. =============================================
  83. [..]
  84. The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
  85. allows the user to configure dynamically the driver callbacks.
  86. Use Function HAL_DSI_RegisterCallback() to register a callback.
  87. [..]
  88. Function HAL_DSI_RegisterCallback() allows to register following callbacks:
  89. (+) TearingEffectCallback : DSI Tearing Effect Callback.
  90. (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
  91. (+) ErrorCallback : DSI Error Callback
  92. (+) MspInitCallback : DSI MspInit.
  93. (+) MspDeInitCallback : DSI MspDeInit.
  94. [..]
  95. This function takes as parameters the HAL peripheral handle, the callback ID
  96. and a pointer to the user callback function.
  97. [..]
  98. Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
  99. weak function.
  100. HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
  101. and the callback ID.
  102. [..]
  103. This function allows to reset following callbacks:
  104. (+) TearingEffectCallback : DSI Tearing Effect Callback.
  105. (+) EndOfRefreshCallback : DSI End Of Refresh Callback.
  106. (+) ErrorCallback : DSI Error Callback
  107. (+) MspInitCallback : DSI MspInit.
  108. (+) MspDeInitCallback : DSI MspDeInit.
  109. [..]
  110. By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
  111. all callbacks are set to the corresponding weak functions:
  112. examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
  113. Exception done for MspInit and MspDeInit functions that are respectively
  114. reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
  115. and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
  116. If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
  117. keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
  118. [..]
  119. Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
  120. Exception done MspInit/MspDeInit that can be registered/unregistered
  121. in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
  122. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  123. In that case first register the MspInit/MspDeInit user callbacks
  124. using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
  125. or HAL_DSI_Init() function.
  126. [..]
  127. When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
  128. not defined, the callback registration feature is not available and all callbacks
  129. are set to the corresponding weak functions.
  130. @endverbatim
  131. ******************************************************************************
  132. */
  133. /* Includes ------------------------------------------------------------------*/
  134. #include "stm32f4xx_hal.h"
  135. /** @addtogroup STM32F4xx_HAL_Driver
  136. * @{
  137. */
  138. #ifdef HAL_DSI_MODULE_ENABLED
  139. #if defined(DSI)
  140. /** @addtogroup DSI
  141. * @{
  142. */
  143. /* Private types -------------------------------------------------------------*/
  144. /* Private defines -----------------------------------------------------------*/
  145. /** @addtogroup DSI_Private_Constants
  146. * @{
  147. */
  148. #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
  149. #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
  150. DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
  151. DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
  152. DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
  153. #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
  154. #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
  155. #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
  156. #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
  157. #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
  158. #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
  159. #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
  160. #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
  161. #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
  162. /**
  163. * @}
  164. */
  165. /* Private variables ---------------------------------------------------------*/
  166. /* Private constants ---------------------------------------------------------*/
  167. /* Private macros ------------------------------------------------------------*/
  168. /* Private function prototypes -----------------------------------------------*/
  169. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
  170. uint32_t Data1);
  171. static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
  172. uint32_t ChannelID,
  173. uint32_t Mode,
  174. uint32_t Param1,
  175. uint32_t Param2);
  176. /* Private functions ---------------------------------------------------------*/
  177. /** @defgroup DSI_Private_Functions DSI Private Functions
  178. * @{
  179. */
  180. /**
  181. * @brief Generic DSI packet header configuration
  182. * @param DSIx Pointer to DSI register base
  183. * @param ChannelID Virtual channel ID of the header packet
  184. * @param DataType Packet data type of the header packet
  185. * This parameter can be any value of :
  186. * @arg DSI_SHORT_WRITE_PKT_Data_Type
  187. * @arg DSI_LONG_WRITE_PKT_Data_Type
  188. * @arg DSI_SHORT_READ_PKT_Data_Type
  189. * @arg DSI_MAX_RETURN_PKT_SIZE
  190. * @param Data0 Word count LSB
  191. * @param Data1 Word count MSB
  192. * @retval None
  193. */
  194. static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
  195. uint32_t ChannelID,
  196. uint32_t DataType,
  197. uint32_t Data0,
  198. uint32_t Data1)
  199. {
  200. /* Update the DSI packet header with new information */
  201. DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
  202. }
  203. /**
  204. * @brief write short DCS or short Generic command
  205. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  206. * the configuration information for the DSI.
  207. * @param ChannelID Virtual channel ID.
  208. * @param Mode DSI short packet data type.
  209. * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
  210. * @param Param1 DSC command or first generic parameter.
  211. * This parameter can be any value of @arg DSI_DCS_Command or a
  212. * generic command code.
  213. * @param Param2 DSC parameter or second generic parameter.
  214. * @retval HAL status
  215. */
  216. static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
  217. uint32_t ChannelID,
  218. uint32_t Mode,
  219. uint32_t Param1,
  220. uint32_t Param2)
  221. {
  222. uint32_t tickstart;
  223. /* Get tick */
  224. tickstart = HAL_GetTick();
  225. /* Wait for Command FIFO Empty */
  226. while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
  227. {
  228. /* Check for the Timeout */
  229. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  230. {
  231. return HAL_TIMEOUT;
  232. }
  233. }
  234. /* Configure the packet to send a short DCS command with 0 or 1 parameter */
  235. /* Update the DSI packet header with new information */
  236. hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
  237. return HAL_OK;
  238. }
  239. /**
  240. * @}
  241. */
  242. /* Exported functions --------------------------------------------------------*/
  243. /** @addtogroup DSI_Exported_Functions
  244. * @{
  245. */
  246. /** @defgroup DSI_Group1 Initialization and Configuration functions
  247. * @brief Initialization and Configuration functions
  248. *
  249. @verbatim
  250. ===============================================================================
  251. ##### Initialization and Configuration functions #####
  252. ===============================================================================
  253. [..] This section provides functions allowing to:
  254. (+) Initialize and configure the DSI
  255. (+) De-initialize the DSI
  256. @endverbatim
  257. * @{
  258. */
  259. /**
  260. * @brief Initializes the DSI according to the specified
  261. * parameters in the DSI_InitTypeDef and create the associated handle.
  262. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  263. * the configuration information for the DSI.
  264. * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
  265. * the PLL Clock structure definition for the DSI.
  266. * @retval HAL status
  267. */
  268. HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
  269. {
  270. uint32_t tickstart;
  271. uint32_t unitIntervalx4;
  272. uint32_t tempIDF;
  273. /* Check the DSI handle allocation */
  274. if (hdsi == NULL)
  275. {
  276. return HAL_ERROR;
  277. }
  278. /* Check function parameters */
  279. assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
  280. assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
  281. assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
  282. assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
  283. assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
  284. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  285. if (hdsi->State == HAL_DSI_STATE_RESET)
  286. {
  287. /* Reset the DSI callback to the legacy weak callbacks */
  288. hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
  289. hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
  290. hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
  291. if (hdsi->MspInitCallback == NULL)
  292. {
  293. hdsi->MspInitCallback = HAL_DSI_MspInit;
  294. }
  295. /* Initialize the low level hardware */
  296. hdsi->MspInitCallback(hdsi);
  297. }
  298. #else
  299. if (hdsi->State == HAL_DSI_STATE_RESET)
  300. {
  301. /* Initialize the low level hardware */
  302. HAL_DSI_MspInit(hdsi);
  303. }
  304. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  305. /* Change DSI peripheral state */
  306. hdsi->State = HAL_DSI_STATE_BUSY;
  307. /**************** Turn on the regulator and enable the DSI PLL ****************/
  308. /* Enable the regulator */
  309. __HAL_DSI_REG_ENABLE(hdsi);
  310. /* Get tick */
  311. tickstart = HAL_GetTick();
  312. /* Wait until the regulator is ready */
  313. while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U)
  314. {
  315. /* Check for the Timeout */
  316. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  317. {
  318. return HAL_TIMEOUT;
  319. }
  320. }
  321. /* Set the PLL division factors */
  322. hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
  323. hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
  324. ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
  325. ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
  326. /* Enable the DSI PLL */
  327. __HAL_DSI_PLL_ENABLE(hdsi);
  328. /* Requires min of 400us delay before reading the PLLLS flag */
  329. /* 1ms delay is inserted that is the minimum HAL delay granularity */
  330. HAL_Delay(1);
  331. /* Get tick */
  332. tickstart = HAL_GetTick();
  333. /* Wait for the lock of the PLL */
  334. while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
  335. {
  336. /* Check for the Timeout */
  337. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  338. {
  339. return HAL_TIMEOUT;
  340. }
  341. }
  342. /*************************** Set the PHY parameters ***************************/
  343. /* D-PHY clock and digital enable*/
  344. hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  345. /* Clock lane configuration */
  346. hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
  347. hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
  348. /* Configure the number of active data lanes */
  349. hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
  350. hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
  351. /************************ Set the DSI clock parameters ************************/
  352. /* Set the TX escape clock division factor */
  353. hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
  354. hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
  355. /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
  356. /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
  357. /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
  358. tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
  359. unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV);
  360. /* Set the bit period in high-speed mode */
  361. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
  362. hdsi->Instance->WPCR[0U] |= unitIntervalx4;
  363. /****************************** Error management *****************************/
  364. /* Disable all error interrupts and reset the Error Mask */
  365. hdsi->Instance->IER[0U] = 0U;
  366. hdsi->Instance->IER[1U] = 0U;
  367. hdsi->ErrorMsk = 0U;
  368. /* Initialize the error code */
  369. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  370. /* Initialize the DSI state*/
  371. hdsi->State = HAL_DSI_STATE_READY;
  372. return HAL_OK;
  373. }
  374. /**
  375. * @brief De-initializes the DSI peripheral registers to their default reset
  376. * values.
  377. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  378. * the configuration information for the DSI.
  379. * @retval HAL status
  380. */
  381. HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
  382. {
  383. /* Check the DSI handle allocation */
  384. if (hdsi == NULL)
  385. {
  386. return HAL_ERROR;
  387. }
  388. /* Change DSI peripheral state */
  389. hdsi->State = HAL_DSI_STATE_BUSY;
  390. /* Disable the DSI wrapper */
  391. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  392. /* Disable the DSI host */
  393. __HAL_DSI_DISABLE(hdsi);
  394. /* D-PHY clock and digital disable */
  395. hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
  396. /* Turn off the DSI PLL */
  397. __HAL_DSI_PLL_DISABLE(hdsi);
  398. /* Disable the regulator */
  399. __HAL_DSI_REG_DISABLE(hdsi);
  400. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  401. if (hdsi->MspDeInitCallback == NULL)
  402. {
  403. hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
  404. }
  405. /* DeInit the low level hardware */
  406. hdsi->MspDeInitCallback(hdsi);
  407. #else
  408. /* DeInit the low level hardware */
  409. HAL_DSI_MspDeInit(hdsi);
  410. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  411. /* Initialize the error code */
  412. hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
  413. /* Initialize the DSI state*/
  414. hdsi->State = HAL_DSI_STATE_RESET;
  415. /* Release Lock */
  416. __HAL_UNLOCK(hdsi);
  417. return HAL_OK;
  418. }
  419. /**
  420. * @brief Enable the error monitor flags
  421. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  422. * the configuration information for the DSI.
  423. * @param ActiveErrors indicates which error interrupts will be enabled.
  424. * This parameter can be any combination of @arg DSI_Error_Data_Type.
  425. * @retval HAL status
  426. */
  427. HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
  428. {
  429. /* Process locked */
  430. __HAL_LOCK(hdsi);
  431. hdsi->Instance->IER[0U] = 0U;
  432. hdsi->Instance->IER[1U] = 0U;
  433. /* Store active errors to the handle */
  434. hdsi->ErrorMsk = ActiveErrors;
  435. if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
  436. {
  437. /* Enable the interrupt generation on selected errors */
  438. hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
  439. }
  440. if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
  441. {
  442. /* Enable the interrupt generation on selected errors */
  443. hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
  444. }
  445. if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
  446. {
  447. /* Enable the interrupt generation on selected errors */
  448. hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
  449. }
  450. if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
  451. {
  452. /* Enable the interrupt generation on selected errors */
  453. hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
  454. }
  455. if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
  456. {
  457. /* Enable the interrupt generation on selected errors */
  458. hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
  459. }
  460. if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
  461. {
  462. /* Enable the interrupt generation on selected errors */
  463. hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
  464. }
  465. if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
  466. {
  467. /* Enable the interrupt generation on selected errors */
  468. hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
  469. }
  470. if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
  471. {
  472. /* Enable the interrupt generation on selected errors */
  473. hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
  474. }
  475. if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
  476. {
  477. /* Enable the interrupt generation on selected errors */
  478. hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
  479. }
  480. if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
  481. {
  482. /* Enable the interrupt generation on selected errors */
  483. hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
  484. }
  485. /* Process Unlocked */
  486. __HAL_UNLOCK(hdsi);
  487. return HAL_OK;
  488. }
  489. /**
  490. * @brief Initializes the DSI MSP.
  491. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  492. * the configuration information for the DSI.
  493. * @retval None
  494. */
  495. __weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
  496. {
  497. /* Prevent unused argument(s) compilation warning */
  498. UNUSED(hdsi);
  499. /* NOTE : This function Should not be modified, when the callback is needed,
  500. the HAL_DSI_MspInit could be implemented in the user file
  501. */
  502. }
  503. /**
  504. * @brief De-initializes the DSI MSP.
  505. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  506. * the configuration information for the DSI.
  507. * @retval None
  508. */
  509. __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
  510. {
  511. /* Prevent unused argument(s) compilation warning */
  512. UNUSED(hdsi);
  513. /* NOTE : This function Should not be modified, when the callback is needed,
  514. the HAL_DSI_MspDeInit could be implemented in the user file
  515. */
  516. }
  517. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  518. /**
  519. * @brief Register a User DSI Callback
  520. * To be used instead of the weak predefined callback
  521. * @param hdsi dsi handle
  522. * @param CallbackID ID of the callback to be registered
  523. * This parameter can be one of the following values:
  524. * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
  525. * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
  526. * @arg HAL_DSI_ERROR_CB_ID Error Callback ID
  527. * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
  528. * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
  529. * @param pCallback pointer to the Callback function
  530. * @retval status
  531. */
  532. HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
  533. pDSI_CallbackTypeDef pCallback)
  534. {
  535. HAL_StatusTypeDef status = HAL_OK;
  536. if (pCallback == NULL)
  537. {
  538. /* Update the error code */
  539. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  540. return HAL_ERROR;
  541. }
  542. /* Process locked */
  543. __HAL_LOCK(hdsi);
  544. if (hdsi->State == HAL_DSI_STATE_READY)
  545. {
  546. switch (CallbackID)
  547. {
  548. case HAL_DSI_TEARING_EFFECT_CB_ID :
  549. hdsi->TearingEffectCallback = pCallback;
  550. break;
  551. case HAL_DSI_ENDOF_REFRESH_CB_ID :
  552. hdsi->EndOfRefreshCallback = pCallback;
  553. break;
  554. case HAL_DSI_ERROR_CB_ID :
  555. hdsi->ErrorCallback = pCallback;
  556. break;
  557. case HAL_DSI_MSPINIT_CB_ID :
  558. hdsi->MspInitCallback = pCallback;
  559. break;
  560. case HAL_DSI_MSPDEINIT_CB_ID :
  561. hdsi->MspDeInitCallback = pCallback;
  562. break;
  563. default :
  564. /* Update the error code */
  565. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  566. /* Return error status */
  567. status = HAL_ERROR;
  568. break;
  569. }
  570. }
  571. else if (hdsi->State == HAL_DSI_STATE_RESET)
  572. {
  573. switch (CallbackID)
  574. {
  575. case HAL_DSI_MSPINIT_CB_ID :
  576. hdsi->MspInitCallback = pCallback;
  577. break;
  578. case HAL_DSI_MSPDEINIT_CB_ID :
  579. hdsi->MspDeInitCallback = pCallback;
  580. break;
  581. default :
  582. /* Update the error code */
  583. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  584. /* Return error status */
  585. status = HAL_ERROR;
  586. break;
  587. }
  588. }
  589. else
  590. {
  591. /* Update the error code */
  592. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  593. /* Return error status */
  594. status = HAL_ERROR;
  595. }
  596. /* Release Lock */
  597. __HAL_UNLOCK(hdsi);
  598. return status;
  599. }
  600. /**
  601. * @brief Unregister a DSI Callback
  602. * DSI callback is redirected to the weak predefined callback
  603. * @param hdsi dsi handle
  604. * @param CallbackID ID of the callback to be unregistered
  605. * This parameter can be one of the following values:
  606. * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
  607. * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
  608. * @arg HAL_DSI_ERROR_CB_ID Error Callback ID
  609. * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
  610. * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
  611. * @retval status
  612. */
  613. HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
  614. {
  615. HAL_StatusTypeDef status = HAL_OK;
  616. /* Process locked */
  617. __HAL_LOCK(hdsi);
  618. if (hdsi->State == HAL_DSI_STATE_READY)
  619. {
  620. switch (CallbackID)
  621. {
  622. case HAL_DSI_TEARING_EFFECT_CB_ID :
  623. hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
  624. break;
  625. case HAL_DSI_ENDOF_REFRESH_CB_ID :
  626. hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
  627. break;
  628. case HAL_DSI_ERROR_CB_ID :
  629. hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
  630. break;
  631. case HAL_DSI_MSPINIT_CB_ID :
  632. hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
  633. break;
  634. case HAL_DSI_MSPDEINIT_CB_ID :
  635. hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
  636. break;
  637. default :
  638. /* Update the error code */
  639. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  640. /* Return error status */
  641. status = HAL_ERROR;
  642. break;
  643. }
  644. }
  645. else if (hdsi->State == HAL_DSI_STATE_RESET)
  646. {
  647. switch (CallbackID)
  648. {
  649. case HAL_DSI_MSPINIT_CB_ID :
  650. hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
  651. break;
  652. case HAL_DSI_MSPDEINIT_CB_ID :
  653. hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
  654. break;
  655. default :
  656. /* Update the error code */
  657. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  658. /* Return error status */
  659. status = HAL_ERROR;
  660. break;
  661. }
  662. }
  663. else
  664. {
  665. /* Update the error code */
  666. hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
  667. /* Return error status */
  668. status = HAL_ERROR;
  669. }
  670. /* Release Lock */
  671. __HAL_UNLOCK(hdsi);
  672. return status;
  673. }
  674. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  675. /**
  676. * @}
  677. */
  678. /** @defgroup DSI_Group2 IO operation functions
  679. * @brief IO operation functions
  680. *
  681. @verbatim
  682. ===============================================================================
  683. ##### IO operation functions #####
  684. ===============================================================================
  685. [..] This section provides function allowing to:
  686. (+) Handle DSI interrupt request
  687. @endverbatim
  688. * @{
  689. */
  690. /**
  691. * @brief Handles DSI interrupt request.
  692. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  693. * the configuration information for the DSI.
  694. * @retval HAL status
  695. */
  696. void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
  697. {
  698. uint32_t ErrorStatus0;
  699. uint32_t ErrorStatus1;
  700. /* Tearing Effect Interrupt management ***************************************/
  701. if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
  702. {
  703. if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
  704. {
  705. /* Clear the Tearing Effect Interrupt Flag */
  706. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
  707. /* Tearing Effect Callback */
  708. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  709. /*Call registered Tearing Effect callback */
  710. hdsi->TearingEffectCallback(hdsi);
  711. #else
  712. /*Call legacy Tearing Effect callback*/
  713. HAL_DSI_TearingEffectCallback(hdsi);
  714. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  715. }
  716. }
  717. /* End of Refresh Interrupt management ***************************************/
  718. if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
  719. {
  720. if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
  721. {
  722. /* Clear the End of Refresh Interrupt Flag */
  723. __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
  724. /* End of Refresh Callback */
  725. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  726. /*Call registered End of refresh callback */
  727. hdsi->EndOfRefreshCallback(hdsi);
  728. #else
  729. /*Call Legacy End of refresh callback */
  730. HAL_DSI_EndOfRefreshCallback(hdsi);
  731. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  732. }
  733. }
  734. /* Error Interrupts management ***********************************************/
  735. if (hdsi->ErrorMsk != 0U)
  736. {
  737. ErrorStatus0 = hdsi->Instance->ISR[0U];
  738. ErrorStatus0 &= hdsi->Instance->IER[0U];
  739. ErrorStatus1 = hdsi->Instance->ISR[1U];
  740. ErrorStatus1 &= hdsi->Instance->IER[1U];
  741. if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
  742. {
  743. hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
  744. }
  745. if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
  746. {
  747. hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
  748. }
  749. if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
  750. {
  751. hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
  752. }
  753. if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
  754. {
  755. hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
  756. }
  757. if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
  758. {
  759. hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
  760. }
  761. if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
  762. {
  763. hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
  764. }
  765. if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
  766. {
  767. hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
  768. }
  769. if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
  770. {
  771. hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
  772. }
  773. if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
  774. {
  775. hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
  776. }
  777. if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
  778. {
  779. hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
  780. }
  781. /* Check only selected errors */
  782. if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
  783. {
  784. /* DSI error interrupt callback */
  785. #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
  786. /*Call registered Error callback */
  787. hdsi->ErrorCallback(hdsi);
  788. #else
  789. /*Call Legacy Error callback */
  790. HAL_DSI_ErrorCallback(hdsi);
  791. #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
  792. }
  793. }
  794. }
  795. /**
  796. * @brief Tearing Effect DSI callback.
  797. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  798. * the configuration information for the DSI.
  799. * @retval None
  800. */
  801. __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
  802. {
  803. /* Prevent unused argument(s) compilation warning */
  804. UNUSED(hdsi);
  805. /* NOTE : This function Should not be modified, when the callback is needed,
  806. the HAL_DSI_TearingEffectCallback could be implemented in the user file
  807. */
  808. }
  809. /**
  810. * @brief End of Refresh DSI callback.
  811. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  812. * the configuration information for the DSI.
  813. * @retval None
  814. */
  815. __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
  816. {
  817. /* Prevent unused argument(s) compilation warning */
  818. UNUSED(hdsi);
  819. /* NOTE : This function Should not be modified, when the callback is needed,
  820. the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
  821. */
  822. }
  823. /**
  824. * @brief Operation Error DSI callback.
  825. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  826. * the configuration information for the DSI.
  827. * @retval None
  828. */
  829. __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
  830. {
  831. /* Prevent unused argument(s) compilation warning */
  832. UNUSED(hdsi);
  833. /* NOTE : This function Should not be modified, when the callback is needed,
  834. the HAL_DSI_ErrorCallback could be implemented in the user file
  835. */
  836. }
  837. /**
  838. * @}
  839. */
  840. /** @defgroup DSI_Group3 Peripheral Control functions
  841. * @brief Peripheral Control functions
  842. *
  843. @verbatim
  844. ===============================================================================
  845. ##### Peripheral Control functions #####
  846. ===============================================================================
  847. [..] This section provides functions allowing to:
  848. (+) Configure the Generic interface read-back Virtual Channel ID
  849. (+) Select video mode and configure the corresponding parameters
  850. (+) Configure command transmission mode: High-speed or Low-power
  851. (+) Configure the flow control
  852. (+) Configure the DSI PHY timer
  853. (+) Configure the DSI HOST timeout
  854. (+) Configure the DSI HOST timeout
  855. (+) Start/Stop the DSI module
  856. (+) Refresh the display in command mode
  857. (+) Controls the display color mode in Video mode
  858. (+) Control the display shutdown in Video mode
  859. (+) write short DCS or short Generic command
  860. (+) write long DCS or long Generic command
  861. (+) Read command (DCS or generic)
  862. (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
  863. (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
  864. (+) Start/Stop test pattern generation
  865. (+) Slew-Rate And Delay Tuning
  866. (+) Low-Power Reception Filter Tuning
  867. (+) Activate an additional current path on all lanes to meet the SDDTx parameter
  868. (+) Custom lane pins configuration
  869. (+) Set custom timing for the PHY
  870. (+) Force the Clock/Data Lane in TX Stop Mode
  871. (+) Force LP Receiver in Low-Power Mode
  872. (+) Force Data Lanes in RX Mode after a BTA
  873. (+) Enable a pull-down on the lanes to prevent from floating states when unused
  874. (+) Switch off the contention detection on data lanes
  875. @endverbatim
  876. * @{
  877. */
  878. /**
  879. * @brief Configure the Generic interface read-back Virtual Channel ID.
  880. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  881. * the configuration information for the DSI.
  882. * @param VirtualChannelID Virtual channel ID
  883. * @retval HAL status
  884. */
  885. HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
  886. {
  887. /* Process locked */
  888. __HAL_LOCK(hdsi);
  889. /* Update the GVCID register */
  890. hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
  891. hdsi->Instance->GVCIDR |= VirtualChannelID;
  892. /* Process unlocked */
  893. __HAL_UNLOCK(hdsi);
  894. return HAL_OK;
  895. }
  896. /**
  897. * @brief Select video mode and configure the corresponding parameters
  898. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  899. * the configuration information for the DSI.
  900. * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
  901. * the DSI video mode configuration parameters
  902. * @retval HAL status
  903. */
  904. HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
  905. {
  906. /* Process locked */
  907. __HAL_LOCK(hdsi);
  908. /* Check the parameters */
  909. assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
  910. assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
  911. assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
  912. assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
  913. assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
  914. assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
  915. assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
  916. assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
  917. assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
  918. assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
  919. assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
  920. assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
  921. assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
  922. /* Check the LooselyPacked variant only in 18-bit mode */
  923. if (VidCfg->ColorCoding == DSI_RGB666)
  924. {
  925. assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
  926. }
  927. /* Select video mode by resetting CMDM and DSIM bits */
  928. hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
  929. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  930. /* Configure the video mode transmission type */
  931. hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
  932. hdsi->Instance->VMCR |= VidCfg->Mode;
  933. /* Configure the video packet size */
  934. hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
  935. hdsi->Instance->VPCR |= VidCfg->PacketSize;
  936. /* Set the chunks number to be transmitted through the DSI link */
  937. hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
  938. hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
  939. /* Set the size of the null packet */
  940. hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
  941. hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
  942. /* Select the virtual channel for the LTDC interface traffic */
  943. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  944. hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
  945. /* Configure the polarity of control signals */
  946. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  947. hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
  948. /* Select the color coding for the host */
  949. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  950. hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
  951. /* Select the color coding for the wrapper */
  952. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  953. hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
  954. /* Enable/disable the loosely packed variant to 18-bit configuration */
  955. if (VidCfg->ColorCoding == DSI_RGB666)
  956. {
  957. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
  958. hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
  959. }
  960. /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
  961. hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
  962. hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
  963. /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
  964. hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
  965. hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
  966. /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
  967. hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
  968. hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
  969. /* Set the Vertical Synchronization Active (VSA) */
  970. hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
  971. hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
  972. /* Set the Vertical Back Porch (VBP)*/
  973. hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
  974. hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
  975. /* Set the Vertical Front Porch (VFP)*/
  976. hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
  977. hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
  978. /* Set the Vertical Active period*/
  979. hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
  980. hdsi->Instance->VVACR |= VidCfg->VerticalActive;
  981. /* Configure the command transmission mode */
  982. hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
  983. hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
  984. /* Low power largest packet size */
  985. hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
  986. hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
  987. /* Low power VACT largest packet size */
  988. hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
  989. hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
  990. /* Enable LP transition in HFP period */
  991. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
  992. hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
  993. /* Enable LP transition in HBP period */
  994. hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
  995. hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
  996. /* Enable LP transition in VACT period */
  997. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
  998. hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
  999. /* Enable LP transition in VFP period */
  1000. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
  1001. hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
  1002. /* Enable LP transition in VBP period */
  1003. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
  1004. hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
  1005. /* Enable LP transition in vertical sync period */
  1006. hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
  1007. hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
  1008. /* Enable the request for an acknowledge response at the end of a frame */
  1009. hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
  1010. hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
  1011. /* Process unlocked */
  1012. __HAL_UNLOCK(hdsi);
  1013. return HAL_OK;
  1014. }
  1015. /**
  1016. * @brief Select adapted command mode and configure the corresponding parameters
  1017. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1018. * the configuration information for the DSI.
  1019. * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
  1020. * the DSI command mode configuration parameters
  1021. * @retval HAL status
  1022. */
  1023. HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
  1024. {
  1025. /* Process locked */
  1026. __HAL_LOCK(hdsi);
  1027. /* Check the parameters */
  1028. assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
  1029. assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
  1030. assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
  1031. assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
  1032. assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
  1033. assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
  1034. assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
  1035. assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
  1036. assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
  1037. /* Select command mode by setting CMDM and DSIM bits */
  1038. hdsi->Instance->MCR |= DSI_MCR_CMDM;
  1039. hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
  1040. hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
  1041. /* Select the virtual channel for the LTDC interface traffic */
  1042. hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
  1043. hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
  1044. /* Configure the polarity of control signals */
  1045. hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
  1046. hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
  1047. /* Select the color coding for the host */
  1048. hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
  1049. hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
  1050. /* Select the color coding for the wrapper */
  1051. hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
  1052. hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
  1053. /* Configure the maximum allowed size for write memory command */
  1054. hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
  1055. hdsi->Instance->LCCR |= CmdCfg->CommandSize;
  1056. /* Configure the tearing effect source and polarity and select the refresh mode */
  1057. hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
  1058. hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
  1059. CmdCfg->VSyncPol);
  1060. /* Configure the tearing effect acknowledge request */
  1061. hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
  1062. hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
  1063. /* Enable the Tearing Effect interrupt */
  1064. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
  1065. /* Enable the End of Refresh interrupt */
  1066. __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
  1067. /* Process unlocked */
  1068. __HAL_UNLOCK(hdsi);
  1069. return HAL_OK;
  1070. }
  1071. /**
  1072. * @brief Configure command transmission mode: High-speed or Low-power
  1073. * and enable/disable acknowledge request after packet transmission
  1074. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1075. * the configuration information for the DSI.
  1076. * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
  1077. * the DSI command transmission mode configuration parameters
  1078. * @retval HAL status
  1079. */
  1080. HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
  1081. {
  1082. /* Process locked */
  1083. __HAL_LOCK(hdsi);
  1084. assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
  1085. assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
  1086. assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
  1087. assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
  1088. assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
  1089. assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
  1090. assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
  1091. assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
  1092. assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
  1093. assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
  1094. assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
  1095. assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
  1096. assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
  1097. /* Select High-speed or Low-power for command transmission */
  1098. hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
  1099. DSI_CMCR_GSW1TX | \
  1100. DSI_CMCR_GSW2TX | \
  1101. DSI_CMCR_GSR0TX | \
  1102. DSI_CMCR_GSR1TX | \
  1103. DSI_CMCR_GSR2TX | \
  1104. DSI_CMCR_GLWTX | \
  1105. DSI_CMCR_DSW0TX | \
  1106. DSI_CMCR_DSW1TX | \
  1107. DSI_CMCR_DSR0TX | \
  1108. DSI_CMCR_DLWTX | \
  1109. DSI_CMCR_MRDPS);
  1110. hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \
  1111. LPCmd->LPGenShortWriteOneP | \
  1112. LPCmd->LPGenShortWriteTwoP | \
  1113. LPCmd->LPGenShortReadNoP | \
  1114. LPCmd->LPGenShortReadOneP | \
  1115. LPCmd->LPGenShortReadTwoP | \
  1116. LPCmd->LPGenLongWrite | \
  1117. LPCmd->LPDcsShortWriteNoP | \
  1118. LPCmd->LPDcsShortWriteOneP | \
  1119. LPCmd->LPDcsShortReadNoP | \
  1120. LPCmd->LPDcsLongWrite | \
  1121. LPCmd->LPMaxReadPacket);
  1122. /* Configure the acknowledge request after each packet transmission */
  1123. hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
  1124. hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
  1125. /* Process unlocked */
  1126. __HAL_UNLOCK(hdsi);
  1127. return HAL_OK;
  1128. }
  1129. /**
  1130. * @brief Configure the flow control parameters
  1131. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1132. * the configuration information for the DSI.
  1133. * @param FlowControl flow control feature(s) to be enabled.
  1134. * This parameter can be any combination of @arg DSI_FlowControl.
  1135. * @retval HAL status
  1136. */
  1137. HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
  1138. {
  1139. /* Process locked */
  1140. __HAL_LOCK(hdsi);
  1141. /* Check the parameters */
  1142. assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
  1143. /* Set the DSI Host Protocol Configuration Register */
  1144. hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
  1145. hdsi->Instance->PCR |= FlowControl;
  1146. /* Process unlocked */
  1147. __HAL_UNLOCK(hdsi);
  1148. return HAL_OK;
  1149. }
  1150. /**
  1151. * @brief Configure the DSI PHY timer parameters
  1152. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1153. * the configuration information for the DSI.
  1154. * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
  1155. * the DSI PHY timing parameters
  1156. * @retval HAL status
  1157. */
  1158. HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
  1159. {
  1160. uint32_t maxTime;
  1161. /* Process locked */
  1162. __HAL_LOCK(hdsi);
  1163. maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
  1164. PhyTimers->ClockLaneHS2LPTime;
  1165. /* Clock lane timer configuration */
  1166. /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
  1167. High-Speed transmission.
  1168. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
  1169. to Low-Power and from Low-Power to High-Speed.
  1170. This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
  1171. Register (DSI_CLTCR).
  1172. But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
  1173. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
  1174. */
  1175. hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
  1176. hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
  1177. /* Data lane timer configuration */
  1178. hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
  1179. hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | ((
  1180. PhyTimers->DataLaneHS2LPTime) << 24U));
  1181. /* Configure the wait period to request HS transmission after a stop state */
  1182. hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
  1183. hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
  1184. /* Process unlocked */
  1185. __HAL_UNLOCK(hdsi);
  1186. return HAL_OK;
  1187. }
  1188. /**
  1189. * @brief Configure the DSI HOST timeout parameters
  1190. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1191. * the configuration information for the DSI.
  1192. * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
  1193. * the DSI host timeout parameters
  1194. * @retval HAL status
  1195. */
  1196. HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
  1197. {
  1198. /* Process locked */
  1199. __HAL_LOCK(hdsi);
  1200. /* Set the timeout clock division factor */
  1201. hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
  1202. hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
  1203. /* High-speed transmission timeout */
  1204. hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
  1205. hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
  1206. /* Low-power reception timeout */
  1207. hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
  1208. hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
  1209. /* High-speed read timeout */
  1210. hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
  1211. hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
  1212. /* Low-power read timeout */
  1213. hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
  1214. hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
  1215. /* High-speed write timeout */
  1216. hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
  1217. hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
  1218. /* High-speed write presp mode */
  1219. hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
  1220. hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
  1221. /* Low-speed write timeout */
  1222. hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
  1223. hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
  1224. /* BTA timeout */
  1225. hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
  1226. hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
  1227. /* Process unlocked */
  1228. __HAL_UNLOCK(hdsi);
  1229. return HAL_OK;
  1230. }
  1231. /**
  1232. * @brief Start the DSI module
  1233. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1234. * the configuration information for the DSI.
  1235. * @retval HAL status
  1236. */
  1237. HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
  1238. {
  1239. /* Process locked */
  1240. __HAL_LOCK(hdsi);
  1241. /* Enable the DSI host */
  1242. __HAL_DSI_ENABLE(hdsi);
  1243. /* Enable the DSI wrapper */
  1244. __HAL_DSI_WRAPPER_ENABLE(hdsi);
  1245. /* Process unlocked */
  1246. __HAL_UNLOCK(hdsi);
  1247. return HAL_OK;
  1248. }
  1249. /**
  1250. * @brief Stop the DSI module
  1251. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1252. * the configuration information for the DSI.
  1253. * @retval HAL status
  1254. */
  1255. HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
  1256. {
  1257. /* Process locked */
  1258. __HAL_LOCK(hdsi);
  1259. /* Disable the DSI host */
  1260. __HAL_DSI_DISABLE(hdsi);
  1261. /* Disable the DSI wrapper */
  1262. __HAL_DSI_WRAPPER_DISABLE(hdsi);
  1263. /* Process unlocked */
  1264. __HAL_UNLOCK(hdsi);
  1265. return HAL_OK;
  1266. }
  1267. /**
  1268. * @brief Refresh the display in command mode
  1269. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1270. * the configuration information for the DSI.
  1271. * @retval HAL status
  1272. */
  1273. HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
  1274. {
  1275. /* Process locked */
  1276. __HAL_LOCK(hdsi);
  1277. /* Update the display */
  1278. hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
  1279. /* Process unlocked */
  1280. __HAL_UNLOCK(hdsi);
  1281. return HAL_OK;
  1282. }
  1283. /**
  1284. * @brief Controls the display color mode in Video mode
  1285. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1286. * the configuration information for the DSI.
  1287. * @param ColorMode Color mode (full or 8-colors).
  1288. * This parameter can be any value of @arg DSI_Color_Mode
  1289. * @retval HAL status
  1290. */
  1291. HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
  1292. {
  1293. /* Process locked */
  1294. __HAL_LOCK(hdsi);
  1295. /* Check the parameters */
  1296. assert_param(IS_DSI_COLOR_MODE(ColorMode));
  1297. /* Update the display color mode */
  1298. hdsi->Instance->WCR &= ~DSI_WCR_COLM;
  1299. hdsi->Instance->WCR |= ColorMode;
  1300. /* Process unlocked */
  1301. __HAL_UNLOCK(hdsi);
  1302. return HAL_OK;
  1303. }
  1304. /**
  1305. * @brief Control the display shutdown in Video mode
  1306. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1307. * the configuration information for the DSI.
  1308. * @param Shutdown Shut-down (Display-ON or Display-OFF).
  1309. * This parameter can be any value of @arg DSI_ShutDown
  1310. * @retval HAL status
  1311. */
  1312. HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
  1313. {
  1314. /* Process locked */
  1315. __HAL_LOCK(hdsi);
  1316. /* Check the parameters */
  1317. assert_param(IS_DSI_SHUT_DOWN(Shutdown));
  1318. /* Update the display Shutdown */
  1319. hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
  1320. hdsi->Instance->WCR |= Shutdown;
  1321. /* Process unlocked */
  1322. __HAL_UNLOCK(hdsi);
  1323. return HAL_OK;
  1324. }
  1325. /**
  1326. * @brief write short DCS or short Generic command
  1327. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1328. * the configuration information for the DSI.
  1329. * @param ChannelID Virtual channel ID.
  1330. * @param Mode DSI short packet data type.
  1331. * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
  1332. * @param Param1 DSC command or first generic parameter.
  1333. * This parameter can be any value of @arg DSI_DCS_Command or a
  1334. * generic command code.
  1335. * @param Param2 DSC parameter or second generic parameter.
  1336. * @retval HAL status
  1337. */
  1338. HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
  1339. uint32_t ChannelID,
  1340. uint32_t Mode,
  1341. uint32_t Param1,
  1342. uint32_t Param2)
  1343. {
  1344. HAL_StatusTypeDef status;
  1345. /* Check the parameters */
  1346. assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
  1347. /* Process locked */
  1348. __HAL_LOCK(hdsi);
  1349. status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
  1350. /* Process unlocked */
  1351. __HAL_UNLOCK(hdsi);
  1352. return status;
  1353. }
  1354. /**
  1355. * @brief write long DCS or long Generic command
  1356. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1357. * the configuration information for the DSI.
  1358. * @param ChannelID Virtual channel ID.
  1359. * @param Mode DSI long packet data type.
  1360. * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
  1361. * @param NbParams Number of parameters.
  1362. * @param Param1 DSC command or first generic parameter.
  1363. * This parameter can be any value of @arg DSI_DCS_Command or a
  1364. * generic command code
  1365. * @param ParametersTable Pointer to parameter values table.
  1366. * @retval HAL status
  1367. */
  1368. HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
  1369. uint32_t ChannelID,
  1370. uint32_t Mode,
  1371. uint32_t NbParams,
  1372. uint32_t Param1,
  1373. uint8_t *ParametersTable)
  1374. {
  1375. uint32_t uicounter;
  1376. uint32_t nbBytes;
  1377. uint32_t count;
  1378. uint32_t tickstart;
  1379. uint32_t fifoword;
  1380. uint8_t *pparams = ParametersTable;
  1381. /* Process locked */
  1382. __HAL_LOCK(hdsi);
  1383. /* Check the parameters */
  1384. assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
  1385. /* Get tick */
  1386. tickstart = HAL_GetTick();
  1387. /* Wait for Command FIFO Empty */
  1388. while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
  1389. {
  1390. /* Check for the Timeout */
  1391. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1392. {
  1393. /* Process Unlocked */
  1394. __HAL_UNLOCK(hdsi);
  1395. return HAL_TIMEOUT;
  1396. }
  1397. }
  1398. /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
  1399. fifoword = Param1;
  1400. nbBytes = (NbParams < 3U) ? NbParams : 3U;
  1401. for (count = 0U; count < nbBytes; count++)
  1402. {
  1403. fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
  1404. }
  1405. hdsi->Instance->GPDR = fifoword;
  1406. uicounter = NbParams - nbBytes;
  1407. pparams += nbBytes;
  1408. /* Set the Next parameters on the write FIFO command*/
  1409. while (uicounter != 0U)
  1410. {
  1411. nbBytes = (uicounter < 4U) ? uicounter : 4U;
  1412. fifoword = 0U;
  1413. for (count = 0U; count < nbBytes; count++)
  1414. {
  1415. fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
  1416. }
  1417. hdsi->Instance->GPDR = fifoword;
  1418. uicounter -= nbBytes;
  1419. pparams += nbBytes;
  1420. }
  1421. /* Configure the packet to send a long DCS command */
  1422. DSI_ConfigPacketHeader(hdsi->Instance,
  1423. ChannelID,
  1424. Mode,
  1425. ((NbParams + 1U) & 0x00FFU),
  1426. (((NbParams + 1U) & 0xFF00U) >> 8U));
  1427. /* Process unlocked */
  1428. __HAL_UNLOCK(hdsi);
  1429. return HAL_OK;
  1430. }
  1431. /**
  1432. * @brief Read command (DCS or generic)
  1433. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1434. * the configuration information for the DSI.
  1435. * @param ChannelNbr Virtual channel ID
  1436. * @param Array pointer to a buffer to store the payload of a read back operation.
  1437. * @param Size Data size to be read (in byte).
  1438. * @param Mode DSI read packet data type.
  1439. * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
  1440. * @param DCSCmd DCS get/read command.
  1441. * @param ParametersTable Pointer to parameter values table.
  1442. * @retval HAL status
  1443. */
  1444. HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
  1445. uint32_t ChannelNbr,
  1446. uint8_t *Array,
  1447. uint32_t Size,
  1448. uint32_t Mode,
  1449. uint32_t DCSCmd,
  1450. uint8_t *ParametersTable)
  1451. {
  1452. uint32_t tickstart;
  1453. uint8_t *pdata = Array;
  1454. uint32_t datasize = Size;
  1455. uint32_t fifoword;
  1456. uint32_t nbbytes;
  1457. uint32_t count;
  1458. /* Process locked */
  1459. __HAL_LOCK(hdsi);
  1460. /* Check the parameters */
  1461. assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
  1462. if (datasize > 2U)
  1463. {
  1464. /* set max return packet size */
  1465. if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
  1466. (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
  1467. {
  1468. /* Process Unlocked */
  1469. __HAL_UNLOCK(hdsi);
  1470. return HAL_ERROR;
  1471. }
  1472. }
  1473. /* Configure the packet to read command */
  1474. if (Mode == DSI_DCS_SHORT_PKT_READ)
  1475. {
  1476. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
  1477. }
  1478. else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
  1479. {
  1480. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
  1481. }
  1482. else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
  1483. {
  1484. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
  1485. }
  1486. else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
  1487. {
  1488. DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
  1489. }
  1490. else
  1491. {
  1492. /* Process Unlocked */
  1493. __HAL_UNLOCK(hdsi);
  1494. return HAL_ERROR;
  1495. }
  1496. /* Get tick */
  1497. tickstart = HAL_GetTick();
  1498. /* If DSI fifo is not empty, read requested bytes */
  1499. while (((int32_t)(datasize)) > 0)
  1500. {
  1501. if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
  1502. {
  1503. fifoword = hdsi->Instance->GPDR;
  1504. nbbytes = (datasize < 4U) ? datasize : 4U;
  1505. for (count = 0U; count < nbbytes; count++)
  1506. {
  1507. *pdata = (uint8_t)(fifoword >> (8U * count));
  1508. pdata++;
  1509. datasize--;
  1510. }
  1511. }
  1512. /* Check for the Timeout */
  1513. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1514. {
  1515. /* Process Unlocked */
  1516. __HAL_UNLOCK(hdsi);
  1517. return HAL_TIMEOUT;
  1518. }
  1519. /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */
  1520. /* issued to the panel and the read data is not captured by the DSI Host */
  1521. /* which returns Packet Size Error. */
  1522. /* Need to ensure that the Read command has finished before checking PSE */
  1523. if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
  1524. {
  1525. if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
  1526. {
  1527. /* Process Unlocked */
  1528. __HAL_UNLOCK(hdsi);
  1529. return HAL_ERROR;
  1530. }
  1531. }
  1532. }
  1533. /* Process unlocked */
  1534. __HAL_UNLOCK(hdsi);
  1535. return HAL_OK;
  1536. }
  1537. /**
  1538. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1539. * (only data lanes are in ULPM)
  1540. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1541. * the configuration information for the DSI.
  1542. * @retval HAL status
  1543. */
  1544. HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
  1545. {
  1546. uint32_t tickstart;
  1547. /* Process locked */
  1548. __HAL_LOCK(hdsi);
  1549. /* ULPS Request on Data Lanes */
  1550. hdsi->Instance->PUCR |= DSI_PUCR_URDL;
  1551. /* Get tick */
  1552. tickstart = HAL_GetTick();
  1553. /* Wait until the D-PHY active lanes enter into ULPM */
  1554. if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1555. {
  1556. while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
  1557. {
  1558. /* Check for the Timeout */
  1559. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1560. {
  1561. /* Process Unlocked */
  1562. __HAL_UNLOCK(hdsi);
  1563. return HAL_TIMEOUT;
  1564. }
  1565. }
  1566. }
  1567. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1568. {
  1569. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
  1570. {
  1571. /* Check for the Timeout */
  1572. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1573. {
  1574. /* Process Unlocked */
  1575. __HAL_UNLOCK(hdsi);
  1576. return HAL_TIMEOUT;
  1577. }
  1578. }
  1579. }
  1580. else
  1581. {
  1582. /* Process unlocked */
  1583. __HAL_UNLOCK(hdsi);
  1584. return HAL_ERROR;
  1585. }
  1586. /* Process unlocked */
  1587. __HAL_UNLOCK(hdsi);
  1588. return HAL_OK;
  1589. }
  1590. /**
  1591. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
  1592. * (only data lanes are in ULPM)
  1593. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1594. * the configuration information for the DSI.
  1595. * @retval HAL status
  1596. */
  1597. HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
  1598. {
  1599. uint32_t tickstart;
  1600. /* Process locked */
  1601. __HAL_LOCK(hdsi);
  1602. /* Exit ULPS on Data Lanes */
  1603. hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
  1604. /* Get tick */
  1605. tickstart = HAL_GetTick();
  1606. /* Wait until all active lanes exit ULPM */
  1607. if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1608. {
  1609. while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
  1610. {
  1611. /* Check for the Timeout */
  1612. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1613. {
  1614. /* Process Unlocked */
  1615. __HAL_UNLOCK(hdsi);
  1616. return HAL_TIMEOUT;
  1617. }
  1618. }
  1619. }
  1620. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1621. {
  1622. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
  1623. {
  1624. /* Check for the Timeout */
  1625. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1626. {
  1627. /* Process Unlocked */
  1628. __HAL_UNLOCK(hdsi);
  1629. return HAL_TIMEOUT;
  1630. }
  1631. }
  1632. }
  1633. else
  1634. {
  1635. /* Process unlocked */
  1636. __HAL_UNLOCK(hdsi);
  1637. return HAL_ERROR;
  1638. }
  1639. /* wait for 1 ms*/
  1640. HAL_Delay(1U);
  1641. /* De-assert the ULPM requests and the ULPM exit bits */
  1642. hdsi->Instance->PUCR = 0U;
  1643. /* Process unlocked */
  1644. __HAL_UNLOCK(hdsi);
  1645. return HAL_OK;
  1646. }
  1647. /**
  1648. * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1649. * (both data and clock lanes are in ULPM)
  1650. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1651. * the configuration information for the DSI.
  1652. * @retval HAL status
  1653. */
  1654. HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
  1655. {
  1656. uint32_t tickstart;
  1657. /* Process locked */
  1658. __HAL_LOCK(hdsi);
  1659. /* Clock lane configuration: no more HS request */
  1660. hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
  1661. /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
  1662. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
  1663. /* ULPS Request on Clock and Data Lanes */
  1664. hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
  1665. /* Get tick */
  1666. tickstart = HAL_GetTick();
  1667. /* Wait until all active lanes exit ULPM */
  1668. if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1669. {
  1670. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
  1671. {
  1672. /* Check for the Timeout */
  1673. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1674. {
  1675. /* Process Unlocked */
  1676. __HAL_UNLOCK(hdsi);
  1677. return HAL_TIMEOUT;
  1678. }
  1679. }
  1680. }
  1681. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1682. {
  1683. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
  1684. {
  1685. /* Check for the Timeout */
  1686. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1687. {
  1688. /* Process Unlocked */
  1689. __HAL_UNLOCK(hdsi);
  1690. return HAL_TIMEOUT;
  1691. }
  1692. }
  1693. }
  1694. else
  1695. {
  1696. /* Process unlocked */
  1697. __HAL_UNLOCK(hdsi);
  1698. return HAL_ERROR;
  1699. }
  1700. /* Turn off the DSI PLL */
  1701. __HAL_DSI_PLL_DISABLE(hdsi);
  1702. /* Process unlocked */
  1703. __HAL_UNLOCK(hdsi);
  1704. return HAL_OK;
  1705. }
  1706. /**
  1707. * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
  1708. * (both data and clock lanes are in ULPM)
  1709. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1710. * the configuration information for the DSI.
  1711. * @retval HAL status
  1712. */
  1713. HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
  1714. {
  1715. uint32_t tickstart;
  1716. /* Process locked */
  1717. __HAL_LOCK(hdsi);
  1718. /* Turn on the DSI PLL */
  1719. __HAL_DSI_PLL_ENABLE(hdsi);
  1720. /* Get tick */
  1721. tickstart = HAL_GetTick();
  1722. /* Wait for the lock of the PLL */
  1723. while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
  1724. {
  1725. /* Check for the Timeout */
  1726. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1727. {
  1728. /* Process Unlocked */
  1729. __HAL_UNLOCK(hdsi);
  1730. return HAL_TIMEOUT;
  1731. }
  1732. }
  1733. /* Exit ULPS on Clock and Data Lanes */
  1734. hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
  1735. /* Get tick */
  1736. tickstart = HAL_GetTick();
  1737. /* Wait until all active lanes exit ULPM */
  1738. if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
  1739. {
  1740. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
  1741. {
  1742. /* Check for the Timeout */
  1743. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1744. {
  1745. /* Process Unlocked */
  1746. __HAL_UNLOCK(hdsi);
  1747. return HAL_TIMEOUT;
  1748. }
  1749. }
  1750. }
  1751. else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
  1752. {
  1753. while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
  1754. DSI_PSR_UANC))
  1755. {
  1756. /* Check for the Timeout */
  1757. if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
  1758. {
  1759. /* Process Unlocked */
  1760. __HAL_UNLOCK(hdsi);
  1761. return HAL_TIMEOUT;
  1762. }
  1763. }
  1764. }
  1765. else
  1766. {
  1767. /* Process unlocked */
  1768. __HAL_UNLOCK(hdsi);
  1769. return HAL_ERROR;
  1770. }
  1771. /* wait for 1 ms */
  1772. HAL_Delay(1U);
  1773. /* De-assert the ULPM requests and the ULPM exit bits */
  1774. hdsi->Instance->PUCR = 0U;
  1775. /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
  1776. __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
  1777. /* Restore clock lane configuration to HS */
  1778. hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
  1779. /* Process unlocked */
  1780. __HAL_UNLOCK(hdsi);
  1781. return HAL_OK;
  1782. }
  1783. /**
  1784. * @brief Start test pattern generation
  1785. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1786. * the configuration information for the DSI.
  1787. * @param Mode Pattern generator mode
  1788. * This parameter can be one of the following values:
  1789. * 0 : Color bars (horizontal or vertical)
  1790. * 1 : BER pattern (vertical only)
  1791. * @param Orientation Pattern generator orientation
  1792. * This parameter can be one of the following values:
  1793. * 0 : Vertical color bars
  1794. * 1 : Horizontal color bars
  1795. * @retval HAL status
  1796. */
  1797. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
  1798. {
  1799. /* Process locked */
  1800. __HAL_LOCK(hdsi);
  1801. /* Configure pattern generator mode and orientation */
  1802. hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
  1803. hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
  1804. /* Enable pattern generator by setting PGE bit */
  1805. hdsi->Instance->VMCR |= DSI_VMCR_PGE;
  1806. /* Process unlocked */
  1807. __HAL_UNLOCK(hdsi);
  1808. return HAL_OK;
  1809. }
  1810. /**
  1811. * @brief Stop test pattern generation
  1812. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1813. * the configuration information for the DSI.
  1814. * @retval HAL status
  1815. */
  1816. HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
  1817. {
  1818. /* Process locked */
  1819. __HAL_LOCK(hdsi);
  1820. /* Disable pattern generator by clearing PGE bit */
  1821. hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
  1822. /* Process unlocked */
  1823. __HAL_UNLOCK(hdsi);
  1824. return HAL_OK;
  1825. }
  1826. /**
  1827. * @brief Set Slew-Rate And Delay Tuning
  1828. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1829. * the configuration information for the DSI.
  1830. * @param CommDelay Communication delay to be adjusted.
  1831. * This parameter can be any value of @arg DSI_Communication_Delay
  1832. * @param Lane select between clock or data lanes.
  1833. * This parameter can be any value of @arg DSI_Lane_Group
  1834. * @param Value Custom value of the slew-rate or delay
  1835. * @retval HAL status
  1836. */
  1837. HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
  1838. uint32_t Value)
  1839. {
  1840. /* Process locked */
  1841. __HAL_LOCK(hdsi);
  1842. /* Check function parameters */
  1843. assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
  1844. assert_param(IS_DSI_LANE_GROUP(Lane));
  1845. switch (CommDelay)
  1846. {
  1847. case DSI_SLEW_RATE_HSTX:
  1848. if (Lane == DSI_CLOCK_LANE)
  1849. {
  1850. /* High-Speed Transmission Slew Rate Control on Clock Lane */
  1851. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
  1852. hdsi->Instance->WPCR[1U] |= Value << 16U;
  1853. }
  1854. else if (Lane == DSI_DATA_LANES)
  1855. {
  1856. /* High-Speed Transmission Slew Rate Control on Data Lanes */
  1857. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
  1858. hdsi->Instance->WPCR[1U] |= Value << 18U;
  1859. }
  1860. else
  1861. {
  1862. /* Process unlocked */
  1863. __HAL_UNLOCK(hdsi);
  1864. return HAL_ERROR;
  1865. }
  1866. break;
  1867. case DSI_SLEW_RATE_LPTX:
  1868. if (Lane == DSI_CLOCK_LANE)
  1869. {
  1870. /* Low-Power transmission Slew Rate Compensation on Clock Lane */
  1871. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
  1872. hdsi->Instance->WPCR[1U] |= Value << 6U;
  1873. }
  1874. else if (Lane == DSI_DATA_LANES)
  1875. {
  1876. /* Low-Power transmission Slew Rate Compensation on Data Lanes */
  1877. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
  1878. hdsi->Instance->WPCR[1U] |= Value << 8U;
  1879. }
  1880. else
  1881. {
  1882. /* Process unlocked */
  1883. __HAL_UNLOCK(hdsi);
  1884. return HAL_ERROR;
  1885. }
  1886. break;
  1887. case DSI_HS_DELAY:
  1888. if (Lane == DSI_CLOCK_LANE)
  1889. {
  1890. /* High-Speed Transmission Delay on Clock Lane */
  1891. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
  1892. hdsi->Instance->WPCR[1U] |= Value;
  1893. }
  1894. else if (Lane == DSI_DATA_LANES)
  1895. {
  1896. /* High-Speed Transmission Delay on Data Lanes */
  1897. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
  1898. hdsi->Instance->WPCR[1U] |= Value << 2U;
  1899. }
  1900. else
  1901. {
  1902. /* Process unlocked */
  1903. __HAL_UNLOCK(hdsi);
  1904. return HAL_ERROR;
  1905. }
  1906. break;
  1907. default:
  1908. break;
  1909. }
  1910. /* Process unlocked */
  1911. __HAL_UNLOCK(hdsi);
  1912. return HAL_OK;
  1913. }
  1914. /**
  1915. * @brief Low-Power Reception Filter Tuning
  1916. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1917. * the configuration information for the DSI.
  1918. * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
  1919. * @retval HAL status
  1920. */
  1921. HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
  1922. {
  1923. /* Process locked */
  1924. __HAL_LOCK(hdsi);
  1925. /* Low-Power RX low-pass Filtering Tuning */
  1926. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
  1927. hdsi->Instance->WPCR[1U] |= Frequency << 25U;
  1928. /* Process unlocked */
  1929. __HAL_UNLOCK(hdsi);
  1930. return HAL_OK;
  1931. }
  1932. /**
  1933. * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
  1934. * defined in the MIPI D-PHY specification
  1935. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1936. * the configuration information for the DSI.
  1937. * @param State ENABLE or DISABLE
  1938. * @retval HAL status
  1939. */
  1940. HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
  1941. {
  1942. /* Process locked */
  1943. __HAL_LOCK(hdsi);
  1944. /* Check function parameters */
  1945. assert_param(IS_FUNCTIONAL_STATE(State));
  1946. /* Activate/Disactivate additional current path on all lanes */
  1947. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
  1948. hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
  1949. /* Process unlocked */
  1950. __HAL_UNLOCK(hdsi);
  1951. return HAL_OK;
  1952. }
  1953. /**
  1954. * @brief Custom lane pins configuration
  1955. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  1956. * the configuration information for the DSI.
  1957. * @param CustomLane Function to be applied on selected lane.
  1958. * This parameter can be any value of @arg DSI_CustomLane
  1959. * @param Lane select between clock or data lane 0 or data lane 1.
  1960. * This parameter can be any value of @arg DSI_Lane_Select
  1961. * @param State ENABLE or DISABLE
  1962. * @retval HAL status
  1963. */
  1964. HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
  1965. FunctionalState State)
  1966. {
  1967. /* Process locked */
  1968. __HAL_LOCK(hdsi);
  1969. /* Check function parameters */
  1970. assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
  1971. assert_param(IS_DSI_LANE(Lane));
  1972. assert_param(IS_FUNCTIONAL_STATE(State));
  1973. switch (CustomLane)
  1974. {
  1975. case DSI_SWAP_LANE_PINS:
  1976. if (Lane == DSI_CLK_LANE)
  1977. {
  1978. /* Swap pins on clock lane */
  1979. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
  1980. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
  1981. }
  1982. else if (Lane == DSI_DATA_LANE0)
  1983. {
  1984. /* Swap pins on data lane 0 */
  1985. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
  1986. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
  1987. }
  1988. else if (Lane == DSI_DATA_LANE1)
  1989. {
  1990. /* Swap pins on data lane 1 */
  1991. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
  1992. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
  1993. }
  1994. else
  1995. {
  1996. /* Process unlocked */
  1997. __HAL_UNLOCK(hdsi);
  1998. return HAL_ERROR;
  1999. }
  2000. break;
  2001. case DSI_INVERT_HS_SIGNAL:
  2002. if (Lane == DSI_CLK_LANE)
  2003. {
  2004. /* Invert HS signal on clock lane */
  2005. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
  2006. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
  2007. }
  2008. else if (Lane == DSI_DATA_LANE0)
  2009. {
  2010. /* Invert HS signal on data lane 0 */
  2011. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
  2012. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
  2013. }
  2014. else if (Lane == DSI_DATA_LANE1)
  2015. {
  2016. /* Invert HS signal on data lane 1 */
  2017. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
  2018. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
  2019. }
  2020. else
  2021. {
  2022. /* Process unlocked */
  2023. __HAL_UNLOCK(hdsi);
  2024. return HAL_ERROR;
  2025. }
  2026. break;
  2027. default:
  2028. break;
  2029. }
  2030. /* Process unlocked */
  2031. __HAL_UNLOCK(hdsi);
  2032. return HAL_OK;
  2033. }
  2034. /**
  2035. * @brief Set custom timing for the PHY
  2036. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2037. * the configuration information for the DSI.
  2038. * @param Timing PHY timing to be adjusted.
  2039. * This parameter can be any value of @arg DSI_PHY_Timing
  2040. * @param State ENABLE or DISABLE
  2041. * @param Value Custom value of the timing
  2042. * @retval HAL status
  2043. */
  2044. HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
  2045. {
  2046. /* Process locked */
  2047. __HAL_LOCK(hdsi);
  2048. /* Check function parameters */
  2049. assert_param(IS_DSI_PHY_TIMING(Timing));
  2050. assert_param(IS_FUNCTIONAL_STATE(State));
  2051. switch (Timing)
  2052. {
  2053. case DSI_TCLK_POST:
  2054. /* Enable/Disable custom timing setting */
  2055. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
  2056. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
  2057. if (State != DISABLE)
  2058. {
  2059. /* Set custom value */
  2060. hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
  2061. hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
  2062. }
  2063. break;
  2064. case DSI_TLPX_CLK:
  2065. /* Enable/Disable custom timing setting */
  2066. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
  2067. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
  2068. if (State != DISABLE)
  2069. {
  2070. /* Set custom value */
  2071. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
  2072. hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
  2073. }
  2074. break;
  2075. case DSI_THS_EXIT:
  2076. /* Enable/Disable custom timing setting */
  2077. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
  2078. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
  2079. if (State != DISABLE)
  2080. {
  2081. /* Set custom value */
  2082. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
  2083. hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
  2084. }
  2085. break;
  2086. case DSI_TLPX_DATA:
  2087. /* Enable/Disable custom timing setting */
  2088. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
  2089. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
  2090. if (State != DISABLE)
  2091. {
  2092. /* Set custom value */
  2093. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
  2094. hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
  2095. }
  2096. break;
  2097. case DSI_THS_ZERO:
  2098. /* Enable/Disable custom timing setting */
  2099. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
  2100. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
  2101. if (State != DISABLE)
  2102. {
  2103. /* Set custom value */
  2104. hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
  2105. hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
  2106. }
  2107. break;
  2108. case DSI_THS_TRAIL:
  2109. /* Enable/Disable custom timing setting */
  2110. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
  2111. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
  2112. if (State != DISABLE)
  2113. {
  2114. /* Set custom value */
  2115. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
  2116. hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
  2117. }
  2118. break;
  2119. case DSI_THS_PREPARE:
  2120. /* Enable/Disable custom timing setting */
  2121. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
  2122. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
  2123. if (State != DISABLE)
  2124. {
  2125. /* Set custom value */
  2126. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
  2127. hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
  2128. }
  2129. break;
  2130. case DSI_TCLK_ZERO:
  2131. /* Enable/Disable custom timing setting */
  2132. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
  2133. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
  2134. if (State != DISABLE)
  2135. {
  2136. /* Set custom value */
  2137. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
  2138. hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
  2139. }
  2140. break;
  2141. case DSI_TCLK_PREPARE:
  2142. /* Enable/Disable custom timing setting */
  2143. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
  2144. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
  2145. if (State != DISABLE)
  2146. {
  2147. /* Set custom value */
  2148. hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
  2149. hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
  2150. }
  2151. break;
  2152. default:
  2153. break;
  2154. }
  2155. /* Process unlocked */
  2156. __HAL_UNLOCK(hdsi);
  2157. return HAL_OK;
  2158. }
  2159. /**
  2160. * @brief Force the Clock/Data Lane in TX Stop Mode
  2161. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2162. * the configuration information for the DSI.
  2163. * @param Lane select between clock or data lanes.
  2164. * This parameter can be any value of @arg DSI_Lane_Group
  2165. * @param State ENABLE or DISABLE
  2166. * @retval HAL status
  2167. */
  2168. HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
  2169. {
  2170. /* Process locked */
  2171. __HAL_LOCK(hdsi);
  2172. /* Check function parameters */
  2173. assert_param(IS_DSI_LANE_GROUP(Lane));
  2174. assert_param(IS_FUNCTIONAL_STATE(State));
  2175. if (Lane == DSI_CLOCK_LANE)
  2176. {
  2177. /* Force/Unforce the Clock Lane in TX Stop Mode */
  2178. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
  2179. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
  2180. }
  2181. else if (Lane == DSI_DATA_LANES)
  2182. {
  2183. /* Force/Unforce the Data Lanes in TX Stop Mode */
  2184. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
  2185. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
  2186. }
  2187. else
  2188. {
  2189. /* Process unlocked */
  2190. __HAL_UNLOCK(hdsi);
  2191. return HAL_ERROR;
  2192. }
  2193. /* Process unlocked */
  2194. __HAL_UNLOCK(hdsi);
  2195. return HAL_OK;
  2196. }
  2197. /**
  2198. * @brief Force LP Receiver in Low-Power Mode
  2199. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2200. * the configuration information for the DSI.
  2201. * @param State ENABLE or DISABLE
  2202. * @retval HAL status
  2203. */
  2204. HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
  2205. {
  2206. /* Process locked */
  2207. __HAL_LOCK(hdsi);
  2208. /* Check function parameters */
  2209. assert_param(IS_FUNCTIONAL_STATE(State));
  2210. /* Force/Unforce LP Receiver in Low-Power Mode */
  2211. hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
  2212. hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
  2213. /* Process unlocked */
  2214. __HAL_UNLOCK(hdsi);
  2215. return HAL_OK;
  2216. }
  2217. /**
  2218. * @brief Force Data Lanes in RX Mode after a BTA
  2219. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2220. * the configuration information for the DSI.
  2221. * @param State ENABLE or DISABLE
  2222. * @retval HAL status
  2223. */
  2224. HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
  2225. {
  2226. /* Process locked */
  2227. __HAL_LOCK(hdsi);
  2228. /* Check function parameters */
  2229. assert_param(IS_FUNCTIONAL_STATE(State));
  2230. /* Force Data Lanes in RX Mode */
  2231. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
  2232. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
  2233. /* Process unlocked */
  2234. __HAL_UNLOCK(hdsi);
  2235. return HAL_OK;
  2236. }
  2237. /**
  2238. * @brief Enable a pull-down on the lanes to prevent from floating states when unused
  2239. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2240. * the configuration information for the DSI.
  2241. * @param State ENABLE or DISABLE
  2242. * @retval HAL status
  2243. */
  2244. HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
  2245. {
  2246. /* Process locked */
  2247. __HAL_LOCK(hdsi);
  2248. /* Check function parameters */
  2249. assert_param(IS_FUNCTIONAL_STATE(State));
  2250. /* Enable/Disable pull-down on lanes */
  2251. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
  2252. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
  2253. /* Process unlocked */
  2254. __HAL_UNLOCK(hdsi);
  2255. return HAL_OK;
  2256. }
  2257. /**
  2258. * @brief Switch off the contention detection on data lanes
  2259. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2260. * the configuration information for the DSI.
  2261. * @param State ENABLE or DISABLE
  2262. * @retval HAL status
  2263. */
  2264. HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
  2265. {
  2266. /* Process locked */
  2267. __HAL_LOCK(hdsi);
  2268. /* Check function parameters */
  2269. assert_param(IS_FUNCTIONAL_STATE(State));
  2270. /* Contention Detection on Data Lanes OFF */
  2271. hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
  2272. hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
  2273. /* Process unlocked */
  2274. __HAL_UNLOCK(hdsi);
  2275. return HAL_OK;
  2276. }
  2277. /**
  2278. * @}
  2279. */
  2280. /** @defgroup DSI_Group4 Peripheral State and Errors functions
  2281. * @brief Peripheral State and Errors functions
  2282. *
  2283. @verbatim
  2284. ===============================================================================
  2285. ##### Peripheral State and Errors functions #####
  2286. ===============================================================================
  2287. [..]
  2288. This subsection provides functions allowing to
  2289. (+) Check the DSI state.
  2290. (+) Get error code.
  2291. @endverbatim
  2292. * @{
  2293. */
  2294. /**
  2295. * @brief Return the DSI state
  2296. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2297. * the configuration information for the DSI.
  2298. * @retval HAL state
  2299. */
  2300. HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
  2301. {
  2302. return hdsi->State;
  2303. }
  2304. /**
  2305. * @brief Return the DSI error code
  2306. * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
  2307. * the configuration information for the DSI.
  2308. * @retval DSI Error Code
  2309. */
  2310. uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
  2311. {
  2312. /* Get the error code */
  2313. return hdsi->ErrorCode;
  2314. }
  2315. /**
  2316. * @}
  2317. */
  2318. /**
  2319. * @}
  2320. */
  2321. /**
  2322. * @}
  2323. */
  2324. #endif /* DSI */
  2325. #endif /* HAL_DSI_MODULE_ENABLED */
  2326. /**
  2327. * @}
  2328. */