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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_fmpsmbus.h
  4. * @author MCD Application Team
  5. * @brief Header file of FMPSMBUS HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.
  11. *
  12. * This software is licensed under terms that can be found in the LICENSE file
  13. * in the root directory of this software component.
  14. * If no LICENSE file comes with this software, it is provided AS-IS.
  15. *
  16. ******************************************************************************
  17. */
  18. /* Define to prevent recursive inclusion -------------------------------------*/
  19. #ifndef STM32F4xx_HAL_FMPSMBUS_H
  20. #define STM32F4xx_HAL_FMPSMBUS_H
  21. #ifdef __cplusplus
  22. extern "C" {
  23. #endif
  24. #if defined(FMPI2C_CR1_PE)
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32f4xx_hal_def.h"
  27. /** @addtogroup STM32F4xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup FMPSMBUS
  31. * @{
  32. */
  33. /* Exported types ------------------------------------------------------------*/
  34. /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types
  35. * @{
  36. */
  37. /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition
  38. * @brief FMPSMBUS Configuration Structure definition
  39. * @{
  40. */
  41. typedef struct
  42. {
  43. uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value.
  44. This parameter calculated by referring to FMPSMBUS initialization section
  45. in Reference manual */
  46. uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
  47. This parameter can be a value of @ref FMPSMBUS_Analog_Filter */
  48. uint32_t OwnAddress1; /*!< Specifies the first device own address.
  49. This parameter can be a 7-bit or 10-bit address. */
  50. uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
  51. This parameter can be a value of @ref FMPSMBUS_addressing_mode */
  52. uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
  53. This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */
  54. uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
  55. This parameter can be a 7-bit address. */
  56. uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
  57. if dual addressing mode is selected
  58. This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */
  59. uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
  60. This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */
  61. uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
  62. This parameter can be a value of @ref FMPSMBUS_nostretch_mode */
  63. uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
  64. This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */
  65. uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
  66. This parameter can be a value of @ref FMPSMBUS_peripheral_mode */
  67. uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value.
  68. (Enable bits and different timeout values)
  69. This parameter calculated by referring to FMPSMBUS initialization section
  70. in Reference manual */
  71. } FMPSMBUS_InitTypeDef;
  72. /**
  73. * @}
  74. */
  75. /** @defgroup HAL_state_definition HAL state definition
  76. * @brief HAL State definition
  77. * @{
  78. */
  79. #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */
  80. #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */
  81. #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */
  82. #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
  83. #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
  84. #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
  85. #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
  86. #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
  87. #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
  88. #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
  89. /**
  90. * @}
  91. */
  92. /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition
  93. * @brief FMPSMBUS Error Code definition
  94. * @{
  95. */
  96. #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */
  97. #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
  98. #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
  99. #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
  100. #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
  101. #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
  102. #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
  103. #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
  104. #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
  105. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  106. #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
  107. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  108. #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
  109. /**
  110. * @}
  111. */
  112. /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition
  113. * @brief FMPSMBUS handle Structure definition
  114. * @{
  115. */
  116. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  117. typedef struct __FMPSMBUS_HandleTypeDef
  118. #else
  119. typedef struct
  120. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  121. {
  122. FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */
  123. FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */
  124. uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */
  125. uint16_t XferSize; /*!< FMPSMBUS transfer size */
  126. __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */
  127. __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */
  128. __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */
  129. HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */
  130. __IO uint32_t State; /*!< FMPSMBUS communication state */
  131. __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */
  132. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  133. void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  134. /*!< FMPSMBUS Master Tx Transfer completed callback */
  135. void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  136. /*!< FMPSMBUS Master Rx Transfer completed callback */
  137. void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  138. /*!< FMPSMBUS Slave Tx Transfer completed callback */
  139. void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  140. /*!< FMPSMBUS Slave Rx Transfer completed callback */
  141. void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  142. /*!< FMPSMBUS Listen Complete callback */
  143. void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  144. /*!< FMPSMBUS Error callback */
  145. void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
  146. /*!< FMPSMBUS Slave Address Match callback */
  147. void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  148. /*!< FMPSMBUS Msp Init callback */
  149. void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus);
  150. /*!< FMPSMBUS Msp DeInit callback */
  151. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  152. } FMPSMBUS_HandleTypeDef;
  153. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  154. /**
  155. * @brief HAL FMPSMBUS Callback ID enumeration definition
  156. */
  157. typedef enum
  158. {
  159. HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */
  160. HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */
  161. HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */
  162. HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */
  163. HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */
  164. HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */
  165. HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */
  166. HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */
  167. } HAL_FMPSMBUS_CallbackIDTypeDef;
  168. /**
  169. * @brief HAL FMPSMBUS Callback pointer definition
  170. */
  171. typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  172. /*!< pointer to an FMPSMBUS callback function */
  173. typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection,
  174. uint16_t AddrMatchCode);
  175. /*!< pointer to an FMPSMBUS Address Match callback function */
  176. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  177. /**
  178. * @}
  179. */
  180. /**
  181. * @}
  182. */
  183. /* Exported constants --------------------------------------------------------*/
  184. /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants
  185. * @{
  186. */
  187. /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter
  188. * @{
  189. */
  190. #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U)
  191. #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
  192. /**
  193. * @}
  194. */
  195. /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode
  196. * @{
  197. */
  198. #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
  199. #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
  200. /**
  201. * @}
  202. */
  203. /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode
  204. * @{
  205. */
  206. #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U)
  207. #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
  208. /**
  209. * @}
  210. */
  211. /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks
  212. * @{
  213. */
  214. #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U)
  215. #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U)
  216. #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U)
  217. #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U)
  218. #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U)
  219. #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U)
  220. #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U)
  221. #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U)
  222. /**
  223. * @}
  224. */
  225. /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode
  226. * @{
  227. */
  228. #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U)
  229. #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
  230. /**
  231. * @}
  232. */
  233. /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode
  234. * @{
  235. */
  236. #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U)
  237. #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
  238. /**
  239. * @}
  240. */
  241. /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode
  242. * @{
  243. */
  244. #define FMPSMBUS_PEC_DISABLE (0x00000000U)
  245. #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN
  246. /**
  247. * @}
  248. */
  249. /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode
  250. * @{
  251. */
  252. #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN
  253. #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U)
  254. #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN
  255. /**
  256. * @}
  257. */
  258. /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition
  259. * @{
  260. */
  261. #define FMPSMBUS_SOFTEND_MODE (0x00000000U)
  262. #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD
  263. #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND
  264. #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE
  265. /**
  266. * @}
  267. */
  268. /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition
  269. * @{
  270. */
  271. #define FMPSMBUS_NO_STARTSTOP (0x00000000U)
  272. #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
  273. #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
  274. #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
  275. /**
  276. * @}
  277. */
  278. /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition
  279. * @{
  280. */
  281. /* List of XferOptions in usage of :
  282. * 1- Restart condition when direction change
  283. * 2- No Restart condition in other use cases
  284. */
  285. #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE
  286. #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE))
  287. #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
  288. #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE
  289. #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE))
  290. #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
  291. #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE))
  292. /* List of XferOptions in usage of :
  293. * 1- Restart condition in all use cases (direction change or not)
  294. */
  295. #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
  296. #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
  297. #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
  298. #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
  299. /**
  300. * @}
  301. */
  302. /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition
  303. * @brief FMPSMBUS Interrupt definition
  304. * Elements values convention: 0xXXXXXXXX
  305. * - XXXXXXXX : Interrupt control mask
  306. * @{
  307. */
  308. #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE
  309. #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE
  310. #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE
  311. #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE
  312. #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE
  313. #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
  314. #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
  315. #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \
  316. FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
  317. #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \
  318. FMPSMBUS_IT_RXI)
  319. #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
  320. #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
  321. /**
  322. * @}
  323. */
  324. /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition
  325. * @brief Flag definition
  326. * Elements values convention: 0xXXXXYYYY
  327. * - XXXXXXXX : Flag mask
  328. * @{
  329. */
  330. #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE
  331. #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS
  332. #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE
  333. #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR
  334. #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF
  335. #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF
  336. #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC
  337. #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR
  338. #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR
  339. #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO
  340. #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR
  341. #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR
  342. #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
  343. #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT
  344. #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY
  345. #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR
  346. /**
  347. * @}
  348. */
  349. /**
  350. * @}
  351. */
  352. /* Exported macros ------------------------------------------------------------*/
  353. /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros
  354. * @{
  355. */
  356. /** @brief Reset FMPSMBUS handle state.
  357. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  358. * @retval None
  359. */
  360. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  361. #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
  362. (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \
  363. (__HANDLE__)->MspInitCallback = NULL; \
  364. (__HANDLE__)->MspDeInitCallback = NULL; \
  365. } while(0)
  366. #else
  367. #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET)
  368. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  369. /** @brief Enable the specified FMPSMBUS interrupts.
  370. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  371. * @param __INTERRUPT__ specifies the interrupt source to enable.
  372. * This parameter can be one of the following values:
  373. * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
  374. * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
  375. * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
  376. * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
  377. * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
  378. * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
  379. * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
  380. *
  381. * @retval None
  382. */
  383. #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
  384. /** @brief Disable the specified FMPSMBUS interrupts.
  385. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  386. * @param __INTERRUPT__ specifies the interrupt source to disable.
  387. * This parameter can be one of the following values:
  388. * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
  389. * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
  390. * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
  391. * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
  392. * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
  393. * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
  394. * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
  395. *
  396. * @retval None
  397. */
  398. #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
  399. /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not.
  400. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  401. * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check.
  402. * This parameter can be one of the following values:
  403. * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable
  404. * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable
  405. * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable
  406. * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable
  407. * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable
  408. * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable
  409. * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable
  410. *
  411. * @retval The new state of __IT__ (SET or RESET).
  412. */
  413. #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
  414. ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  415. /** @brief Check whether the specified FMPSMBUS flag is set or not.
  416. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  417. * @param __FLAG__ specifies the flag to check.
  418. * This parameter can be one of the following values:
  419. * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty
  420. * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status
  421. * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty
  422. * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
  423. * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
  424. * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
  425. * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode)
  426. * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload
  427. * @arg @ref FMPSMBUS_FLAG_BERR Bus error
  428. * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
  429. * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
  430. * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
  431. * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  432. * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
  433. * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy
  434. * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode)
  435. *
  436. * @retval The new state of __FLAG__ (SET or RESET).
  437. */
  438. #define FMPSMBUS_FLAG_MASK (0x0001FFFFU)
  439. #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
  440. (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
  441. ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
  442. /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit.
  443. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  444. * @param __FLAG__ specifies the flag to clear.
  445. * This parameter can be any combination of the following values:
  446. * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode)
  447. * @arg @ref FMPSMBUS_FLAG_AF NACK received flag
  448. * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag
  449. * @arg @ref FMPSMBUS_FLAG_BERR Bus error
  450. * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost
  451. * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun
  452. * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception
  453. * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
  454. * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert
  455. *
  456. * @retval None
  457. */
  458. #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
  459. /** @brief Enable the specified FMPSMBUS peripheral.
  460. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  461. * @retval None
  462. */
  463. #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
  464. /** @brief Disable the specified FMPSMBUS peripheral.
  465. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  466. * @retval None
  467. */
  468. #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
  469. /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode.
  470. * @param __HANDLE__ specifies the FMPSMBUS Handle.
  471. * @retval None
  472. */
  473. #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
  474. /**
  475. * @}
  476. */
  477. /* Private constants ---------------------------------------------------------*/
  478. /* Private macros ------------------------------------------------------------*/
  479. /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros
  480. * @{
  481. */
  482. #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \
  483. ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE))
  484. #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
  485. #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \
  486. ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT))
  487. #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \
  488. ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE))
  489. #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \
  490. ((MASK) == FMPSMBUS_OA2_MASK01) || \
  491. ((MASK) == FMPSMBUS_OA2_MASK02) || \
  492. ((MASK) == FMPSMBUS_OA2_MASK03) || \
  493. ((MASK) == FMPSMBUS_OA2_MASK04) || \
  494. ((MASK) == FMPSMBUS_OA2_MASK05) || \
  495. ((MASK) == FMPSMBUS_OA2_MASK06) || \
  496. ((MASK) == FMPSMBUS_OA2_MASK07))
  497. #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \
  498. ((CALL) == FMPSMBUS_GENERALCALL_ENABLE))
  499. #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \
  500. ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE))
  501. #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \
  502. ((PEC) == FMPSMBUS_PEC_ENABLE))
  503. #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \
  504. ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \
  505. ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))
  506. #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \
  507. ((MODE) == FMPSMBUS_AUTOEND_MODE) || \
  508. ((MODE) == FMPSMBUS_SOFTEND_MODE) || \
  509. ((MODE) == FMPSMBUS_SENDPEC_MODE) || \
  510. ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \
  511. ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \
  512. ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \
  513. ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \
  514. FMPSMBUS_RELOAD_MODE )))
  515. #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \
  516. ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \
  517. ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \
  518. ((REQUEST) == FMPSMBUS_NO_STARTSTOP))
  519. #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
  520. ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \
  521. ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \
  522. ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
  523. ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \
  524. ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \
  525. ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
  526. ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC))
  527. #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \
  528. ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
  529. ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \
  530. ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
  531. #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
  532. (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \
  533. FMPI2C_CR1_PECEN)))
  534. #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
  535. (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
  536. FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
  537. FMPI2C_CR2_RD_WRN)))
  538. #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \
  539. (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
  540. (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \
  541. (~FMPI2C_CR2_RD_WRN)) : \
  542. (uint32_t)((((uint32_t)(__ADDRESS__) & \
  543. (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \
  544. (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
  545. #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U)
  546. #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)
  547. #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
  548. #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE)
  549. #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN)
  550. #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \
  551. ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET)
  552. #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
  553. #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
  554. #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
  555. /**
  556. * @}
  557. */
  558. /* Include FMPSMBUS HAL Extended module */
  559. #include "stm32f4xx_hal_fmpsmbus_ex.h"
  560. /* Exported functions --------------------------------------------------------*/
  561. /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions
  562. * @{
  563. */
  564. /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
  565. * @{
  566. */
  567. /* Initialization and de-initialization functions ****************************/
  568. HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  569. HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  570. void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  571. void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  572. HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter);
  573. HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter);
  574. /* Callbacks Register/UnRegister functions ***********************************/
  575. #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
  576. HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
  577. HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
  578. pFMPSMBUS_CallbackTypeDef pCallback);
  579. HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
  580. HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
  581. HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
  582. pFMPSMBUS_AddrCallbackTypeDef pCallback);
  583. HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  584. #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
  585. /**
  586. * @}
  587. */
  588. /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions
  589. * @{
  590. */
  591. /* IO operation functions *****************************************************/
  592. /** @addtogroup Blocking_mode_Polling Blocking mode Polling
  593. * @{
  594. */
  595. /******* Blocking mode: Polling */
  596. HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials,
  597. uint32_t Timeout);
  598. /**
  599. * @}
  600. */
  601. /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
  602. * @{
  603. */
  604. /******* Non-Blocking mode: Interrupt */
  605. HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
  606. uint8_t *pData, uint16_t Size, uint32_t XferOptions);
  607. HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
  608. uint8_t *pData, uint16_t Size, uint32_t XferOptions);
  609. HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
  610. HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
  611. uint32_t XferOptions);
  612. HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
  613. uint32_t XferOptions);
  614. HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  615. HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  616. HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  617. HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  618. /**
  619. * @}
  620. */
  621. /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
  622. * @{
  623. */
  624. /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
  625. void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  626. void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  627. void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  628. void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  629. void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  630. void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  631. void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
  632. void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  633. void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  634. /**
  635. * @}
  636. */
  637. /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
  638. * @{
  639. */
  640. /* Peripheral State and Errors functions **************************************************/
  641. uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  642. uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus);
  643. /**
  644. * @}
  645. */
  646. /**
  647. * @}
  648. */
  649. /* Private Functions ---------------------------------------------------------*/
  650. /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions
  651. * @{
  652. */
  653. /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */
  654. /**
  655. * @}
  656. */
  657. /**
  658. * @}
  659. */
  660. /**
  661. * @}
  662. */
  663. /**
  664. * @}
  665. */
  666. #endif /* FMPI2C_CR1_PE */
  667. #ifdef __cplusplus
  668. }
  669. #endif
  670. #endif /* STM32F4xx_HAL_FMPSMBUS_H */