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TrainCamp_fubowen_Modbus/cmsis/core_cm4_simd.h

652 wiersze
20 KiB
Czysty Wina Historia 

  1. /**

  2.  *******************************************************************************

  3.  * @file     core_cm4_simd.h

  4.  * @brief    CMSIS Cortex-M4 SIMD Header File

  5.  * @version  V3.01

  6.  * @date     06. March 2012

  7.  *

  8.  * @note

  9.  * Copyright (C) 2010-2012 ARM Limited. All rights reserved.

  10.  *

  11.  * @par

  12.  * ARM Limited (ARM) is supplying this software for use with Cortex-M

  13.  * processor based microcontrollers.  This file can be freely distributed

  14.  * within development tools that are supporting such ARM based processors.

  15.  *

  16.  * @par

  17.  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

  18.  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

  19.  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

  20.  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

  21.  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

  22.  *

  23.  ******************************************************************************/

  24. 

  25. #ifndef __CORE_CM4_SIMD_H

  26. #define __CORE_CM4_SIMD_H

  27. 

  28. #ifdef __cplusplus

  29.  extern "C" {

  30. #endif

  31. 

  32. 

  33. 

  34. /*******************************************************************************

  35.  *                Hardware Abstraction Layer

  36.  ******************************************************************************/

  37. 

  38. 

  39. /* ###################  Compiler specific Intrinsics  ########################### */

  40. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics

  41.   Access to dedicated SIMD instructions

  42.   @{

  43. */

  44. 

  45. #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/

  46. /* ARM armcc specific functions */

  47. 

  48. /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

  49. #define __SADD8                           __sadd8

  50. #define __QADD8                           __qadd8

  51. #define __SHADD8                          __shadd8

  52. #define __UADD8                           __uadd8

  53. #define __UQADD8                          __uqadd8

  54. #define __UHADD8                          __uhadd8

  55. #define __SSUB8                           __ssub8

  56. #define __QSUB8                           __qsub8

  57. #define __SHSUB8                          __shsub8

  58. #define __USUB8                           __usub8

  59. #define __UQSUB8                          __uqsub8

  60. #define __UHSUB8                          __uhsub8

  61. #define __SADD16                          __sadd16

  62. #define __QADD16                          __qadd16

  63. #define __SHADD16                         __shadd16

  64. #define __UADD16                          __uadd16

  65. #define __UQADD16                         __uqadd16

  66. #define __UHADD16                         __uhadd16

  67. #define __SSUB16                          __ssub16

  68. #define __QSUB16                          __qsub16

  69. #define __SHSUB16                         __shsub16

  70. #define __USUB16                          __usub16

  71. #define __UQSUB16                         __uqsub16

  72. #define __UHSUB16                         __uhsub16

  73. #define __SASX                            __sasx

  74. #define __QASX                            __qasx

  75. #define __SHASX                           __shasx

  76. #define __UASX                            __uasx

  77. #define __UQASX                           __uqasx

  78. #define __UHASX                           __uhasx

  79. #define __SSAX                            __ssax

  80. #define __QSAX                            __qsax

  81. #define __SHSAX                           __shsax

  82. #define __USAX                            __usax

  83. #define __UQSAX                           __uqsax

  84. #define __UHSAX                           __uhsax

  85. #define __USAD8                           __usad8

  86. #define __USADA8                          __usada8

  87. #define __SSAT16                          __ssat16

  88. #define __USAT16                          __usat16

  89. #define __UXTB16                          __uxtb16

  90. #define __UXTAB16                         __uxtab16

  91. #define __SXTB16                          __sxtb16

  92. #define __SXTAB16                         __sxtab16

  93. #define __SMUAD                           __smuad

  94. #define __SMUADX                          __smuadx

  95. #define __SMLAD                           __smlad

  96. #define __SMLADX                          __smladx

  97. #define __SMLALD                          __smlald

  98. #define __SMLALDX                         __smlaldx

  99. #define __SMUSD                           __smusd

  100. #define __SMUSDX                          __smusdx

  101. #define __SMLSD                           __smlsd

  102. #define __SMLSDX                          __smlsdx

  103. #define __SMLSLD                          __smlsld

  104. #define __SMLSLDX                         __smlsldx

  105. #define __SEL                             __sel

  106. #define __QADD                            __qadd

  107. #define __QSUB                            __qsub

  108. 

  109. #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \

  110.                                            ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )

  111. 

  112. #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \

  113.                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )

  114. 

  115. 

  116. /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

  117. 

  118. 

  119. 

  120. #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/

  121. /* IAR iccarm specific functions */

  122. 

  123. /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

  124. #include <cmsis_iar.h>

  125. 

  126. /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

  127. 

  128. 

  129. 

  130. #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

  131. /* TI CCS specific functions */

  132. 

  133. /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

  134. #include <cmsis_ccs.h>

  135. 

  136. /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

  137. 

  138. 

  139. 

  140. #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/

  141. /* GNU gcc specific functions */

  142. 

  143. /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

  144. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)

  145. {

  146.   uint32_t result;

  147. 

  148.   __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  149.   return(result);

  150. }

  151. 

  152. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)

  153. {

  154.   uint32_t result;

  155. 

  156.   __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  157.   return(result);

  158. }

  159. 

  160. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)

  161. {

  162.   uint32_t result;

  163. 

  164.   __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  165.   return(result);

  166. }

  167. 

  168. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)

  169. {

  170.   uint32_t result;

  171. 

  172.   __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  173.   return(result);

  174. }

  175. 

  176. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)

  177. {

  178.   uint32_t result;

  179. 

  180.   __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  181.   return(result);

  182. }

  183. 

  184. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)

  185. {

  186.   uint32_t result;

  187. 

  188.   __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  189.   return(result);

  190. }

  191. 

  192. 

  193. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)

  194. {

  195.   uint32_t result;

  196. 

  197.   __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  198.   return(result);

  199. }

  200. 

  201. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)

  202. {

  203.   uint32_t result;

  204. 

  205.   __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  206.   return(result);

  207. }

  208. 

  209. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)

  210. {

  211.   uint32_t result;

  212. 

  213.   __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  214.   return(result);

  215. }

  216. 

  217. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)

  218. {

  219.   uint32_t result;

  220. 

  221.   __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  222.   return(result);

  223. }

  224. 

  225. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)

  226. {

  227.   uint32_t result;

  228. 

  229.   __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  230.   return(result);

  231. }

  232. 

  233. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)

  234. {

  235.   uint32_t result;

  236. 

  237.   __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  238.   return(result);

  239. }

  240. 

  241. 

  242. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)

  243. {

  244.   uint32_t result;

  245. 

  246.   __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  247.   return(result);

  248. }

  249. 

  250. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)

  251. {

  252.   uint32_t result;

  253. 

  254.   __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  255.   return(result);

  256. }

  257. 

  258. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)

  259. {

  260.   uint32_t result;

  261. 

  262.   __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  263.   return(result);

  264. }

  265. 

  266. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)

  267. {

  268.   uint32_t result;

  269. 

  270.   __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  271.   return(result);

  272. }

  273. 

  274. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)

  275. {

  276.   uint32_t result;

  277. 

  278.   __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  279.   return(result);

  280. }

  281. 

  282. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)

  283. {

  284.   uint32_t result;

  285. 

  286.   __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  287.   return(result);

  288. }

  289. 

  290. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)

  291. {

  292.   uint32_t result;

  293. 

  294.   __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  295.   return(result);

  296. }

  297. 

  298. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)

  299. {

  300.   uint32_t result;

  301. 

  302.   __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  303.   return(result);

  304. }

  305. 

  306. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)

  307. {

  308.   uint32_t result;

  309. 

  310.   __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  311.   return(result);

  312. }

  313. 

  314. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)

  315. {

  316.   uint32_t result;

  317. 

  318.   __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  319.   return(result);

  320. }

  321. 

  322. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)

  323. {

  324.   uint32_t result;

  325. 

  326.   __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  327.   return(result);

  328. }

  329. 

  330. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)

  331. {

  332.   uint32_t result;

  333. 

  334.   __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  335.   return(result);

  336. }

  337. 

  338. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)

  339. {

  340.   uint32_t result;

  341. 

  342.   __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  343.   return(result);

  344. }

  345. 

  346. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)

  347. {

  348.   uint32_t result;

  349. 

  350.   __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  351.   return(result);

  352. }

  353. 

  354. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)

  355. {

  356.   uint32_t result;

  357. 

  358.   __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  359.   return(result);

  360. }

  361. 

  362. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)

  363. {

  364.   uint32_t result;

  365. 

  366.   __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  367.   return(result);

  368. }

  369. 

  370. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)

  371. {

  372.   uint32_t result;

  373. 

  374.   __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  375.   return(result);

  376. }

  377. 

  378. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)

  379. {

  380.   uint32_t result;

  381. 

  382.   __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  383.   return(result);

  384. }

  385. 

  386. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)

  387. {

  388.   uint32_t result;

  389. 

  390.   __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  391.   return(result);

  392. }

  393. 

  394. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)

  395. {

  396.   uint32_t result;

  397. 

  398.   __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  399.   return(result);

  400. }

  401. 

  402. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)

  403. {

  404.   uint32_t result;

  405. 

  406.   __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  407.   return(result);

  408. }

  409. 

  410. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)

  411. {

  412.   uint32_t result;

  413. 

  414.   __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  415.   return(result);

  416. }

  417. 

  418. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)

  419. {

  420.   uint32_t result;

  421. 

  422.   __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  423.   return(result);

  424. }

  425. 

  426. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)

  427. {

  428.   uint32_t result;

  429. 

  430.   __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  431.   return(result);

  432. }

  433. 

  434. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)

  435. {

  436.   uint32_t result;

  437. 

  438.   __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  439.   return(result);

  440. }

  441. 

  442. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)

  443. {

  444.   uint32_t result;

  445. 

  446.   __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  447.   return(result);

  448. }

  449. 

  450. #define __SSAT16(ARG1,ARG2) \

  451. ({                          \

  452.   uint32_t __RES, __ARG1 = (ARG1); \

  453.   __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

  454.   __RES; \

  455.  })

  456. 

  457. #define __USAT16(ARG1,ARG2) \

  458. ({                          \

  459.   uint32_t __RES, __ARG1 = (ARG1); \

  460.   __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \

  461.   __RES; \

  462.  })

  463. 

  464. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)

  465. {

  466.   uint32_t result;

  467. 

  468.   __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));

  469.   return(result);

  470. }

  471. 

  472. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)

  473. {

  474.   uint32_t result;

  475. 

  476.   __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  477.   return(result);

  478. }

  479. 

  480. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)

  481. {

  482.   uint32_t result;

  483. 

  484.   __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));

  485.   return(result);

  486. }

  487. 

  488. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)

  489. {

  490.   uint32_t result;

  491. 

  492.   __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  493.   return(result);

  494. }

  495. 

  496. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)

  497. {

  498.   uint32_t result;

  499. 

  500.   __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  501.   return(result);

  502. }

  503. 

  504. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)

  505. {

  506.   uint32_t result;

  507. 

  508.   __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  509.   return(result);

  510. }

  511. 

  512. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)

  513. {

  514.   uint32_t result;

  515. 

  516.   __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  517.   return(result);

  518. }

  519. 

  520. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)

  521. {

  522.   uint32_t result;

  523. 

  524.   __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  525.   return(result);

  526. }

  527. 

  528. #define __SMLALD(ARG1,ARG2,ARG3) \

  529. ({ \

  530.   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

  531.   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

  532.   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

  533.  })

  534. 

  535. #define __SMLALDX(ARG1,ARG2,ARG3) \

  536. ({ \

  537.   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \

  538.   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

  539.   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

  540.  })

  541. 

  542. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)

  543. {

  544.   uint32_t result;

  545. 

  546.   __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  547.   return(result);

  548. }

  549. 

  550. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)

  551. {

  552.   uint32_t result;

  553. 

  554.   __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  555.   return(result);

  556. }

  557. 

  558. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)

  559. {

  560.   uint32_t result;

  561. 

  562.   __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  563.   return(result);

  564. }

  565. 

  566. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)

  567. {

  568.   uint32_t result;

  569. 

  570.   __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );

  571.   return(result);

  572. }

  573. 

  574. #define __SMLSLD(ARG1,ARG2,ARG3) \

  575. ({ \

  576.   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

  577.   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

  578.   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

  579.  })

  580. 

  581. #define __SMLSLDX(ARG1,ARG2,ARG3) \

  582. ({ \

  583.   uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \

  584.   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \

  585.   (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \

  586.  })

  587. 

  588. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)

  589. {

  590.   uint32_t result;

  591. 

  592.   __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  593.   return(result);

  594. }

  595. 

  596. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)

  597. {

  598.   uint32_t result;

  599. 

  600.   __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  601.   return(result);

  602. }

  603. 

  604. __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)

  605. {

  606.   uint32_t result;

  607. 

  608.   __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );

  609.   return(result);

  610. }

  611. 

  612. #define __PKHBT(ARG1,ARG2,ARG3) \

  613. ({                          \

  614.   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

  615.   __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

  616.   __RES; \

  617.  })

  618. 

  619. #define __PKHTB(ARG1,ARG2,ARG3) \

  620. ({                          \

  621.   uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \

  622.   if (ARG3 == 0) \

  623.     __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \

  624.   else \

  625.     __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \

  626.   __RES; \

  627.  })

  628. 

  629. /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

  630. 

  631. 

  632. 

  633. #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/

  634. /* TASKING carm specific functions */

  635. 

  636. 

  637. /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/

  638. /* not yet supported */

  639. /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/

  640. 

  641. 

  642. #endif

  643. 

  644. /*@} end of group CMSIS_SIMD_intrinsics */

  645. 

  646. 

  647. #ifdef __cplusplus

  648. }

  649. #endif

  650. 

  651. #endif /* __CORE_CM4_SIMD_H */